JPH0216738A - Manufacture of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a heterojunction bipolar transistor(HBT) having a planar structure by causing an emitter and the surface of an external base to be in a level plane and arranging even the surface of an external collector on the level plane. CONSTITUTION:A stepped part corresponding to the thickness of an emitter layer is formed on the surface of a GaAs semiinsulating semiconductor substrate 1. Then, a collector layer consisting of n-type GaAs and a base consisting of p-type GaAs are laminated one by one on the substrate 1 comprising the stepped part. Further, the emitter layer 4 consisting of n-type Al0.3Ga0.7As grows selectively on the surface of the stepped part as well as on the surface of a substrate part which is lower than the stepped part. The emitter layer 4 and the base layer 3 are thus on the level plane. Then an external collector 6 is formed by injecting Si in the base layer through an ion implantation process. Moreover, an insulating region 7 is formed by implanting H<+> ions and finally, a collector electrode is formed on the external collector 6 which is on the level plane and then, base and emitter electrodes 8 and 9 are formed on base and emitter layers 3 and 4 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a heterojunction bipolar transistor with a brainer structure.

[Conventional technology]

A heterojunction bipolar transistor (HBT) is a device that is expected to operate faster than conventional silicon transistors. The conventional HBT structure has mesas in some form, and the surface of the element is uneven. The manufacturing method is, for example, on a compound semiconductor substrate such as GaAs,
The semiconductor layers that become the collector, base and emitter are MO
Epitaxial growth is performed sequentially using a CVD method, and then mesa etching is performed using a photolithography technique.

[Problem to be solved by the invention]

However, the above structure has a problem in that the unevenness of the element surface tends to cause disconnections in the wiring, making it difficult to integrate it into an IC.

[Means to solve the problem]

The present invention has been made in view of the above points.
The purpose is to provide a preferable manufacturing method for an HBT having a brainer structure that eliminates surface irregularities. In a method for manufacturing a heterojunction bipolar transistor, which includes a step of sequentially epitaxially growing semiconductor layers that will become the collector, base, and emitter to form a heterojunction, a portion of the semiconductor substrate is preliminarily grown to the same thickness as the emitter layer or collector layer. etching, then laminating a collector layer or emitter layer on the semiconductor substrate, then epitaxially growing a base layer, and then growing an emitter layer or collector layer on the etched portion of the semiconductor substrate. This is a method for manufacturing a heterojunction bipolar transistor characterized by the following.

[Effect]

According to the above manufacturing method, the part of the semiconductor substrate on which the emitter layer is laminated is etched thinner than other parts by the thickness of the emitter layer, so when the emitter layer is laminated, there is a gap between the emitter and the external base. If the surfaces are on the same level plane and the external collector surface is also formed on said plane,
The three surfaces are aligned on the same level, and the H of the Brenna structure
You can get BT.

〔Example〕

The present invention will be described below based on embodiments shown in the drawings.

FIGS. 1(a) to (d) show NPN type HB according to the present invention.
It is a process explanatory drawing of one Example of the manufacturing method of T. According to this embodiment, first, a GaAs semi-insulating semiconductor substrate (1)
A part of the etching layer is masked with a Sigh dielectric film, and a step of approximately 0.2μ, which corresponds to the thickness of the emitter layer, is formed on the surface of the semi-insulating semiconductor substrate (1) by wet etching. n-C on the semi-insulating semiconductor substrate (1)
A collector layer made of yaAs and a base layer made of p-CaAs are sequentially laminated. As shown in FIG. ! (5), and on the step surface and the semi-insulating semiconductor substrate (1) surface lower than the step, n Al1o,
An emitter layer (4) made of 5Gao and qAS is selectively grown. The surface of the emitter layer (4) thus formed is at the same level as the surface of the base layer (3) formed on the surface of the semi-insulating semiconductor substrate (1) which is higher than the step.
Next, after removing the dielectric film (5), Si ions are selectively implanted into the base layer to reach the collector layer (2) to form an external collector (6).

Furthermore, an insulating region (7) is formed by implanting H ions outside the region including the external collector (6) and the step, and finally,
A collector electrode (8) is formed on the external collector (6) on the same level plane, a base electrode (9) is formed on the base N (3), and an emitter electrode 0ω is formed on the emitter layer (4) to form a planar structure. Get IBT.

In addition, as another example, as shown in FIG. 2(a), 0), after forming the emitter layer (4) in the above example
Figure (C)), emitter layer (4) and external base layer (3')
The surface of the external collector is covered with a dielectric film 00, and a hole (121) for the external collector is etched to a depth that reaches the collector in the external base layer (3').Next, the external collector is selectively grown to form a dielectric The body WA00 is removed.Finally, H ions are implanted on both sides of the element to form an insulating region (7), and a collector electrode (8), a base electrode (9) and an emitter electrode 0[I] are formed. It is also possible to obtain an HBT with a planar structure. In addition, although the above-mentioned embodiment shows the case of an NPN type transistor, the case of a PNP type transistor may also be used. Further, in the present invention, a structure may be adopted in which the emitter layer is formed on the substrate side and the collector layer is formed on the surface side.

〔Effect of the invention〕

As explained above, according to the present invention, a part of the semiconductor substrate is etched in advance to the same thickness as the emitter layer or collector layer, then the collector layer or emitter layer is laminated on the semiconductor substrate, and then the base layer is etched. HBT with a brainer structure to grow layers and then grow an emitter or collector layer on the etched portion of the semiconductor substrate.
It has the excellent effect of being able to manufacture efficiently.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) show the NPN type HB according to the present invention.
A process explanatory diagram of an example of the method for manufacturing T, FIG. 2(a),
[Yes]) is a process explanatory diagram of another example. l... Semi-insulating semiconductor substrate, 2... Collector layer,
3...Base layer, 3'...External base layer, 4.
...Emitter layer, 5.11...Dielectric film, 6.1
3...External collector, 7...Insulating area, 8
...Collector electrode, 9...Base electrode, 10
... Emitter electrode, 12 ... Hole for external collector.

Claims (1)

[Claims] In a method for manufacturing a heterojunction bipolar transistor, which includes a step of epitaxially growing semiconductor layers to become a collector, a base, and an emitter on a semiconductor substrate so that at least one of an emitter-base junction and a collector-base junction becomes a heterojunction, A part of the semiconductor substrate is etched to the same thickness as the emitter layer or collector layer, then the collector layer or emitter layer is laminated on the semiconductor substrate, then the base layer is epitaxially grown, and then the semiconductor substrate is etched. A method for manufacturing a heterojunction bipolar transistor, comprising the step of growing an emitter layer or a collector layer on an etched portion.