JPH01215065A - Heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To increase working speed by forming a semiconductor layer having a band gap larger than an emitter region or a collector region and an external base region between the emitter or collector region and the external base region. CONSTITUTION:An external base 56 and an emitter region 49 are shaped while the side faces of one sides thereof are faced oppositely, a Ga0.52In0.48P layer 50 having a band gap Eg larger than these regions 56 and 49 is formed between the external base region 56 and the emitter region 49 in the side faces of the regions 56 and 49, and buffer layer 42 composed of semi-insulating AlGaAs is shaped under the external base region 56 and a sub-emitter region 47. Since an intrinsic base region 59 and a collector region 58 in width W2 (<W3, W1) are formed so as to include the boundary of an intrinsic emitter region 48 and the external base region 56, the external base region 56 and the intrinsic base region 59 are brought into contact on one sides, and the width W2 of the intrinsic base region 59 is made smaller than that W3 of the external base region 56. Accordingly, base recombination currents, emitter resistance and emitter capacitance are reduced when the title bipolar transistor is manufactured in a collector-top type, and collector breakdown strength is increased and collector capacitance can be lowered when the bipolar transistor is produced in an emitter-top type.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a heterojunction bipolar transistor.

(Summary of the Invention) The present invention provides a heterojunction bipolar transistor in which an emitter or collector region and an external base region are formed so as to face each other on their sides, and the emitter or collector region and the external base region are interposed between the emitter or collector region and the external base region. By forming a semiconductor layer with a larger bandgap, forming an intrinsic base region on a region including the boundary between the emitter or collector region and the extrinsic base region, and forming a collector or emitter region on the intrinsic base region, high-speed In addition, the collector-top type aims to reduce base recombination current, reduce emitter cracking, and reduce parasitic emitter capacitance, and the emitter-top type aims to improve collector breakdown voltage and reduce parasitic collector capacitance. This is what I did.

[Conventional technology]

A heterojunction bipolar transistor is a transistor that can overcome the drawbacks of a homojunction bipolar transistor made of silicon or the like. That is, taking a heterojunction bipolar transistor using A9GaAs for the emitter (E) and GaAs for the base (B) and collector (C) as an example, the holes, which are the majority carriers in the base, are Bandgap difference between E − B (Δ
Eg) cannot diffuse into the emitter due to the energy barrier, the base current decreases, and the efficiency of electron injection from the emitter to the base increases. Therefore, even if the base concentration is increased and the emitter concentration is decreased, the degree of amplification will decrease β-I
C./18) can be increased.

This means that the base resistance and E-B junction capacitance, which are related to high speed performance, can be reduced, and it has been shown both theoretically and experimentally that the transistor is faster than a silicon bipolar transistor.

The ffllO diagram is a typical structure of an AQ GaAs layer GaAs brainer type heterojunction bipolar transistor that makes full use of ion implantation technology≧metal embedding technology. An example of a method for manufacturing a transistor (13) having this structure will be briefly described.

On a semi-insulating GaAs substrate (1), an n''-GaAs layer which becomes a collector electrode extraction layer (2) and a collector region (3) are sequentially formed.
The n-GaAs layer becomes the base region (i.e., the intrinsic base region) (4), the P GaAs layer becomes the emitter region (4), and the emitter region (
5) n-AQ GaAs layer and key? 7 layers (6
) After epitaxially growing an n-GaAsJm, n''-GaAs layer, the n''-GaAs cap layer (6) was etched away leaving an emitter region, and Mg was ion-implanted using 5ilh as a mask.
An external base region (7) is formed by annealing. Next, an element isolation region (8) and a base/collector isolation region (9) are formed by boron or H+ ion implantation. i (h layer (lO)
A transistor (13) is manufactured by opening a window, forming a trench (11), and filling the trench (11) with a metal (12). (14) is a base electrode, (15) is an emitter electrode, and (16) is a collector electrode.

On the other hand, as shown in FIG. 11, a so-called collector-l-tube type heterojunction bipolar transistor (17) in which the collector region is on the surface 1-side is also being considered. The procedure for manufacturing this collector-top type heterojunction bipolar transistor is basically the same as the emitter-L-tube type heterojunction bipolar transistor (13) in Figure 10, except that the epitaxy order is changed. It is. In Fig. 11, parts corresponding to Fig. 1θ are given the same reference numerals;
(18) is 11” GaAs which becomes the emitter electrode extraction layer.
layer, (5) is n-AQGa^3 layer which becomes the engineering region,
(4) is a p-GaAs layer which becomes a base region, (3) is an n"-GaAs layer which becomes a collector region, (19) is an n"-GaAs layer which becomes a collector cap layer, and (7) is an external base region. .

The switching time τ3 of the heterojunction bipolar transistor is given by: However, Rh? Base resistance, Cc: base-collector capacitance, RL: load resistance, CL: load capacitance, τb: base passage time. Therefore, in order to reduce τS, it is necessary to reduce Rh and Cc. In general, collector-top type heterojunction bipolar transistors are more advantageous in reducing Cc than emitter-top type heterojunction bipolar transistors, and are therefore considered to have higher speed performance. That is, (i) the collector-top type heterojunction bipolar transistor has a small collector area, so the collector-base junction capacitance is small;
It is advantageous for high speed. On the other hand, the emitter area is large (as a result, the emitter-base capacitance becomes large. This is a disadvantage, but the emitter-base is a heterojunction, which is smaller than a homojunction. Also, the emitter concentration is Since the emitter junction capacitance is small, the emitter junction capacitance is essentially small and does not pose a major problem.However, the advantage of reducing the collector capacitance is far greater, and published simulations show that the collector top type is faster.

(1!) From a circuit perspective, in the case of ECL (emitter coupled logic), the emitters of several transistors are connected in common to form a gate, so n+
By using a common emitter layer without isolation, the device area can be reduced. ' By the way, in the conventional heterojunction type pievora transistor mentioned above, as the area of the device is reduced, the capacitance around the active region, that is, the capacitance of the periphery between the collector and the external base and between the emitter and the external base, becomes relatively large. It gets bigger.

For example, in the collector-top type heterojunction bipolar transistor shown in FIG. 11, the collector area is 1×! μ
Calculating the case of d, the intrinsic partial capacitance is the emitter-base capacitance Cebmi2. ? fF is small at 0.27 fF (assuming a depletion layer of 40 GG people), but the external capacitance, that is, the capacitance only at the periphery, Ccb' and Cbc', is 3.2 fF.

It can be seen that Cbc' Mi 0.5 fl' is quite large.

Therefore, it is desirable to have a structure in which the contribution of the peripheral portion does not become large as the device area is reduced, and such measures have been taken in actual Si-based bipolar transistors.

For example, in a heterojunction bipolar transistor having the configuration shown in FIG. 11, if an attempt is made to reduce the external capacitance, the base contact region becomes smaller, which increases the base contact resistance and limits the speed of the device.

In addition to the above-mentioned points, conventional heterojunction bipolar transistors in which an external base is formed by ion implantation have the following drawbacks.

■) The concentration of the external base region cannot be increased.

(ii) A displacement of the junction position occurs due to the diffusion of implanted impurities into the emitter region and the diffusion of impurities in the intrinsic base region during activation annealing.

(Stripes) The external capacitance of the periphery generated between the emitter external base and between the collector external base becomes relatively large as the device area becomes smaller. In particular, the collector capacity of the periphery cannot be eliminated.

(1v) To take out the collector (or emitter) electrode, formation of a deep trench and metal burying technique are required.

(V) The base and emitter contact areas cannot be increased without increasing the capacitance.

(vi) Among the electrons injected from the emitter region to the intrinsic base region, electrons in the periphery diffuse into the extrinsic base region by the diffusion length (several microns) and recombine with holes, forming an invalid base. Due to the so-called periphery effect resulting in current, the current amplification factor decreases when the element is made smaller.

On the other hand, in Japanese Patent Application No. 62-107352, the present applicant proposed a heterojunction bipolar transistor that can overcome the above drawbacks of the conventional transistor. As shown in FIGS. 8 and 9, this heterojunction bipolar transistor (32)
A wide bandgap undoped A (lGaAs) buffer layer (22) is formed on a semi-insulating GaAs substrate (21).
3) and a sub-emitter region (24), and form an external base region (26) of p''-GaAs in contact with one side of the emitter region (25). A p''-GaAs intrinsic base region (27) and an n-GaAs collector region (28) are formed on the intrinsic emitter region (23) so as to partially straddle the region (26).
) are formed sequentially. In this case, @W 2 in the intrinsic region is smaller than @W in the sub-emitter region (24) and @W3 in the extrinsic base region (26), and on the collector region (28) and on the extrinsic base region (26). A collector electrode (29), a base electrode (30), and an emitter electrode (31) are connected to each other in ohmic contact on the sub-emitter region (24).

This collector top type heterojunction bipolar transistor (32) has the following advantages.

Since the collector region (28) is formed in a mesa shape, no collector capacitance is generated at the periphery, and the collector capacitance includes only an intrinsic collector capacitance.

Therefore, the collector capacitance becomes extremely small.

The external base region (26) is formed of an epitaxial layer having a thickness of, for example, 0.5 .mu.m and an impurity concentration of 2.times.10"cs-' or more, so it is formed by ion implantation into the n-Al1GaAs layer of the conventional structure. , the impurity concentration can be improved by an order of magnitude, and the mobility can also be improved, and the external base resistance becomes small.Also, the external base region (26) hardly contacts the collector region (28), and the emitter region (25) ) are in contact with only 4% i W 2 on one side, so in addition to increasing the impurity concentration of the extrinsic base region (26), the extrinsic base region (26) can be By forming the area of (26) large, it becomes possible to reduce the base contact resistance.The emitter region (25) and the external base region (
The contact with 26) is only within the width W2 of one side surface, and therefore the emitter capacitance is also small.

In addition, as the device area is reduced, the capacitance of the periphery generated between the emitter external base and between the collector external base does not become relatively large, and the base contact resistance can also be reduced, resulting in excellent high-speed performance.
In addition, a heterojunction bipolar transistor that can be easily converted into an IC can be obtained.

Since the structure is such that the emitter region (25) and the external base region (26) are in contact with each other only on one side, electrons injected from the emitter region (25) into the intrinsic base region (27) are transferred to the external base region (26). ) is less likely to spread. This means that the loss of electrons in the periphery is reduced (that is, the periphery effect is reduced in principle), and the active region 1x
Even if it is as small as l#m, a high m current amplification factor can be obtained even in the low current iw4 range.

Semi-insulating GaAs base & (31) and emitter region (25)
and a wide bandgap semi-insulating GaAs buffer layer (22) between the external base region (26) and the external base region (26).
is provided, so that the external base region (26) of p"-GaAs and the emitter m region (26) of n-A9 GaAs are
5), this leakage current can be prevented through the substrate (21) between the two. Furthermore, in this configuration, the base, collector, and emitter are formed almost in a brainer structure (a structure in which the electrodes are taken from the top surface), so there is no need to form a trench for taking out the emitter electrode or collector electrode as in the conventional case. Furthermore, element isolation is automatically performed when forming the collector region by RIE. Ion implantation and annealing techniques are also not required, increasing device reproducibility.

After forming the thick external base region (26), the intrinsic base region (27) is formed by the final epitaxial growth, so the thickness of the intrinsic base region (27) is extremely thin, and even a thickness of 2 to 300 layers, for example, can be manufactured with high precision. At the same time, no misalignment of the joint occurs.

In addition, IEICE journal CVol, Jlo-C11
o, 5PP743-749 May 1987, e.g. AQ
In a GaAs thread heterojunction bipolar transistor, A is applied in the emitter region, base region, or both.
It has been shown that properties can be further improved by creating a gradient in the composition ratio.

[Problem to be solved by the invention]

By the way, although the heterojunction bipolar transistor (32) shown in FIGS. 8 and 9 overcomes the drawbacks of the conventional heterojunction bipolar transistor (17) shown in FIG. Problems were discovered.

(i) The base current between the highly doped external base region (26) and the highly doped sub-emitter region (24) increases.

(1st n-An GaAs sub-emitter region (24
), contact resistance increases because the emitter electrode (31) is formed.

(iii) n constituting the sub-emitter region (24)
- In addition to the fact that the electron concentration of AQGaAs cannot be large (less than the doping concentration), the emitter sheet resistance is high due to its low mobility, and when the self-alignment method is not used, the emitter resistance is slightly reduced, including the effect of (ji). This may result in deterioration of transistor characteristics.

(1v) The parasitic emitter capacitance between the highly doped external base region (26) and the highly doped sub-emitter region (24) is large relative to the contact area.

The present invention provides a heterojunction bipolar transistor that also solves the above-mentioned problems.

[Means to solve the problem]

In the heterojunction bipolar transistor of the present invention, an emitter (or collector) region and an external base region are formed so as to face each other at their sides, and there is a gap between the emitter (or collector) region and the external base region. forming a semiconductor layer with a larger bandgap than them, - on the region containing the emitter (or collector) region and the external base region boundary
That is, an intrinsic base region is formed on a region spanning part of an emitter (or collector) region and a part of an external base region, and a collector (or emitter) region is formed on this intrinsic base region.

The emitter (or collector) region and the external base region may be opposed to each other on one side, for example. The collector (or emitter) region and the intrinsic base region are formed in a mesa structure, around which an insulating layer is formed.

[Effect]

According to the configuration of the present invention described above, it has the advantages of the heterojunction bipolar transistor shown in FIG. 9 described above, and at the same time has the following effects.

In the case of collector-I-tube heterojunction bipolar transistors, the large bandgap semiconductor layer creates a large barrier to electrons and holes between the emitter region and the extrinsic base region, resulting in The base current between the sub-emitter region and the sub-emitter region is reduced. Furthermore, this allows the sub-emitter region to be made of a semiconductor with a small bandgap, such as GaAs, thereby making it possible to reduce the emitter sheet resistance and the contact resistance with the emitter electrode, thereby reducing the emitter resistance. Also, the parasitic emitter capacitance between the external base region and the emitter region is reduced.

In the case of an emitter-top type heterojunction bipolar transistor, the pn between the external base region and the subcollector region
The junction is reverse biased, and normally the reverse breakdown voltage is reduced, but by interposing a semiconductor layer with a large band gap between the external base region and the sub-collector region as in the present invention, the collector breakdown voltage is improved. The volume between the external base area and the sub-collector area is smaller.

(Example) Referring to FIG. 1, an example of a collector top type heterojunction bipolar transistor according to the present invention will be described together with its manufacturing method.

First, as shown in FIG. 1A, an undoped A9a3Gao film with a thickness of 1000 nm,
v As buffer layer (42), which becomes the sub-emitter region, has a thickness of 5000 mm and has an impurity concentration n ” due to separate doping.
n''-GaAs layer (43) of about 10'' cm-3, impurity concentration of about n-5 x 1017 cm-3, thickness 850A
n −AQ xGat − with Affi composition ratio X changed by
A graded composition layer of
(44), impurity concentration nw 5 ×lQ1?
A gradient composition layer of n-Ga1-ylnyAs (i.e., y
A layer with a thickness of 100 A in which the
A gradient composition layer (45) consisting of 100 layers with y=0.15 is grown. The growth temperature is 700°C.

Furthermore, n -Gat-ylnyAs4TI4 diagonal composition layer (
45) A silicon nitride (SIN) layer (46) having a thickness of approximately IGOOA is deposited on the surface by the CVLl method.

Next, as shown in No. 11g1B, a silicon nitride layer (4
After selectively etching 6) so as to leave a portion corresponding to the emitter region, wet etching was performed using a phosphoric acid solution using the remaining silicon nitride layer (46) as a mask to form n-Gat-VlnV83 ( The first graded composition layer (45), the n-AQ x Gat -x As graded composition layer (44), and a portion of the n''-GaAs layer (43) are selectively removed, followed by RIE (reactive ion etching).
A part of the n''-GaAs layer (43) is etched away using a method to form an emitter region (49). AQ GaAs has RI
Since it is difficult to be etched by E, selective etching by RIE is stopped at the buffer layer (42). Note that this RIE is not particularly necessary for device fabrication.
However, if R1k4 is used, the etching depth will be accurate, which is advantageous in terms of device fabrication.

Next, as shown in FIG. 1C, a silicon nitride layer (46) is formed.
Using as a mask, a semiconductor layer with a larger band camp Eg than the emitter region (49) and the rear external base region, that is, a 0-undoped Gaq5i 1 n with a thickness of about 1500 nm is formed.
oKIP layer (about n −10” cm−3) (50
), and then the impurity concentration p which becomes the external base region is grown.
-107u C-3 p”-GaA!1 layer (5
1) is selectively grown to the same height as the silicon nitride layer (46) (ie, approximately 5,000 nm thick). -D M Z n (demethyl zinc) is used as the p-type dopant.

The growth temperature is 650℃.In this example, -OC of the acoustic pressure method is used.
Since the ν0 method was used, Ga1nP was selectively grown, but if the reduced pressure FIocvo method was used, A9GaA could be grown.
Since selective growth is also possible for s, this GalnP layer (5
0) can be functionally replaced with an AQGaAs layer.

Next, as shown in the first diagram, the silicon nitride layer (46) is removed, and after wet etching of about 50A to clean the surface, it is etched to a thickness of 200mm and an impurity concentration of P"5 x 10", which will become the intrinsic base region. p”-Gax where the in composition ratio X changes sequentially from 0.15 to 0.18 at about cm-3
-xlnxAs gradient composition Jim (52), thickness 15
0 A, n-Ga where the In composition ratio X changes sequentially from 0.18 to 0 at an impurity concentration of n-10ttCa1-'.
)-xlnxAs (IJ1 diagonal composition layer (53), thickness 40
00 people, impurity concentration n-101t cs-3 approximately n-
A GaAs layer (54) and an n''-GaAs layer (55) with a thickness of 5,000 mm and an impurity concentration of n = 10'' to serve as the collector cap 1- are sequentially formed. Grow by 1OCVD method. The growth temperature is 650°C. In addition, n”-GaAsJil (
It is said that replacing 55) with a GalnAs layer is effective because it lowers the contact resistance with the bridge metal.
This is not done in this example.

Next, as shown in FIG.
In the RIB, the n''-GaAs layer (55) on the surface side and the
- Selectively remove the GaAs layer (54).

Since the RIE stops at the GalnAs layer (53), the thickness of the next dowel is 350 n-Ga1-xlnxAs layer (53).
3) and p”-Gat-xlnx^3 (IJ oblique composition m
(52) is selectively removed using a phosphoric acid etching solution. 40
A rough etching of 0 to 600 people is sufficient. This exposes the p''-GaAs layer (51) to the surface in the external base region. Subsequently, the p''-GaAs layer (51) is selectively removed by HIE. At this time, RfE is Ga@21 no
, stop at the P layer (50), and then wet-etch again to selectively remove about too many layers of n-Gat-ylnyAs (LJI diagonal composition layer (45) and n-A9xGat-X) in the portion corresponding to the external emitter. The diagonal composition layer (44) is removed to expose the n"-GaAs sub-emitter region (47). This forms an extrinsic base region (56) and an intrinsic emitter region (48).

The selective etching pattern shown in FIG. 1E is shown in FIG. 2 (this is a plan view of the completed device).
The pattern is as shown in . In other words, the square emitter region (49) has a hooked area (
(corresponding to the area of the intrinsic part to be described later), and @W3 (in the illustrated example, W3-), which is larger than w2, is connected to the extension part extending outside the emitter region (49) of this region part.
The pattern has an external base region (56) of W t ).

Next, as shown in FIG. 1F, the n"-GaAs layer (55) on the external base region (56) and
i (54) was selectively removed by HIH, and then wet etching was performed on about 400 people to obtain n -Ga.
a-xlnxAs graded composition layer (53) and p”-Gat
-xlnxAs layer (52) is selectively removed to expose the p''-GaAs layer in the external base region (56).
58) and an intrinsic base region (59) are formed. A base electrode (60) with a thickness of about 5000 mm, an emitter electrode (61) and a collector electrode (62) are formed.
Next, 5i (h layer (63)) is laminated on the entire surface and planarized.
Regarding the formation of the i(h layer (63)), it is possible to use a known technique.Also, a self-alignment technique can be used to form the i(h layer (63)). ^3, which uses a known technique.

In this way, as shown in FIG. 1F and FIG. 56)
and the emitter region (49).
A Ga+HI 110411 P layer (50) with a larger band gap Eg than the external base region (56) and the emitter region (49) is formed.
47) A buffer layer (42) made of semi-insulating AQGaAs is formed below, and includes the boundary between the intrinsic emitter region (48) and the extrinsic base region (56), that is, partially contacts the extrinsic base region (56). Like @W 2 (<W31
The intrinsic base region (59) and collector region (Wl) of
58) is formed, therefore, the extrinsic base region (56) and the intrinsic base region (59) touch at the - side, and @W2 of the intrinsic base region (59) is smaller than the width W3 of the extrinsic base region (56). A desired collector-type heterojunction bipolar transistor (65) is obtained.

The collector-top type heterojunction bipolar transistor (65) having such a configuration has all the advantages of the heterojunction bipolar transistor (32) shown in FIG. 6 described above, although the explanation will be omitted. Furthermore, the collector top type heterojunction bipolar transistor (65) of the present invention
has the following advantages compared to the transistor (32) described above. We will discuss its advantages below.

In the heterojunction bipolar transistor (32) shown in Fig. 6, the sub-emitter region (24) had to be formed with ^Q (:, ahs). This is because, since the regions (24) are in contact, the bandgap Mg of this interface 1a) had to be larger than the bandgap Eg of the interface crest of the intrinsic base region/intrinsic emitter region.

If the sub-emitter region is made of Al1GaAs, the electron concentration cannot be high and the mobility is low, resulting in a high sheet resistance. It also had a considerable effect on the ohmic contact to A9GaAs, causing an increase in emitter resistance. Therefore, it is clear that the sub-emitter region and ohmic contact are preferably made of GaAs, which has a small bandgap.
In 5), since the sub-emitter region (4'O) is formed of GaAs with a small band gap, the sheet resistance and contact resistance are reduced, and as a result, the emitter resistance is reduced.

Next, as shown in FIG. 3, a GalnP layer (50) is provided between the p"-GaAs forming the external base region (56) and the n"-GaAs forming the sub-emitter region (47). Think about what will happen. The band diagram of the section A- in FIG. 3 is as shown in FIG. 4. p side has some p
This is in consideration of the diffusion of the dopant into the GalnP layer (50). Looking at FIG. 4, it can be seen that a large barrier to electrons and holes is created.

The forward diode current is given by the following equation.

1 = l rec + 1 diff where] l rec is the recombination current, I diH is the diffusion current, q is the unit charge, τ is the recombination lifetime, W is the thickness of the depletion layer, ■ is the applied voltage, N^+ND is the acceptor concentration and donor concentration, l and niLp are the diffusion lengths of minority carriers, respectively, and l)n+1)p is the diffusion coefficient.

ni is the intrinsic carrier density, which is a trough specific to the substance, and is multiplied by the following formula.

nl gourd J-long-=ko 4 v 6-1 & /2 ky here? 'Nc, Nv are the effective density of states, and in the case of GaAs, Nc
= 4.7 X 10"c+s-'Nc7
X 10"cm-' For Ga1aP, N c = 9 x 10"cm-"N v =
10"as-'.

Recombination current 1 rec is ni/τ, diffusion current 1 di
In ff, ni''/NL differs depending on the material and its quality, but in particular ni is an amount specific to the material and is closely related to the Eg of the material.For example, n of GaAs
When i is normalized to 1, the ni of Gaqsa l noInP is -1,65 This means that it can be ignored compared to that of GaAs. Figure 5 shows an actually fabricated GaAs pn diode, G ate 1 n
Curve (11) shows the forward diode current of each pn diode in aslP (in the case of a GaAAa diode, curve (11) is in the case of a GaplrmwP diode. The current in Ga1nP is three orders of magnitude higher than that in GaAs. You can see that it is small * AQ o, a Gaat
As pn diodes fall between these. This allows the GalnP layer (50) to be connected to the p"-GaAs external base region (56) and the fl"-GaAs sub-emitter region (47).
), i.e., the external base region (56) and the sub-emitter region (47)
The base recombination current flowing between n”−
The GaAs sub-emitter region (47) may be made to have an infinitely high concentration, thereby lowering the emitter sheet resistance and allowing non-alloy emitter contact.

The GalaP layer (50) creates a pn junction in Ga1nP by dopant diffusion from both sides, but there is a depletion layer of approximately 13,000 degrees. Therefore, the parasitic emitter capacitance in this part, which is originally small due to its small cross-sectional area, is not only a fraction of that of the conventional one, but also because no current flows during operation and the depletion layer does not decrease, the parasitic capacitance decreases. Does not increase.

In this way, the embodiments of FIGS. 1 and 2 can overcome the disadvantages inherent in the heterojunction bipolar transistor (32) described above.

6 and 7 show an embodiment in which the present invention is applied to an emitter-top type heterojunction bipolar transistor. The manufacturing method is shown in Figure 1 and I! fI (12), so the explanation will be omitted. This emitter-top type heterojunction bipolar transistor (87) is an undoped A90.3 Gao, v As on a semi-insulating GaAs substrate (70).
An n''-GaAs sub-collector region (72) is formed through the buffer layer (71).
) on a part of the n-GaAs layer (73) and n''-Gal
An intrinsic collector region (75) is formed by the flAS layer (74). Further, an undoped Ga1nP layer (76) with a large band gap is placed opposite to one side of the intrinsic collector region (75) and the sub-collector region (72).
A p''-GaAs external base region (77) is formed through the intrinsic collector region (75) and a part of the external base region (77). "-GaAspJ diagonal composition layer with five composition layer base region (7B), n-8gGaAs (91 diagonal composition layer (79) and n-AQ GaAs layer (80) emitter region (81), n"-GaAs emitter cap Layers (82) are formed in sequence, and n”-GaA
The emitter voltage & (83) is in the s cap layer (82), p”
- GaAs external base region (77) with base electrode (84)
), a collector electrode (85) is formed in the n''-GaAs sub-collector region (73), respectively.

(86) is the 5i (h layer).

Also in such an emitter-top type heterojunction bipolar transistor (87), the external base region (77)
and the collector area (72) (75) are opposite to each other on only one side, and the external base area (77) and the area (8) are opposite to each other on one side.
1), the collector capacitance and emitter capacitance become small. Furthermore, the external base resistance can be reduced, and the base contact resistance can be reduced without increasing the collector capacitance. Furthermore, since the intrinsic base region is formed by epitaxial growth after the process, the thickness of the intrinsic base region can be made extremely thin, and no displacement of the junction occurs.

On the other hand, the p''-GaAs external base region (77) and the n''-
The undoped Ga1nP layer (76) inserted between the GaAs sub-collector region (72) and the collector region (76) of the previous embodiment
Top type heterojunction bipolar transistor (65)
The role of the GalaP layer (50) is slightly different from that of the GalaP layer (50). The pn junction in this case is reverse biased. Therefore, if the current is applied, the reverse breakdown voltage will be reduced, but the breakdown voltage will be improved by inserting GafnP with a large Eg.

Also, as in the previous embodiment, the capacity of this portion is reduced. It goes without saying that the collector capacitance is almost exclusively in the intrinsic region.

Therefore, ultra-high speed operation is possible.

(Effects of the Invention) According to the present invention described above, by providing a semiconductor layer having a larger band gap between the emitter or collector region and the external base region, the base recombination current is reduced when the emitter or collector region is made into a collector-top type. , the emitter grinding resistor and the emitter capacitance can be made smaller, and when the emitter top type is used, the collector withstand voltage can be improved and the collector space can be made smaller.Therefore, as shown in FIG. The drawbacks inherent in the heterojunction bipolar transistor can be overcome, and a heterojunction bipolar transistor with better high-speed operation can be obtained.

[Brief explanation of the drawing]

S1 Figures A-F are cross-sectional views showing an example of a collector-top type heterojunction bipolar transistor according to the present invention in the order of manufacturing steps, Figure 2 is a plan view of Figure 111F, and Figure 3 is provided for explanation of the present invention. A sectional view of the main part, Figure 4 is A- in Figure 3.
A band diagram of cross section A, FIG. 5 is a Ga
Forward current of ^3 diode and Ga1nP diode -
The electric ratio characteristics diagram, FIGS. 6 and 7 are a cross-sectional view and a plan view showing an example of the emitter-top type heterojunction bipolar transistor according to the present invention, and FIGS. 8 and 9 are the collector as previously proposed.・A cross-sectional view and a plan view of an example of a top-type heterojunction bipolar transistor; FIG. 1O is a cross-sectional view of a conventional emitter-top heterojunction bipolar transistor; FIG. 11 is a conventional collector-top type heterojunction bipolar transistor. 1 is a cross-sectional view of a heterojunction bipolar transistor of FIG. (41) is a semi-insulating GaAs substrate, (42) is a buffer layer, (47) is a sub-emitter region, (48) is an intrinsic emitter region, (50) is a large bandgap semiconductor layer, (56) is an extrinsic base The area (58) is the collector area, and (59) is the intrinsic base area. Plan view of Hidemori Matsukuma original version 1, Figure 2 Book @n14er+t1. BMIHI*13*H11tl
Hi1fflFigure 3 A-Allrl! Figure 4

Claims (1)

[Claims] An emitter or collector region and an external base region are formed so as to face each other on their sides, and a semiconductor layer having a larger band gap than the emitter or collector region and the external base region is provided between the emitter or collector region and the external base region. . A heterojunction bipolar transistor, wherein an intrinsic base region is formed on a region including a boundary between the emitter or collector region and the external base region, and a collector or emitter region is formed on the intrinsic base region.