KR960006751B1 - Hetero-junction bipolar transistor and the manufacturing method thereof - Google Patents

Abstract

The method of fabricating a hetero-junction bipolar transistor includes the steps of forming a sub-collector layer(2) on a GaAs substrate(1), forming a collector layer(3) on the sub-collector layer(2) and implanting p-type impurities to form a high-concentration base layer(4), forming a multiple quantum wells(6c) and potential barrier(6b) alternately on the base layer(4) and forming a AlGaAs layer(6d) thereon, selectively etching the wells(6c) and potential barrier(6b) to expose the base layer(4), forming an emitter resistant contact layer(8) and etching the base layer(4) and collector layer(3) for isolation, and forming a base resistant contact layer(10) on the base layer(4) and forming a collector resistant contact layer(11) on the sub-collector layer(2).

Description

Heterojunction bipolar transistor and method for manufacturing same

(A) and (b) of FIG. 1 show a substrate structure and an energy band structure of a heterojunction bipolar transistor having an abrupt economy.

(A) and (b) of FIG. 2 show a substrate structure and an energy band structure of a heterojunction bipolar transistor having an emitter of a graded structure.

(A) and (b) of FIG. 3 show a substrate structure and an energy band structure of a heterojunction bipolar transistor having a base of a layered structure.

(A) and (b) of FIG. 4 show the substrate structure and the energy band structure of a heterojunction bipolar transistor using a multi-well well base having different thicknesses according to the present invention.

(A) to (h) of FIG. 5 is a manufacturing flowchart of the device substrate according to the present invention.

6 is an enlarged structure of the quantum well base layer having different thicknesses devised by the present invention.

7 (a) to 7 (f) are flowcharts of an element process.

Figure 7 (g) is a completed structure of a heterojunction bipolar transistor using a variety of wells of different thicknesses completed by the present invention.

* Explanation of symbols for main parts of the drawings

1: semi-insulating substrate, 2: secondary collector layer,

3: collector layer, 4: base layer,

5: emitter layer, 6a: well,

6b: potential barrier, 6c: multi-quantum well,

6d: gallium arsenide layer, 6e :: cap layer,

7,9 photoresist (PR), 8: emitter resistive contact layer,

10: base resistive contact layer, 11: collector resistive contact layer.

The present invention relates to a heterojunction bipolar transistor (HBT), and more particularly, to a heterojunction bipolar in which multiple quantum wells having different thicknesses are inserted into an interface between a base layer and an emitter layer. A transistor and a method of manufacturing the same.

In the fabrication of heterojunction bipolar transistors, n-type doping of the emitter layer with a large band gap and p-type doping of the base layer with a small band gap are used to diffuse electrons from the junction surface of the emitter layer toward the base layer and the emitter layer at the base layer. The diffusion of holes toward the depletion layer forms a depletion layer on the contact boundary surface so that an energy band on the boundary surface of the emitter layer is bent to form a band spike that forms a dislocation barrier.

The spikes of the energy bands thus formed serve as a barrier to the flow of electrons from the emitter to the base, thereby reducing the efficiency of the device. Therefore, in the structural design of the heterojunction bipolar transistor, the band spike at the junction boundary must be removed. do.

Accordingly, various methods have been disclosed, such as a method of reducing the band gap until the energy band of the emitter reaches the junction surface of the base and gradually reducing the energy gap of the base bonded to the emitter.

Let's look at the fabricated structure by some of these representative methods.

FIG. 1A illustrates a structure of a most basic heterojunction bipolar transistor, in which an n-type highly doped subcollector layer 2 and an n-type doped collector layer 3 are formed on a semi-insulating substrate 1. The thin p-type base layer 4 is formed on the collector layer 3.

On this p-type base layer 4, an n-type emitter layer 5 which is an electron supply layer is formed.

The energy band structure of this structure is shown in FIG. 1 (b), where it can be seen that the band spike A is formed on the junction surface of the emitter layer and the base layer.

FIG. 2 (a) changes the material composition of the emitter layer 5a in order to eliminate the spike of the energy band generated in the structure of FIG. 1 (a), and thus is close to the junction between the emitter layer 5a and the base layer 4. The lower the energy band, the less the band difference between the two materials in the boundary surface, the energy band structure is shown in Figure 2 (b).

Heterojunction bipolar transistors of this structure can increase the efficiency of the emitter by eliminating spikes, resulting in high current gain.

However, in changing the material composition of the emitter, it is not easy to make the material of the base layer and the material of the emitter layer 5a the same when the base junction surface is reached.

(A) of FIG. 3 also changes the emitter layer 5 from the base layer 4a to the base layer 4a by changing the material composition of the base layer 4a in order to eliminate band spikes at the bonding surface of the emitter layer 5 and the base layer 4a. By extending the composition of the material as it is, the band discontinuity of the bonded surface was eliminated.

In this structure, the gain of the current is improved as well as the gain of the current is increased because the transit time for the electron to pass through the base is shortened by the drift motion of the electron by the quasi-electric field. It is advantageous to the characteristics, and the base width can be made thick, which is advantageous to the process, and there is a difficulty in the manufacturing process due to the change in the band gap like the structure of FIG. 2 (a).

An object of the present invention is to simplify the structure for removing energy band spikes and differences between band gaps generated during heterojunction and to improve the electrical characteristics of the device.

In order to achieve the above object, in the present invention, the thickness of a well is improved by using a molecular beam epitaxy method capable of controlling a steep interface to the monoatomic layer in the emitter boundary region formed from the emitter layer to the base layer. It is characterized by inserting different multi-quantum wells.

The method of the present invention for producing a heterojunction bipolar transistor having the above structure is characterized by adsorbing gallium molecules on the surface of the semi-insulated substrate to form a sub-collector layer, and forming a collector layer on the sub-collector layer. implanting a p-type impurity to grow a high concentration basal layer, forming a multi-quantum well consisting of wells and dislocation barriers on the base layer and forming an aluminum gallium arsenide layer, covering the photoresist layer and etching to the base layer Forming an emitter ohmic contact layer and sequentially etching the base layer and the collector layer for device isolation; forming a base ohmic contact layer on the base layer and collector resistive contact on the subcollector layer. Forming a layer.

As another feature of the method of the present invention, the forming of the multi-quantum well comprises a n-type gallium arsenide having a relatively small energy band gap, a multi-quantum well, and an n-type aluminum gallium arsenide having a relatively large energy band gap. It is formed alternately on the potential barrier.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

(A) of FIG. 4 is sectional drawing which shows the heterojunction structure which concerns on this invention briefly, (b) shows the energy band structure.

As described above, the heterojunction structure to be obtained by the present invention, as shown in FIG. 4 (a), forms a superlattice quantum well 6 between the emitter 5 and the base 5. As shown in Fig. 4 (b), as the width of the quantum well becomes wider, the energy level decreases, so that the width of the quantum well is gradually increased. Connected.

The present invention for obtaining such a structure is shown in Figure 5 (a) to (h).

The manufacturing method of the present invention will now be described in detail with reference to FIG.

First, as shown in FIG. 5A, a semi-insulating gallium arsenide substrate 1 having a clean surface is prepared and placed in a growth chamber of a molecular beam epitaxy (MBE) device, and then arsenic (As) on the surface is released by heat. To prevent this, the surface oxide film is removed by applying heat at 580 ° C. in an arsenic atmosphere.

Gallium molecules are adsorbed on the surface of the engine 1 from which the oxide film has been removed to form an n + subcollector layer 2 as shown in FIG.

At this time, silicon molecules are adsorbed together for the device process to be made later to make a high concentration n-type layer.

In the process of adsorbing the silicon molecules, the temperature of the silicon crucible, which is a silicon molecule generator, is controlled, and the lid of the crucible is opened and closed to supply an appropriate amount of silicon molecules.

After the high concentration sub-collector layer 2 is formed, the collector layer 3, which is an n-type gallium arsenide layer, is formed as shown in FIG.

When the n-type collector layer 3 is formed, the lid of the silicon crucible is closed and the lid of the crucible containing p-type impurity beryllium (Be) is opened. As shown in (d) of FIG. 5, the high concentration p-type base layer 4 is formed. ).

On the base layer 4, as shown in (e) and (f) of FIG. 5, the well 6a of the n-type gallium arsenide layer having a relatively small energy band gap, and the energy band gap are the wells. The potential barrier 6b of the n-type aluminum gallium arsenide layer relatively larger than (6a) is alternately formed.

At this time, the thickness of the gallium arsenide layer of the well 6a gradually decreases toward the upper layer portion, and the aluminum gallium arsenide layer of the dislocation barrier 6b is fixed to a thickness (about 50 GPa or less) through which electrons can sufficiently pass.

In this case, AlGaAs material is used as a material having a high band gap, and GaAs is used as a material having a low band gap. In general, the energy band gap is the sum of the difference between the conduction band and the valence band at the electrically neutral Fermi level. When forming a quantum well, a material with a large band gap becomes a barrier and a material with a low band gap becomes a barrier. do.

That is, in the present inventors, since the bandgap of AlGaAs is much larger than that of GaAs, the AlGaAs layer 6b becomes a barrier and the GaAs layer 6a becomes a well. At this time, InGaAs material may be used as the material of the well.

The multi-quantum well structure of the superlattice (GaAs / AlGaAs superlattice) of the gallium arsenide layer 6a and the aluminum gallium arsenide layer 6b thus formed is shown in Fig. 5G.

On the top of the multi-quantum well 6c of the superlattice structure, the lid of the aluminum crucible is opened to form the aluminum gallium arsenide layer 6d.

Subsequently, a cap layer made of a high concentration of gallium arsenide layer as shown in (h) of FIG. 5 to close the lid of the aluminum crucible to cut off the supply of aluminum molecules and to improve ohmic contact of the emitter layer during device fabrication. (cap layer) 6e is formed.

6 shows an enlarged view of the superlattice structure quantum well base layer of the device substrate manufactured as described above. That is, it shows that the emitter layer 6c is alternately formed of an n-GaAs layer and an n-AlGaAs layer.

7 is a cross-sectional view illustrating a process of manufacturing a bipolar transistor using a substrate manufactured according to the present invention. Referring to this, a method of manufacturing a heterojunction bipolar transistor according to the present invention will be described below.

As shown in FIG. 7A, the photosensitive film 7 is covered and etched to form a raised structure as shown in FIG. 7B to form an emitter layer.

In this case, the device substrate is etched up to the high concentration n-type base layer 4 to be used as the base layer.

Subsequently, the photoresist film 7 is removed, and then the emitter ohmic contact layer 8 is formed as shown in FIG. 7C by a lift-off method.

Then, in order to separate each substrate, the photosensitive film 9 is applied as shown in FIG. 7 (d), and the base layer 4 and the collector layer 3 are sequentially etched to form the same as in FIG. 7 (e). Make.

Subsequently, as shown in FIG. 7F, the resistive contact layer 10 is formed on the base layer 4 by a lift-off method, and the collector resistive contact layer 11 is coated on the subcollector layer 2. Formed by the method, the device fabrication is completed as shown in Fig. 7G.

Accordingly, according to the present invention, the formation of the sub-energy band of the quantum well depends on the shape of the quantum well, but the energy of the electrons in the quantum well depends on the shape of the quantum well. The higher the energy of the electrons in the well, the higher the position of the sub-energy band ("Schrodlnger equation"). Therefore, in the present invention, when the quantum well is inserted between the emitter and the base as shown in FIG. 4 (a), the width of the well is gradually widened from the emitter to the base. As shown in FIG. Even if an energy band spike is formed at the interface between the base layer and the base layer, it is caused by the barrier of the quantum well, so that the electrons are gradually lowered and connected to the base because they exist in the sub energy band in the well.

According to the present invention which inserts multiple quantum wells having different thicknesses at the interface between the base layer and the emitter layer, as described above, the width of the quantum well is gradually changed from the emitter to the junction surface of the base. Is gradually lowered so that the sub-bands of the quantum wells are smoothly connected to the bands of the emitter by the spikes formed at the joint surface.

Therefore, it is possible to eliminate the potential barrier effect of the spike as in the prior art.

The structure of the present invention can obtain a high current gain, can solve the D-X center according to the doping of the bonding surface, can easily adjust the width of the quantum well has the advantage of convenient process.

Claims (5)

In a heterojunction bipolar transistor having a base layer 4 and an emitter layer 5 each formed of materials having different energy band gaps, the base layer 4 is more energy than the material of the emitter layer 5. The band gap is made of a material having a relatively small size, the emitter layer 5 is made of a material having a relatively larger energy band gap than the base layer 4, and the base layer 4 and the emitter layer 5 A plurality of potential barriers 6b formed of a material having a larger energy bandgap than a material forming a well, and a material having a smaller energy bandgap compared to a material forming the potential barrier 6b. A multi-quantum well 6c having a predetermined thickness having a plurality of wells 6a alternately formed therein is inserted, and the plurality of potential barriers 6b are aluminum gallium arsenide layers each having a thickness of about 50 GPa. And the plurality of wells (6a) are gallium arsenide layers each of which is formed to be sequentially thinner from the base side toward the emitter side. In the method of manufacturing a heterojunction bipolar transistor, the surface of the semi-insulating substrate 1 adsorbs gallium molecules to form a sub-collector layer 2 and the collector layer 3 on the sub-collector layer 2. ) And growing a high concentration base layer 4 by injecting p-type impurities, and alternately forming a well and a potential barrier 6b on the base layer 4, The well 6a forms a multi-quantum well 6c having a predetermined thickness, the thickness of which becomes thinner toward the upper layer portion, forming an aluminum gallium arsenide layer 6d thereon, covering the photosensitive film 7 and Etching to the base layer (4), forming an emitter ohmic contact layer (8) and sequentially etching the base layer (4) and the collector layer (3) for device isolation, and the base layer A base ohmic contact layer 10 is formed on (4) and a collector is formed on the subcollector layer (2). A method of manufacturing a heterojunction bipolar transistor comprising the step of forming an ohmic contact layer (l). The method of claim 2, wherein the forming of the multi-quantum well 6c comprises n-type gallium arsenide having a relatively small energy band gap as the well 6a, and forms the well. And alternately forming an n-type aluminum gallium arsenide having a relatively large energy bandgap as a potential barrier (6b) compared to the material to be used. The method according to claim 2, wherein after forming the aluminum gallium arsenide layer 6d on the multi-quantum well 6c, the cap layer 6e is further formed on the aluminum gallium arsenide layer 6d for resistive contact of the emitter layer. Method of manufacturing a heterojunction bipolar transistor comprising a step. 5. The method of claim 4, wherein the forming of the cap layer (6e), in the step of forming the aluminum gallium arsenide layer (6d) to block the molecules of aluminum and to supply only a high concentration of gallium arsenide to the cap layer (6e) of high concentration A method for producing a heterojunction bipolar transistor, characterized in that it is formed of aluminum gallium arsenide.