KR100211940B1 - Epi-layer format0ion method for fabricating pnp/npn cmos hbt - Google Patents
Epi-layer format0ion method for fabricating pnp/npn cmos hbt Download PDFInfo
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- KR100211940B1 KR100211940B1 KR1019960064705A KR19960064705A KR100211940B1 KR 100211940 B1 KR100211940 B1 KR 100211940B1 KR 1019960064705 A KR1019960064705 A KR 1019960064705A KR 19960064705 A KR19960064705 A KR 19960064705A KR 100211940 B1 KR100211940 B1 KR 100211940B1
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 127
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 85
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 230000000295 complement effect Effects 0.000 claims abstract description 13
- 238000000206 photolithography Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 20
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims description 13
- 239000011574 phosphorus Substances 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000002128 reflection high energy electron diffraction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
Abstract
본 발명은 동일 평면상에 Npn과 Pnp AlGaAs/GaAs 이중 접합 바이폴라 트랜지스터(HBT)를 제조하는 방법에 관한 것으로, Npn과 Pnp AlGaAs/GaAs HBT를 동일 평면상에 제작하기 위하여 반절연성 갈륨비소기판(10)을 사진식각법으로 패터닝하여 장방형의 Npn AlGaAs/GaAs HBT 개별소자의 크기를 갖는 돌출부(100)와 오목부(200)를 형성하고, Npn AlGaAs/GaAs HBT의 에피층과, Pnp AlGaAs/GaAs HBT의 에피층을 차례로 증착한 다음, 상기 돌출부 상측에 형성된 Pnp HBT의 에피층을 제거하여 동일평면상에 상보형 HBT의 에피층을 형성한다.The present invention relates to a method for manufacturing an Npn and Pnp AlGaAs / GaAs double junction bipolar transistor (HBT) on the same plane, and to produce a semi-insulating gallium arsenide substrate (10) to fabricate Npn and Pnp AlGaAs / GaAs HBT on the same plane. ) Is patterned by photolithography to form protrusions 100 and recesses 200 having the size of a rectangular Npn AlGaAs / GaAs HBT individual element, an epitaxial layer of Npn AlGaAs / GaAs HBT, and Pnp AlGaAs / GaAs HBT After depositing an epi layer of, the epi layer of the Pnp HBT formed on the protrusions is removed to form an epi layer of the complementary HBT on the same plane.
따라서, 본 발명에 따른 에피층의 형성방법을 HBT의 제조공정에 적용하는 것에 의해 동일평면상에 Npn/Pnp 상보형 HBT를 제조할 수 있다.Therefore, the Npn / Pnp complementary type HBT can be manufactured on the same plane by applying the epitaxial layer formation method which concerns on this invention to the manufacturing process of HBT.
Description
본 발명의 목적은 동일 평면상에 에미터-업구조를 가지는 Npn/Pnp AlGaAs/GaAs 상보형 HBT를 제조하기 위한 에피층 형성방법을 제공하는데 있다,SUMMARY OF THE INVENTION An object of the present invention is to provide an epitaxial layer formation method for producing Npn / Pnp AlGaAs / GaAs complementary HBT having an emitter-up structure on the same plane.
본 발명은 HBT에 관한 것으로, 특히, 동일 평면상에 에미터-업 구조를 가지는 AlGaAs/GaAs 상보형 HBT를 제조하기 위한 에피층 형성방법에 관한 것이다.The present invention relates to an HBT, and more particularly, to an epitaxial layer formation method for producing an AlGaAs / GaAs complementary HBT having an emitter-up structure on the same plane.
일반적으로 에피터-업(emitter-up)구조를 가지는 Npn AlGaAs/GaAs HBT는 제조공정이 간단하고 에미터 주입 효율이 크기 때문에, 대부분의 마이크로 웨이브 개별 소자와, Npn AlGaAs/GaAs HBT를 이용하여 제조되는 아날로그와 디지털 집적회로에 이 구조를 적용하고 있다.In general, Npn AlGaAs / GaAs HBTs having an emitter-up structure are manufactured using most of the microwave discrete devices and Npn AlGaAs / GaAs HBTs because of the simple manufacturing process and high emitter injection efficiency. This structure is applied to analog and digital integrated circuits.
또한, 상술한 에미터-업구조를 가지는 Pnp AlGaAs/GaAs HBT의 경우에도 제조공정이 간단하고, 에미터 주입효율이 크기 때문에 마이크로 웨이브 개별소자도 이 구조를 적용하고 있다.In addition, even in the case of the Pnp AlGaAs / GaAs HBT having the emitter-up structure described above, the microwave individual device also applies the structure because the manufacturing process is simple and the emitter injection efficiency is high.
그러나, Npn과 Pnp AlGaAs/GaAs HBT를 동일 평면상에 제조하는 것은 에피 구조와 그 제작공정이 복잡하기 때문에 제조공정상 어려움이 있었다.However, the manufacturing of Npn and Pnp AlGaAs / GaAs HBT on the same plane has difficulty in manufacturing process because the epi structure and its manufacturing process are complicated.
본 발명의 목적은 Npn과 Pnp AlGaAs/GaAs HBT를 동일평면상에 형성하는 상보형 HBT를 제조하기 위한 에피층의 형성방법을 제공하는데 있다. 상기 목적을 달성하기 위한 본 발명은 반절연성 갈륨비소기판을 사진식각공정으로 패터닝하여 Npn AlGaAs/GaAs HBT 크기를 갖는 돌출부와 Pnp AlGaAs/GaAs HBT 크기를 갖는 오목부를 정의하는 공정과, 상기 기판의 전면에 Npn HBT의 에피층을 형성하는 공정과, 상기 Npn HBT의 에피층상에 Pnp HBT의 에피층을 형성하는 공정과, 상기 돌출부와 상측에 형성된 Pnp HBT의 에피층을 제거하는 공정을 포함한다.An object of the present invention is to provide a method for forming an epitaxial layer for producing a complementary HBT forming Npn and Pnp AlGaAs / GaAs HBT on the same plane. The present invention for achieving the above object is a process of defining a semi-insulating gallium arsenide substrate by a photolithography process to define a projection having a Npn AlGaAs / GaAs HBT size and a recess having a Pnp AlGaAs / GaAs HBT size, and the front surface of the substrate Forming an epitaxial layer of Npn HBT on the epitaxial layer of Npn HBT, a process of forming an epitaxial layer of Pnp HBT on the epitaxial layer of Npn HBT, and removing an epitaxial layer of Pnp HBT formed on the protruding portion and the upper side.
그리고 패터닝된 반절연성 갈륨비소기판(10)상이 1차로 형성되는 Npn HBT의 에피층의 높이는 오목부의 높이와 동일한 높이로 형성된다.In addition, the height of the epitaxial layer of the Npn HBT on which the patterned semi-insulating gallium arsenide substrate 10 is primarily formed is the same as the height of the recess.
예컨데, 본 발명은 Npn과 Pnp AlGaAs/GaAs HBT를 동일평면상에 제작하기 위한 Npn AlGaAs/GaAs HBT와 Pnp AlGaAs/GaAs HBT의 에피층이 동일평면상에 있도록 형성하는 방법을 제공한다.For example, the present invention provides a method of forming an epitaxial layer of Npn AlGaAs / GaAs HBT and Pnp AlGaAs / GaAs HBT for coplanar production of Npn and Pnp AlGaAs / GaAs HBT.
따라서, 본 발명은 사진식각공정으로 반절연성 갈륨비소기판을 Npn AlGaAs/GaAs HBT 개별소자 크기를 갖는 장방형의 돌출부를 형성하는 동시에, Pnp AlGaAs/GaAs HBT의 크기를 갖는 오목부를 형성하고, MBE 성장법으로 Npn AlGaAs/GaAs HBT의 에피층을 성장시킨 후, 연속하여 Pnp AlGaAs/GaAs HBT의 에피층을 성장시키고, 돌출부 상측에 형성된 Npn AlGaAs/GaAs HBT의 에피층상에 있는 여분의 Pnp AlGaAs/GaAs HBT의 에피층을 제거하는 것에 의해 Npn과 Pnp AlGaAs/GaAs 상보형 HBT의 에피층을 동일평면상에 형성할 수 있다.Accordingly, the present invention forms a semi-insulating gallium arsenide substrate by the photolithography process to form a rectangular protrusion having a size of the Npn AlGaAs / GaAs HBT individual element, and at the same time to form a recess having a size of Pnp AlGaAs / GaAs HBT, MBE growth method After growing the epitaxial layer of Npn AlGaAs / GaAs HBT, the epitaxial layer of Pnp AlGaAs / GaAs HBT was successively grown, and the excess Pnp AlGaAs / GaAs HBT on the epitaxial layer of Npn AlGaAs / GaAs HBT formed on the protrusions By removing the epitaxial layer, an epitaxial layer of Npn and Pnp AlGaAs / GaAs complementary HBT can be formed on the same plane.
본 발명의 실시예에 따른 반도체 소자의 제조방법은 첨부한 도면을 참조한 이하의 상세한 설명으로부터 명백해질 것이다.A method of manufacturing a semiconductor device according to an embodiment of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.
제1도는 Npn AlGaAs/GaAs HBT 개별소자의 크기를 갖는 돌출부와 Pnp AlGaAs/GaAs HBT 개별소자의 크기를 갖는 오목부를 수직하게 화학 식각한 후 갈륨비소기판의 단면도.FIG. 1 is a cross-sectional view of a gallium arsenide substrate after chemical etching of a projection having a size of an Npn AlGaAs / GaAs HBT individual device and a recess having a size of a Pnp AlGaAs / GaAs HBT individual device.
제2도는 화학식각된 갈륨비소기판상에 Npn AlGaAs/GaAs HBT 의 에피층을 성장시킨 후의 단면도.2 is a cross-sectional view after the epitaxial layer of Npn AlGaAs / GaAs HBT is grown on the gallium arsenide substrate.
제3도는 Npn AlGaAs/GaAs HBT의 에피층상에 Pnp AlGaAs/GaAs HBT의 에피층을 성장시킨 후의 단면도.3 is a cross-sectional view after the epitaxial layer of Pnp AlGaAs / GaAs HBT is grown on the epitaxial layer of Npn AlGaAs / GaAs HBT.
제4도는 돌출부상의 Npn AlGaAs/GaAs HBT의 에피층위에 형성되어 있는 Pnp AlGaAs/GaAs HBT의 에피층을 식각한 후의 단면도.4 is a cross-sectional view after etching the epi layer of Pnp AlGaAs / GaAs HBT formed on the epi layer of the Npn AlGaAs / GaAs HBT on the protrusion.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반절연성 갈륨비소기판 11 : n+-GaAs 서브 콜렉터층10: semi-insulating gallium arsenide substrate 11: n + -GaAs sub-collector layer
12 : n--GaAs 콜렉터층 13 : p+-GaAs 베이스층12: n - GaAs collector layer 13: p + -GaAs base layer
14 : N-AlGaAs 에미터층 15 : n+-GaAs 에피터 켑층14: N-AlGaAs emitter layer 15: n + -GaAs epitaxial layer
21 : P+-GaAs 서브 콜렉터층 22 : p--GaAs 콜렉터층21: P + -GaAs sub collector layer 22: p -- GaAs collector layer
23 : n+-GaAs 베이스층 24 : p-AlGaAs 에미터층23: n + -GaAs base layer 24: p-AlGaAs emitter layer
25 : p+-GaAs 에미터 캡층 100 : 개별소자영역25: p + -GaAs emitter cap layer 100: individual device region
이하, 첨부된 도면을 참조하여 본 발명의 실시예에 대하여 상세히 설명한다. 제1도부터 제4도는 본 발명에 따른 상보형 HBT의 에피층 형성방법을 나타낸 공정 단면도이다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. 1 to 4 are cross-sectional views showing a method of forming an epitaxial layer of the complementary HBT according to the present invention.
이하, 상기 제1도부터 제4도를 참조하여 본 발명의 실시예를 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 4.
먼저, 제1도에 도시한 바와 같이, (100)의 결정방향을 가지는 반절 연성갈륨비소(GaAs)기판(10)을 사진식각법으로 장방형의 변의 길이가 긴 쪽이 갈륨비소 기판(10)의 주 평탄면에 대하여 45°경사지도록 패터닝하여 후속 형성되는 Pnp AlGaAs/GaAs HBT 개별소자의 영역(돌출부)(100) 및 Pnp AlGaAs/GaAs HBT 개별소자의 영역(오목부)(200)을 정의한다.First, as shown in FIG. 1, the long side of the long side of the gallium arsenide substrate 10 is formed by using a half ductile gallium arsenide (GaAs) substrate 10 having a crystal direction of (100) by photolithography. A region (protrusion) 100 of a Pnp AlGaAs / GaAs HBT individual element, which is subsequently formed by patterning to be inclined at 45 ° with respect to the main flat surface, and a region (concave portion) 200 of the Pnp AlGaAs / GaAs HBT individual element are defined.
상기 식각 공정은 Npn과 AlGaAs/GaAs HBT 개별소자의 크기와 같게 형성되었으며 식각용액으로서는 H2SO4-H2O2-H2O계 용액을 사용하였다. 상기와 같이 개별소자영역을 형성하기 위해 갈륨비소기판(10)상에 복수의 돌출부(100)와 오목부(200)가 기판상에 형성된다.The etching process was formed in the same size as the Npn and AlGaAs / GaAs HBT individual devices, and H 2 SO 4 -H 2 O 2 -H 2 O-based solution was used as an etching solution. A plurality of protrusions 100 and recesses 200 are formed on the gallium arsenide substrate 10 to form individual device regions as described above.
이어서, 제2도에 도시한 바와 같이, (100)결정방향을 가지는 Npn 및 Pnp AlGaAs/GaAs HBT 개별 소자 영역(100)이 정의된 반절연성 갈륨비소기판(10)을 기판을 MBE 챔버에 장착하고 챔버의 진공압력이 10-11Torr가 될 때까지 배기시킨 후, 갈륨비소기판(10)을 600부근까지 가열하여 갈륨비소(10)의 표면이 24구조를 갖는 것을 RHEED 패턴으로 확인한 후 10-7Torr 진공 상태에서 III/V족 원소의 플럭스 비(flux ratio)을 1/15로 유지시키면서 Npn AlGaAs/GaAs HBT의 에피층을 성장시킨다.Subsequently, as shown in FIG. 2, a semi-insulating gallium arsenide substrate 10 having Npn and Pnp AlGaAs / GaAs HBT discrete element regions 100 having a (100) crystal orientation is mounted in an MBE chamber. After evacuating the chamber until the vacuum pressure becomes 10 -11 Torr, the gallium arsenide substrate 10 is 600 Heated to near, so that the surface of gallium arsenide 10 After confirming that the RHEED pattern having a 4 structure, the epitaxial layer of Npn AlGaAs / GaAs HBT is grown while maintaining the flux ratio of group III / V elements at 1/15 in a 10 −7 Torr vacuum state.
이때, 갈륨비소기판(10)상에 형성되는 Npn HBT의 에피층은 불순물 도핑농도가 51018/㎝-3이고 두께가 0.5인 n+-GaAs층(11), 불순물 도핑농도가 21016/㎝-3이고 두께가 0.4인 n--GaAs층(12), 불순물 도핑농도가 31019/㎝-3이고 두께가 0.07인 p+-GaAs층(13), 불순물 도핑농도가 21017/㎝-3이고 두께가 0.2인 N-AlGaAs층(14) 및 불순물 도핑농도가 41018/㎝-3이고 두께가 0.2인 n+-GaAs층(15)을 차례로 적층하여 Npn AlGaAs/GaAs HBT의 에피층(11-15)을 형성한다.At this time, the epitaxial layer of Npn HBT formed on the gallium arsenide substrate 10 has an impurity doping concentration of 5 10 18 / cm -3 and thickness 0.5 Phosphorus n + -GaAs layer 11, impurity doping concentration 2 10 16 / cm -3 and thickness 0.4 Phosphorus n -- GaAs layer 12, impurity doping concentration of 3 10 19 / ㎝ -3 and thickness 0.07 Phosphorus p + -GaAs layer 13, impurity doping concentration 2 10 17 / cm -3 and thickness 0.2 Phosphorus N-AlGaAs layer 14 and impurity doping concentration of 4 10 18 / cm -3 and thickness 0.2 An n + -GaAs layer 15 is sequentially stacked to form an epitaxial layer 11-15 of Npn AlGaAs / GaAs HBT.
상기 n+-GaAs층(11), n--GaAs층(12), p+-GaAs층(13), N-AlGaAs층(14) 및 n+-GaAs층(15)은 각각 Npn AlGaAs/GaAs HBT의 서브 콜렉터 (11), 콜렉터(12), 베이스(13), 에미터(14) 및 에미터 캡층(15)에 해당한다.The n + -GaAs layer 11, n -- GaAs layer 12, p + -GaAs layer 13, N-AlGaAs layer 14 and n + -GaAs layer 15 are each Npn AlGaAs / GaAs Corresponds to the sub-collector 11, collector 12, base 13, emitter 14 and emitter cap layer 15 of the HBT.
이러한, 에피텍시공정에 의해 갈륨비소기판(10)의 오목부(200)내부와 돌출부(100)상에 Npn HBT의 에피층이 서로 분리되어 형성되며, 상기 오목부(200)내에 형성되는 Npn HBT의 에피층의 상표면과 상기 돌출부(100)의 표면이 평탄하게 형성된다.The epitaxial layer of Npn HBT is formed on the inside of the recess 200 and the protrusion 100 of the gallium arsenide substrate 10 by the epitaxial process, and the Npn is formed in the recess 200. The brand surface of the epitaxial layer of the HBT and the surface of the protrusion 100 are formed flat.
이어서, 제3도에 도시한 바와 같이, Pnp AlGaAs/GaAs HBT의 에피층을 성장시킨다.Next, as shown in FIG. 3, an epitaxial layer of Pnp AlGaAs / GaAs HBT is grown.
이때, Npn AlGaAs/GaAs HBT의 에피층상에 형성되는 Pnp HBT의 에피층은 불순물 도핑농도가 51018/㎝-3이고 두께가 0.5인 P+-GaAs층(21), 불순물 도핑농도가 21016/㎝-3이고 두께가 0.4인 p--GaAs층(22), 불순물 도핑농도가 31018/㎝-3이고 두께가 0.07인 n+-GaAs층(23), 불순물 도핑농도가 21017/㎝-3이고, 두께가 0.2인 P-AlGaAs층(24) 및 불순물 도핑농도가 11019/㎝-3이고, 두께가 0.2인 p+-GaAs층(25)을 차례로 적층하여 Ppn AlGaAs/GaAs HBT의 에피층(21-25)을 형성한다.At this time, the epi layer of Pnp HBT formed on the epi layer of Npn AlGaAs / GaAs HBT has an impurity doping concentration of 5 10 18 / cm -3 and thickness 0.5 P + -GaAs layer 21, impurity doping concentration 2 10 16 / cm -3 and thickness 0.4 Phosphorus p -- GaAs layer 22, impurity doping concentration of 3 10 18 / cm -3 and thickness 0.07 Phosphorus n + -GaAs layer 23, impurity doping concentration 2 10 17 / cm -3 , with a thickness of 0.2 P-AlGaAs layer 24 and impurity doping concentration of 1 10 19 / cm -3 , thickness 0.2 The p + -GaAs layer 25 is sequentially stacked to form an epitaxial layer 21-25 of Ppn AlGaAs / GaAs HBT.
상기 p+-GaAs층(21), p--GaAs층(22), n+-GaAs층(23), P-AlGaAs층(24) 및 p+-GaAs층(25)은 각각 Ppn AlGaAs/GaAs HBT의 서브 콜렉터, 콜렉터, 베이스, 에미터 및 에미터 캡층에 해당한다.The p + -GaAs layer 21, the p -- GaAs layer 22, the n + -GaAs layer 23, the P-AlGaAs layer 24 and the p + -GaAs layer 25 are respectively Ppn AlGaAs / GaAs Corresponds to the subcollector, collector, base, emitter and emitter cap layers of the HBT.
이때, Npn AlGaAs/GaAs HBT의 에피층상에 Pnp AlGaAs/GaAs HBT의 에피층을 성장시킬 수 있는 것은 Npn AlGaAs/GaAs HBT 에피층의 n+-GaAs 에피터 캡층(15)과 Pnp AlGaAs/GaAs HBT의 p+-GaAs 서브 콜렉터(21)이 pn 접합을 형성하기 때문에, 전위장벽이 Npn AlGaAs/GaAs HBT의 n+-GaAs 서브 콜렉터층(21)로부터 Npn AlGaAs/GaAs HBT의 n+-GaAs 에미터 캡층(15)으로 정공이 주입되지 않기 때문이다.At this time, Npn of the AlGaAs / GaAs HBT of the epitaxial layer is to grow the epitaxial layer of a Pnp AlGaAs / GaAs HBT Npn AlGaAs / GaAs HBT epitaxial n + -GaAs emitter cap layer 15 and Pnp AlGaAs / GaAs HBT of the epilayer Since the p + -GaAs sub-collector 21 forms a pn junction, the potential barrier is n + -GaAs emitter cap layer of Npn AlGaAs / GaAs HBT from the n + -GaAs sub-collector layer 21 of Npn AlGaAs / GaAs HBT. This is because holes are not injected into (15).
그 다음, 제4도에 도시한 바와 같이, 영역(100)상의 Npn AlGaAs/GaAs HBT의 에피층위에 형성된 Pnp AlGaAs/GaAs HBT의 에피층(21-25)을 사진식각 공정으로 제거한다.Next, as shown in FIG. 4, the epitaxial layer 21-25 of Pnp AlGaAs / GaAs HBT formed on the epitaxial layer of Npn AlGaAs / GaAs HBT on the region 100 is removed by a photolithography process.
이때, 식각용액으로는 H2SO4-H2O2-H2O계 용액을 사용한다.At this time, H 2 SO 4 -H 2 O 2 -H 2 O-based solution is used as an etching solution.
화학 식각이 끝난 후 개별소자영역(100)에 형성된 Npn AlGaAs/GaAs HBT의 에피층(11-15)과 오목부(200)상측에 형성된 Pnp AlGaAs/GaAs HBT의 에피층(21-25)의 표면과 하면이 서로 평탄하게 된다.The surface of the epi layer 11-15 of the Npn AlGaAs / GaAs HBT formed in the individual device region 100 after the chemical etching and the epi layer 21-25 of the Pnp AlGaAs / GaAs HBT formed above the recess 200. The lower surface and the lower surface are flat to each other.
따라서, 갈륨비소기판(10)의 식각된 오목부(200)상측에 형성된 Pnp AlGaAs/GaAs HBT의 에피층(21-25)과 갈륨비소기판(10)의 식각되지 않은 영역인 개별소자영역(100)위에 형성된 Npn AlGaAs/GaAs HBT의 에피층(11-15)은 동일평면상에 형성되고, 상기 오목부(200)내에 형성된 Npn AlGaAs/GaAs HBT의 에피층과 개별소자영역(100)위에 형성된 Npn AlGaAs/GaAs HBT의 에피층은 서로 전기적으로 격리되게 된다.Accordingly, the individual device region 100 which is an epitaxial layer 21-25 of the Pnp AlGaAs / GaAs HBT formed on the etched recess 200 of the gallium arsenide substrate 10 and the unetched region of the gallium arsenide substrate 10. The epitaxial layer 11-15 of Npn AlGaAs / GaAs HBT formed on the same plane is formed on the same plane, and the Npn AlGaAs / GaAs HBT epitaxial layer formed on the recess 200 and the Npn formed on the individual device region 100 The epi layers of the AlGaAs / GaAs HBTs are electrically isolated from each other.
본 발명에서는 갈륨비소기판(10)을 수직으로 화학 식각한 후, MBE 성장방법에 의해 Npn과 Pnp AlGaAs/GaAs HBT의 에피층을 성장시키면, 제2도에 도시한 바와 같이 이상적으로 성장되지 않고 갈륨비소기판의 식각된 측면에도 에피층이 성장된다.In the present invention, when the gallium arsenide substrate 10 is chemically etched vertically, and then epitaxial layers of Npn and Pnp AlGaAs / GaAs HBT are grown by the MBE growth method, gallium arsenide is not ideally grown as shown in FIG. An epitaxial layer also grows on the etched side of the arsenic substrate.
이러한, 측면성장은 갈륨 비소기판(10)의 평면상에 성장되는 두께의 약 1/10 정도가 성장되는데, 이것은 Pnp AlGaAs/GaAs HBT의 에피층을 사진식각 공정에 의해 화학 식각할 때, 갈륨 비소기판(10)의 측면에 성자된 영역을 함께 식각하여 제거시킬 수 있다.This side growth is about 1/10 of the thickness grown on the plane of the gallium arsenide substrate 10, which is a gallium arsenide when chemically etching the epitaxial layer of Pnp AlGaAs / GaAs HBT by a photolithography process The regions formed on the side surfaces of the substrate 10 may be removed by etching together.
본 발명은 에미터-업 구조를 갖는 Npn과 Pnp AlGaAs/GaAs HBT를 동일평면상에 제작할 수 있으므로, Npn AlGaAs/GaAs HBT 만으로 제작이 곤란했던 능동부하(active loads), 전류원(current sources) 및 푸시풀 증폭기(push-pull amplifier)를 제작할 수 있다.According to the present invention, since Npn and Pnp AlGaAs / GaAs HBTs having an emitter-up structure can be manufactured on the same plane, active loads, current sources, and pushes that are difficult to manufacture with only Npn AlGaAs / GaAs HBTs Push-pull amplifiers can be manufactured.
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