WO1998034274A1 - Self-aligned process for fabricating a passivating ledge in a heterojunction bipolar transistor - Google Patents

Self-aligned process for fabricating a passivating ledge in a heterojunction bipolar transistor Download PDF

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Publication number
WO1998034274A1
WO1998034274A1 PCT/US1998/001869 US9801869W WO9834274A1 WO 1998034274 A1 WO1998034274 A1 WO 1998034274A1 US 9801869 W US9801869 W US 9801869W WO 9834274 A1 WO9834274 A1 WO 9834274A1
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WIPO (PCT)
Prior art keywords
ledge
emitter
layer
nitride
base
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Application number
PCT/US1998/001869
Other languages
French (fr)
Inventor
Masatoshi Fukuda
Yong-Hoon Yun
Gregory N. Henderson
Matthew F. O'keefe
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The Whitaker Corporation
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Publication date
Application filed by The Whitaker Corporation filed Critical The Whitaker Corporation
Priority to JP53313698A priority Critical patent/JP2001510636A/en
Priority to AU60522/98A priority patent/AU6052298A/en
Publication of WO1998034274A1 publication Critical patent/WO1998034274A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors

Definitions

  • the present invention relates to a method of fabricating a self-aligned heterojunction bipolar transistor having ledge passivation to reduce surface recombination effects.
  • Heterojunction bipolar transistors are used in a variety of applications requiring active devices having low "one over f" (1/f) noise and a good high frequency performance.
  • the HBT consists of a vertical structure with an emitter layer on top of a base layer on top of a collector layer, with selected portions of each layer removed to expose the different layers and to facilitate electrical connections via metal contacts.
  • One commonly used structure consists of an emitter fabricated of n- AlGaAs, a p- type GaAs base and an n- type GaAs collector.
  • a functioning HBT creates a flow of electrons from the emitter through the base and into the collector.
  • the electron current is modulated by holes injected into the base from the base contacts. Specifically, the extrinsic base region is exposed, and due to high surface recombination velocity, high surface recombination occurs at the extrinsic base surface.
  • Degradation processes within the HBT manifest themselves as a reduction in ⁇ , the DC current gain, the ratio of collector current to base current.
  • a high current density at the emitter/base junction which lies at the corner between the emitter layer and the base layer, results in high recombination current.
  • there is a region of the extrinsic base which is exposed.
  • This exposed extrinsic base is susceptible to degradation due to recombination current described herein.
  • a mesa structure HBT carriers from the emitter reco bine with holes from the base.
  • the extrinsic base being exposed results in recombination at the surface.
  • This surface recombination contributes to device degradation.
  • the lead structure is utilized to reduce this degradation.
  • a ledge structure extends the semiconductor crystal layer of the emitter mesa across the extrinsic base. This ledge is depleted of carriers in operation, thereby reducing the potential for recombination that contributes to the degradation.
  • the result is that the hole/carrier interaction between the base and emitter respectively occurs in the semiconductor base layer and not at an exposed surface as occurs without the ledge. Accordingly, ledges which passivate the extrinsic base layer surface are an attractive alternative to improve device performance.
  • Passivation has been effected by a variety of techniques.
  • One such technique is as disclosed in U.S. Patent 5,298,439 to Liu, et al., the disclosure which is specifically incorporated herein by reference.
  • the emitter layer of the HBT has a ledge fabricated across a substantial portion of the exposed extrinsic base area between the original emitter mesa and the base contacts.
  • the "439 reference discloses a passivation technique that uses a portion of the depleted emitter layer on top of the extrinsic base layer to reduce surface recombination.
  • the method disclosed "439 reference has certain drawbacks.
  • the reference to Liu, et al. is not a self-aligned process. That is, the reference to Liu, et al. results in the finite tolerances in aligned techniques. These tolerances are manifest as different ledge widths, and difference base separations. Additionally, the base contacts are not self aligned.
  • the overall result is a non-symmetrical structure about a plane through the semi-conductor mesa. The result is a reduction in yield due to a reduction in uniformity of device performance across a wafer in large scale wafer fabrication. The final result is an increase in price per unit of acceptable device to an unacceptable level.
  • the present invention relates to a method of fabricating a heterojunction bipolar transistor (HBT) having a passivating ledge structure wherein the emitter mesa, ledge mesa and base contact metallization are self-aligned relative to one another.
  • a photolithographic step defines the separation of the base contact metallization.
  • the geometry of the ledge is defined in a masking material lying beneath the photolithographically defined material. It is a result of process art that the masking material has a slightly smaller geometry than the photolithographically defined material. The difference is referred to an undercut.
  • the dielectric material is silicon nitride.
  • the ledge is formed by a mesa etch.
  • the masking material is reduced in area using standard semiconductor processing techniques and without the need for another photolithographic step, resulting in a further undercut.
  • the emitter mesa is formed preferably using an isotropic etching step.
  • the resulting profile maintains the ledge and provides a sufficient undercut to allow the self-aligned deposition of the base contact metallization.
  • the resulting structure has a base metallization separated from a passivating ledge, of controlled dimensions, by a controlled distance and accordingly an improved manufacturability and higher yield when compared to aligned techniques.
  • Figure 2 shows the emitter layer of the present invention having a layer of dielectric material deposited thereon.
  • Figure 3 shows the patterned photoresist disposed on the dielectric layer.
  • Figure 4 shows the dry etching step used to remove unprotected dielectric with the undercut in the dielectric layer resulting.
  • Figure 5 shows the etching step of the passivating ledge by standard wet etching technique.
  • Figure 6 is the second etching of the dielectric layer again having a slight undercut.
  • Figure 7 is the isotropic wet etch step used to fabricate the emitter mesa.
  • Figure 8 shows the resulting emitter mesa passivating ledge of the present disclosure.
  • Figure 9 shows the emitter mesa and base contacts of the invention of the present disclosure.
  • Figure 10 shows the overall structure of a heterostructure bipolar transistor formed by the present invention . Detailed Description of the Invention
  • Figure 1 shows a table with the preferred materials and doping levels as well as the thicknesses of the materials of the present invention.
  • the preferred structure of the present invention having a gallium arsenide substrate with epitaxial layers grown thereon by standard technique such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) .
  • emitter layer 101 has disposed thereon a dielectric layer 102 which is deposited by standard technique well known to one of ordinary skill in the art on top of the emitter layer 101.
  • the emitter consists of the emitter epitaxial layers and the emitter contact which is deposited previously using standard techniques, with the preferred dielectric material being silicon nitride.
  • a photoresist is shown as in Figure 3 at 203. In the preferred embodiment, this is Shipley Microposit 1813 photoresist. Unprotected dielectric material is thereafter removed using standard techniques.
  • the preferred embodiment of the present step is to use a dry etching technique, preferably SF 5 dry etch chemistry.
  • SF 5 dry etch chemistry preferably SF 5 dry etch chemistry.
  • a direct consequence of the process outlined above is that the masking material has slightly smaller geometry than the photoresist geometry as is shown clearly in Figure 4. The difference known as an undercut 304.
  • This dielectric material geometry defines the passivating ledge of the present invention.
  • the ledge thickness has been experimentally found to be preferably on the order of 200 to 1000 A.
  • the ledge is etched using standard etching techniques with the result as is shown in Figure 5.
  • a wet etch technique is effected at this point in order to fabricate the ledge.
  • this step is preferably an isotropic etch and most preferably H 2 SO 4 -H 2 O2-H 2 O etching step. Again, these techniques are well known to one of ordinary skill in the art.
  • This step is in contrast to the method utilized in the above reference to U.S. Patent 5,298,429. That is, in the present invention the etch step to fabricate the passivating ledge is done in the first etching of the mesa.
  • a small undercut is realized in the present etch step as is shown at 406 in Figure 5 with the resulting ledge as is shown at 405.
  • the width of the ledge 405 is defined by further etching the dielectric material, increasing the level of the undercut as is shown in Figure 6.
  • a wet etch sequence is effected using a buffered HF acid.
  • the emitter mesa etch shown in Figure 7 is an isotropic etch. By etching equally in all directions the ledge profile is retained as the mesa is defined. This is effected in a preferred embodiment using standard wet etching techniques outlined above.
  • the semiconductor emitter is undercut relative to dielectric material, which is undercut relative to the protecting photoresist.
  • the bounds of the ledge also lie inside the bounds of the photoresist, as is shown in Figure 7.
  • the excess dielectric material, the "overhang" shown as 610 is removed in a buffered hydrofluoric acid, with the photoresist hard baked to allow a second photoresist process to define the aligned edges of the base contact metallization.
  • the metallization is effected through standard technique, with metal deposited as shown at 711, but also on the photoresist. This metal layer on the photoresist is removed with the photoresist and a further step.
  • Certain salient features are worthy of specific mention.
  • the distance between the edge of the ledge 712 and the base metallization 711 is identical within tolerance by virtue of the self-aligned technique of the present invention.
  • the ledge width which on the order of 0.50 microns is uniform with intolerance as well.
  • the base contacts as shown in Figures 8, 9 and 10 at 711 are equal distant from line 609 as well as from the edges of the passivating ledge on each respective side of the ledge. This distance is delineated as 808. It is of interest to note that in an alternative embodiment, it is possible to have one base contact for the device. Again, this base contact is self-aligned.
  • the base and collector mesas and collector contacts are effected by standard technique.
  • the final HBT structure including the self aligned emitter mesa, passivating ledge and base contacts is shown in Figure 10. That is, the substrate layer 1001 of gallium arsenide has the n-type gallium arsenide sub-collector layer as shown at 1002 with collector contacts as shown at 1006. The base and collector layers are is shown at 1003 with base contact 711. Emitter mesa is shown at 1004 in Figure 10 with the passivating ledge shown at 712 and emitter contact 1007. The preferred materials and the doping and aluminum content thereof are as disclosed in the Table of Figure 1.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

The present invention relates to a method for fabricating a heterojunction bipolar transistor having a passivating ledge (712) on the emitter layer (101). The passivating ledge (712) is fabricated first through a first etching step and the emitter mesa (1004) thereafter through an isotropic etching step.

Description

SELF-ALIGNED PROCESS FOR FABRICATING A PASSIVATING LEDGE IN A HETEROJUNC ION BIPOLAR TRANSISTOR
Field of the Intervention The present invention relates to a method of fabricating a self-aligned heterojunction bipolar transistor having ledge passivation to reduce surface recombination effects. Background of the Invention Heterojunction bipolar transistors (HBT) are used in a variety of applications requiring active devices having low "one over f" (1/f) noise and a good high frequency performance. The HBT consists of a vertical structure with an emitter layer on top of a base layer on top of a collector layer, with selected portions of each layer removed to expose the different layers and to facilitate electrical connections via metal contacts. One commonly used structure consists of an emitter fabricated of n- AlGaAs, a p- type GaAs base and an n- type GaAs collector. A functioning HBT creates a flow of electrons from the emitter through the base and into the collector. The electron current is modulated by holes injected into the base from the base contacts. Specifically, the extrinsic base region is exposed, and due to high surface recombination velocity, high surface recombination occurs at the extrinsic base surface. Degradation processes within the HBT manifest themselves as a reduction in β, the DC current gain, the ratio of collector current to base current. A high current density at the emitter/base junction, which lies at the corner between the emitter layer and the base layer, results in high recombination current. In a mesa HBT structure, there is a region of the extrinsic base which is exposed. This exposed extrinsic base is susceptible to degradation due to recombination current described herein. In a mesa structure HBT, carriers from the emitter reco bine with holes from the base. The extrinsic base being exposed results in recombination at the surface. This surface recombination contributes to device degradation. The lead structure is utilized to reduce this degradation. A ledge structure extends the semiconductor crystal layer of the emitter mesa across the extrinsic base. This ledge is depleted of carriers in operation, thereby reducing the potential for recombination that contributes to the degradation. The result is that the hole/carrier interaction between the base and emitter respectively occurs in the semiconductor base layer and not at an exposed surface as occurs without the ledge. Accordingly, ledges which passivate the extrinsic base layer surface are an attractive alternative to improve device performance.
Passivation has been effected by a variety of techniques. One such technique is as disclosed in U.S. Patent 5,298,439 to Liu, et al., the disclosure which is specifically incorporated herein by reference. In the reference to Liu, et al., the emitter layer of the HBT has a ledge fabricated across a substantial portion of the exposed extrinsic base area between the original emitter mesa and the base contacts. The "439 reference discloses a passivation technique that uses a portion of the depleted emitter layer on top of the extrinsic base layer to reduce surface recombination. While this reference discloses a technique for fabricating a ledge in the tightly toleranced ledge-to-base region, which results in spacing that enable a lower extrinsic base resistance and base-collector capacitance, the method disclosed "439 reference has certain drawbacks. To this end, the reference to Liu, et al. is not a self-aligned process. That is, the reference to Liu, et al. results in the finite tolerances in aligned techniques. These tolerances are manifest as different ledge widths, and difference base separations. Additionally, the base contacts are not self aligned. The overall result is a non-symmetrical structure about a plane through the semi-conductor mesa. The result is a reduction in yield due to a reduction in uniformity of device performance across a wafer in large scale wafer fabrication. The final result is an increase in price per unit of acceptable device to an unacceptable level.
The prior art requires the mesa to be defined prior to defining the ledge and the thickness of the ledge is less than the thickness of the mesa. Accordingly, what is needed is a technique for fabricating a heterojunction bipolar transistor having a ledge passivation through a self-aligned technique. The resulting structure will allow a greater yield and a uniformity across the wafer with the final result being a reduction in cost per unit of acceptable product. Summary of the Invention
The present invention relates to a method of fabricating a heterojunction bipolar transistor (HBT) having a passivating ledge structure wherein the emitter mesa, ledge mesa and base contact metallization are self-aligned relative to one another. To this end, a photolithographic step defines the separation of the base contact metallization. The geometry of the ledge is defined in a masking material lying beneath the photolithographically defined material. It is a result of process art that the masking material has a slightly smaller geometry than the photolithographically defined material. The difference is referred to an undercut. Preferably the dielectric material is silicon nitride. The ledge is formed by a mesa etch. Thereafter, the masking material is reduced in area using standard semiconductor processing techniques and without the need for another photolithographic step, resulting in a further undercut. The emitter mesa is formed preferably using an isotropic etching step. The resulting profile maintains the ledge and provides a sufficient undercut to allow the self-aligned deposition of the base contact metallization. The resulting structure has a base metallization separated from a passivating ledge, of controlled dimensions, by a controlled distance and accordingly an improved manufacturability and higher yield when compared to aligned techniques.
Objects, Features, and Advantages of the Invention
It is an object of the present invention to have a process for forming a heterojunction bipolar transistor with a passivating ledge on the emitter layer at the emitter/base interface with the resultant device being symmetric about a plane through the emitter mesa.
It is a feature of the present invention to have a process for fabricating a passivating ledge in a first etching step and to etch the emitter mesa thereafter through an isotropic etching step.
It is a further feature of the present invention to have a self-aligned process for fabricating semiconductor ledge structures such that the width of the ledge and the gap between the ledge and base metallization is uniform.
It is a further feature of the present invention to have a self-aligned process such that the gap between the ledge and base metallization is reduced in dimension compared to previous techniques. It is an advantage of the present invention that the resulting device have a uniform structure and accordingly uniform performance characteristics facilitating large scale production. Brief Description of the Drawings Figure 1 shows the preferred materials of the present invention.
Figure 2 shows the emitter layer of the present invention having a layer of dielectric material deposited thereon. Figure 3 shows the patterned photoresist disposed on the dielectric layer. Figure 4 shows the dry etching step used to remove unprotected dielectric with the undercut in the dielectric layer resulting.
Figure 5 shows the etching step of the passivating ledge by standard wet etching technique.
Figure 6 is the second etching of the dielectric layer again having a slight undercut.
Figure 7 is the isotropic wet etch step used to fabricate the emitter mesa. Figure 8 shows the resulting emitter mesa passivating ledge of the present disclosure.
Figure 9 shows the emitter mesa and base contacts of the invention of the present disclosure.
Figure 10 shows the overall structure of a heterostructure bipolar transistor formed by the present invention . Detailed Description of the Invention
Figure 1 shows a table with the preferred materials and doping levels as well as the thicknesses of the materials of the present invention. The preferred structure of the present invention having a gallium arsenide substrate with epitaxial layers grown thereon by standard technique such as molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) . In Figure 2 emitter layer 101 has disposed thereon a dielectric layer 102 which is deposited by standard technique well known to one of ordinary skill in the art on top of the emitter layer 101. In the preferred embodiment the emitter consists of the emitter epitaxial layers and the emitter contact which is deposited previously using standard techniques, with the preferred dielectric material being silicon nitride. The separation of the base contacts, a very important aspect of the present invention, as well as the patterning of the dielectric material, is defined by a photoresist is shown as in Figure 3 at 203. In the preferred embodiment, this is Shipley Microposit 1813 photoresist. Unprotected dielectric material is thereafter removed using standard techniques. The preferred embodiment of the present step is to use a dry etching technique, preferably SF5 dry etch chemistry. A direct consequence of the process outlined above is that the masking material has slightly smaller geometry than the photoresist geometry as is shown clearly in Figure 4. The difference known as an undercut 304. This dielectric material geometry defines the passivating ledge of the present invention. The ledge thickness has been experimentally found to be preferably on the order of 200 to 1000 A. The ledge is etched using standard etching techniques with the result as is shown in Figure 5. In the preferred embodiment of the present process, a wet etch technique is effected at this point in order to fabricate the ledge. Again, as stated above, this step is preferably an isotropic etch and most preferably H2SO4-H2O2-H2O etching step. Again, these techniques are well known to one of ordinary skill in the art. This step is in contrast to the method utilized in the above reference to U.S. Patent 5,298,429. That is, in the present invention the etch step to fabricate the passivating ledge is done in the first etching of the mesa. Again, a small undercut is realized in the present etch step as is shown at 406 in Figure 5 with the resulting ledge as is shown at 405. The width of the ledge 405 is defined by further etching the dielectric material, increasing the level of the undercut as is shown in Figure 6. In the preferred embodiment a wet etch sequence is effected using a buffered HF acid. The emitter mesa etch shown in Figure 7 is an isotropic etch. By etching equally in all directions the ledge profile is retained as the mesa is defined. This is effected in a preferred embodiment using standard wet etching techniques outlined above.
This procedure outlined above differs significantly from the prior art as the ledge is defined prior to the formation of the emitter mesa. The resulting structure has symmetry about an axis lying through the semiconductor emitter mesa. This axis of symmetry is shown at 609 in Figures 7, 8 and 9 within process tolerances, is assured across the wafer.
The above process fabricates the structure shown in Figure 7. Due to the isotropic nature of the emitter mesa etch step, the semiconductor emitter is undercut relative to dielectric material, which is undercut relative to the protecting photoresist. The bounds of the ledge also lie inside the bounds of the photoresist, as is shown in Figure 7. This allows the base contact metallization to be effected through standard deposition techniques and aligned to the whole geometry of the structure. In the preferred embodiment of the present disclosure, the excess dielectric material, the "overhang" shown as 610 is removed in a buffered hydrofluoric acid, with the photoresist hard baked to allow a second photoresist process to define the aligned edges of the base contact metallization. The metallization is effected through standard technique, with metal deposited as shown at 711, but also on the photoresist. This metal layer on the photoresist is removed with the photoresist and a further step. Certain salient features are worthy of specific mention. First of all, the distance between the edge of the ledge 712 and the base metallization 711 is identical within tolerance by virtue of the self-aligned technique of the present invention. Additionally, the ledge width which on the order of 0.50 microns is uniform with intolerance as well. The base contacts as shown in Figures 8, 9 and 10 at 711 are equal distant from line 609 as well as from the edges of the passivating ledge on each respective side of the ledge. This distance is delineated as 808. It is of interest to note that in an alternative embodiment, it is possible to have one base contact for the device. Again, this base contact is self-aligned.
After the base contact metallization has been deposited preferably by electron beam evaporation, or other well known metallization techniques, the excess photoresist is removed with the structure resulting as shown in Figure 9.
After the formation of the emitter mesa including the passivating ledge as well as the deposition of the self-aligned base contacts, the base and collector mesas and collector contacts are effected by standard technique. The final HBT structure including the self aligned emitter mesa, passivating ledge and base contacts is shown in Figure 10. That is, the substrate layer 1001 of gallium arsenide has the n-type gallium arsenide sub-collector layer as shown at 1002 with collector contacts as shown at 1006. The base and collector layers are is shown at 1003 with base contact 711. Emitter mesa is shown at 1004 in Figure 10 with the passivating ledge shown at 712 and emitter contact 1007. The preferred materials and the doping and aluminum content thereof are as disclosed in the Table of Figure 1.
The invention having been described in detail it is clear that other variations and modifications are well within the purview of one of ordinary skill in the art. To the extent that such modifications to the present disclosure allows a self-aligned ledge process which maintains the symmetry of the passivating ledge on the sides of the emitter are within the purview of one of ordinary skill in the art having had the benefit of the present disclosure, such are deemed to be within the scope of the present invention.

Claims

CLAIMS :
1. A process for fabricating a heterojunction bipolar transistor comprising growing a collector layer on a subcollector layer; growing a base layer on said collector layer; growing an emitter layer on said base layer; depositing a layer of silicon nitride on said emitter layer and patterning said nitride with a photoresist; dry etching said nitride in a first nitride etch step to remove unprotected nitride; etching said emitter layer to define a passivating ledge having a defined width; dry etching said nitride in a second nitride etching step forming an undercut in said nitride; isotropically etching said emitter layer to form an emitter mesa characterized in that: said emitter mesa and said ledge being symmetric about an axis through said emitter mesa and said ledge.
2. A process as recited in Claim 1 further characterized in that subcollector, said collector and said base are gallium arsenide selectively doped to form said heterojunction bi-polar transistor.
3. A process as recited in Claim 1 further characterized in that said first nitride etch step defines a length of separation between an edge of said ledge and a base metallization. . A process as recited in Claim 1 further characterized in that said undercut in said nitride formed in said second nitride etch step defines said width of said ledge. 5. A process as recited in Claim 4, further characterized in that said emitter is AlGaAs .
6. A process as recited in claim 1, further characterized in that said at least one contact further comprises two base contacts symmetrically about said semiconductor mesa.
PCT/US1998/001869 1997-02-03 1998-01-30 Self-aligned process for fabricating a passivating ledge in a heterojunction bipolar transistor WO1998034274A1 (en)

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JP53313698A JP2001510636A (en) 1997-02-03 1998-01-30 Self-aligned method for fabricating immobilized shelves in heterojunction bipolar transistors
AU60522/98A AU6052298A (en) 1997-02-03 1998-01-30 Self-aligned process for fabricating a passivating ledge in a heterojunction bipolar transistor

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
US8748943B2 (en) 2010-03-30 2014-06-10 Fairchild Semiconductor Corporation Bipolar junction transistor with stair profile
EP4300590A1 (en) * 2022-06-29 2024-01-03 GlobalFoundries U.S. Inc. Bipolar transistor with stepped emitter

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0478923A2 (en) * 1990-08-31 1992-04-08 Texas Instruments Incorporated Method of fabricating self-aligned heterojunction bipolar transistors
US5298439A (en) * 1992-07-13 1994-03-29 Texas Instruments Incorporated 1/f noise reduction in heterojunction bipolar transistors
EP0752723A1 (en) * 1995-07-07 1997-01-08 Thomson-Csf Bipolar transistor with optimized structure
EP0818810A2 (en) * 1996-07-10 1998-01-14 Trw Inc. Method of fabricating high beta HBT devices

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Publication number Priority date Publication date Assignee Title
EP0478923A2 (en) * 1990-08-31 1992-04-08 Texas Instruments Incorporated Method of fabricating self-aligned heterojunction bipolar transistors
US5298439A (en) * 1992-07-13 1994-03-29 Texas Instruments Incorporated 1/f noise reduction in heterojunction bipolar transistors
EP0752723A1 (en) * 1995-07-07 1997-01-08 Thomson-Csf Bipolar transistor with optimized structure
EP0818810A2 (en) * 1996-07-10 1998-01-14 Trw Inc. Method of fabricating high beta HBT devices

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Title
MA T ET AL: "EFFECT OF BULK RECOMBINATION CURRENT ON THE CURRENT GAIN OF GAAS/ALGAAS HETEROJUNCTION BIPOLAR TRANSISTORS IN GAAS-ON-SI", IEEE ELECTRON DEVICE LETTERS, vol. 10, no. 10, 1 October 1989 (1989-10-01), pages 458 - 460, XP000094578 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8748943B2 (en) 2010-03-30 2014-06-10 Fairchild Semiconductor Corporation Bipolar junction transistor with stair profile
EP4300590A1 (en) * 2022-06-29 2024-01-03 GlobalFoundries U.S. Inc. Bipolar transistor with stepped emitter

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AU6052298A (en) 1998-08-25

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