JPH02243025A - Parallel/serial data converter - Google Patents

Abstract

PURPOSE:To eliminate an undesired data caused at the initial state of data output by providing a parallel data inhibit circuit and an output circuit before and after a multiplexer respectively and excluding an undesired data from the multiplexer in advance. CONSTITUTION:When a new serial data output command is inputted externally, a parallel data inhibit circuit 23 and an output circuit 24 are operated to inhibit the input of a new parallel data to the multiplexer 23 and the signal level of the serial data outputted from the multiplexer 3 is attenuated. That is, an undesired data of a maximum n-digit stored in a register of each digit of the multiplexer 8 is excluded from the multiplexer 3 by n-set of clock signal inputs for a data excluding time. When a prescribed preparation time elapses, the input of the clock signal is started and the inputted parallel data is converted into a correct serial data by the multiplexer 3 and outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel/serial data conversion device that converts parallel data into high-speed serial data, and in particular, the present invention relates to a parallel/serial data conversion device that converts parallel data into high-speed serial data, and in particular, it is a device that reliably eliminates unnecessary data generated at the initial stage of data output. The present invention relates to a parallel/serial data conversion device that can be removed.

[Prior Art] In recent years, in the fields of PCM (pulse code modulation), LAN (corporate information communication), and supercomputers,
The number of data processing devices that process input data at extremely high speeds is increasing. In general, data transmission between data processing devices located at a distance greater than a certain distance involves converting some of the parallel data into serial data using a parallel/serial data converter on the transmitting side. The state is sent to the data transmission path. Then, on the receiving side, the input serial data is converted into parallel data using a serial/parallel data conversion device, and then various data processing is executed.

Therefore, a parallel/serial data conversion device incorporated in a data processing device that executes processing at high speed as described above is also required to have a function of converting parallel data into serial data at high speed.

Normally, the parallel/serial data conversion device that converts parallel data into serial data at high speed as described above employs a so-called incremental type circuit shown in FIG.

In FIG. 5, 1 is a CPU (central processing unit) that constitutes a part of the data processing device on the sending side.
For example, 0-digit parallel data to be transmitted outputted from I is sequentially stored in each address area of the data memory 2. Also, the clock signal a input from the clock terminal
is input to multiplexer 3 and divided into 1 by frequency divider 4.
/ n. The frequency-divided signal output from the frequency divider 4 is input to the multiplexer 3 and also to the address counter 5.

This address counter 5 applies n address values to be read next in the data memory 2 to the data memory 2 every time the frequency division signal is input.

The data memory 2 stores n pieces of data DO and DI stored in the address area designated by the address counter 5.
, D2, -Dn-1 to the multiplexer 3.

The multiplexer 3 converts the input 0-digit (n bits) parallel data into 0-digit serial data C and applies it to the output circuit 6. The output circuit 6 amplifies the signal level of the input serial data C to a specified signal level, such as 2V, and sends it to the output terminal 7.

The multiplexer 3 of such a parallel/serial data conversion device is generally constructed as shown in FIG. In addition,
In order to simplify the explanation, the case of n-w4 will be explained.

That is, this multiplexer 3 includes four registers 8a each composed of p-type flip-flops.

It consists of a shift register in which 3b, 8c, and 8d are connected in cascade, and of the four-digit parallel data output from the data memory 2, data D1, D2, D3, . is connected to each register 8b via each AND gate 9b, 9cr9d and each OR gate 10b, 10c, 10d.
, 8c, and 8d. Further, the data DO of the least significant digit is directly applied to the data terminal of the register 8a via the AND gate 9a. Each register 8a
, 8b, 8c, each output signal of the output terminal Q is connected to each AND gate 11b.

11c, lid and each of the or gates 10b.

Each register 8b in the next stage via lQc and 10d.

It is applied to the data terminals 8c and 8d. Then, the serial data C is output from the output terminal Q of the most significant register 8d.
is output.

Further, the clock signal a is applied to each trigger terminal T of each register 8a to 8d. Further, the frequency-divided signal is input to the load signal generation circuit 12. When the load signal generation circuit 12 receives the frequency-divided signal d, the load signal d at the H level is sent to the other input terminal of each AND gate 9a to 9d.
Apply.

Further, this load signal d is applied to each AND gate 11b.

It is applied to the inverting input terminals of lie and lid.

In such a multiplexer 3, when a divided signal having a cycle four times longer than the clock signal a is applied to the load signal generation circuit 12, an H level load signal d is output during the clock cycle, and each AND gate 9a-9
d is made conductive, and each data D is stored in each register 8a' to 8d.
O to D3 are captured in synchronization with the clock signal. In addition,
At that point, each AND gate 11b-lld is shut off, so the output data of the lower-order registers 8a-8c is not taken into the upper-order registers 8b-8d. When the load signal d returns to the L (low) level after a clock cycle, each AND gate 9a-9d is cut off, and conversely, each AND gate 11b-11d becomes conductive.

Then, each time a clock signal a having a period of 1/4 of the frequency-divided signal is input, each of the data DO to D2 taken into the registers 8a to 8c of the lower digits is transferred to each register of the upper digits.
Shifted from b to 8d. When four clock signals a are input, serial data C consisting of four digits (D3-D2-Dl-DO) is output from the most significant register 8d.

When the 4-digit serial data C is output, the next divided signal is input, and the next 4-digit parallel data DO to D3 are input.
is taken into each register 8a to 8d in synchronization with the clock signal.

Therefore, the parallel/serial data conversion device shown in FIG.
The parallel parallel data stored in the data memory 2 is converted into 0-digit serial data C by the CPU and sent to, for example, a high-speed PCM transmission line.

[Problems to be Solved by the Invention] However, even in the parallel/series boot feeding device configured as shown in FIGS. 5 and 6, the following problems still remain to be solved. That is, as described above, since it is necessary to perform data conversion at high speed, it is necessary to simplify the configuration of the multiplexer 3 to the minimum necessary and make it compact.

Therefore, in order to obtain high frequency characteristics of -window or higher, for example, each register 8a to 8d is not provided with a reset terminal. Incidentally, if a reset terminal is provided, not only will each register 8a to 8d become larger; , wiring to the reset terminal is required, and the wiring generates stray capacitance, which deteriorates frequency characteristics.

However, if each register 8a to 8d is not provided with a reset terminal, the following problem will occur.

First of all, when the device is powered on and the first serial data is transmitted, up to one digit of unnecessary data remaining in each register 88 to 8d of the multiplexer 3 is transferred to the data memory 2.
It is output before outputting the correct serial data C based on the correct data stored in . Therefore, a problem arises in which erroneous unnecessary data is input to the side receiving this serial data.

Next, when the CPU rewrites the storage contents of the data memory 1 and transmits new data, the old data of up to n bits before being rewritten is stored in each register 8a to 8d of the multiplexer 3. Therefore, as described above, there is a problem in that the serial data corresponding to unnecessary old data is output before the new serial data C is output.

The present invention was made in view of these circumstances, and
By providing a parallel data inhibition circuit and an output circuit before and after the multiplexer to eliminate unnecessary data stored in each register of the multiplexer in advance,
Even if each register does not have a reset terminal, it is possible to reliably prevent unnecessary data from being output before correct data is output, greatly improving device reliability without degrading frequency characteristics. The purpose is to provide parallel/serial data conversion measures that can be used.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a frequency divider that divides the frequency of a clock signal output from a clock signal generation source to 1/n, and a shifter having an n-stage configuration. Consisting of registers, in response to the frequency division signal input output from the frequency divider, each digit of n (n≧2) digit parallel data input from the outside is taken into each 0-digit register, In response to a clock signal input, the data of each digit taken into the register of each digit is sequentially digitally multiplexed starting from the register of the most significant digit and is output as one serial data. In a data converter, there is a clock inhibit circuit that inhibits input of a clock signal to a frequency divider in response to a clock inhibit command input, and a parallel circuit that inhibits input of parallel data to a multiplexer in response to a data input inhibit command. A data inhibit circuit, an output circuit that adjusts the signal level of serial data output from the multiplexer, and a data input inhibit command that responds to the serial data output command input to the parallel data inhibit circuit and output level to the output circuit. A data input/output prohibition control means that sends an attenuation command, and a clock that sends a clock prohibition command to a clock prohibition circuit after an unnecessary data discharge time that is longer than the time required for inputting n pulses of a clock signal from the data input prohibition command sending time has elapsed. a prohibition control means, a data input/output prohibition release control means for canceling the data input prohibition command and the output level reduction command after the unnecessary data discharge time has elapsed; and clock inhibition release control means for canceling the inhibition command.

[Function] According to the parallel/serial data converter configured in this way, when a new serial data output command is input from the outside, for example, the parallel data prohibition circuit and the output circuit are activated, and the new serial data output command is input to the multiplexer. The input of parallel data is prohibited, and the signal level of serial data output from the multiplexer is attenuated. Therefore, during the operation period, that is, during the data discharge time, the maximum 0-digit unnecessary data stored in the register of each digit of the multiplexer is discharged from the multiplexer by inputting n clock signals. Thereafter, the clock signal input is stopped by the clock prohibition circuit, and at the same time, the above operations of the parallel data prohibition circuit and the output circuit are canceled.

Then, when a predetermined preparation time has elapsed, input of a clock signal is started, and the input parallel data is converted into correct serial data by a multiplexer and output.

That is, serial data caused by unnecessary data is not output before correct serial data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a data processing device incorporating a parallel/serial data conversion device according to an embodiment. The same parts as in FIG. 5 are given the same reference numerals.

In other words, C forming part of the data processing device on the sending side
For example, 0-digit parallel data to be transmitted outputted from the PU 21 is sequentially stored in each address area of the data memory 2 via an address bus and a data bus. Further, a clock signal a inputted from a clock terminal of a clock signal generation source (not shown) is inputted to the multiplexer 3 via the clock inhibiting circuit 22 and also inputted to the frequency divider 4. The clock signal a input to the frequency divider 4 is frequency-divided by 1/n, and is input to the multiplexer 3 as a frequency-divided signal, and is also input to the address counter 5.

The address counter 5 is designated by the CPU 21 with the address area length in the data memory 2 corresponding to the number (-n) of parallel data to be read at one time. Then, each time one frequency-divided signal is input, n address values to be read next in the data memory 2 are applied to the data memory 2. The data memory 2 has n pieces of data D stored in the address area designated by the address counter 5.
o, DI, D2, .Dn-1 are output to the multiplexer 3 via the parallel data inhibition circuit 23.

This multiplexer 3 has the same configuration as that shown in FIG. Apply. The output circuit 6 changes the signal level of the input serial data C to the control terminal G when the L level output level attenuation command e outputted from the sequence control circuit 25 is applied. Attenuate to almost 0 level. Output level reduction i
If the im command e is not input, the input serial data C is amplified to a prescribed signal level, such as 2V, and sent to the output terminal 7.

The sequence control circuit 25 is composed of a type of microcomputer, and sends an output level attenuation command e to the output circuit 24 as necessary, and also sends a clock signal to each control terminal G of the clock prohibition circuit 22 and the parallel data prohibition circuit 23. Prohibition command f and data input prohibition command g
Send out.

Clock prohibition circuit 22 to which clock prohibition command f is input
blocks the clock signal a, and the parallel data prohibition circuit 23 to which the input data prohibition command g is input blocks the parallel data DO to Dn-1.

Further, the sequence control circuit 25 sends a reset signal to the reset terminal R of the frequency divider 4 and the address register 5. Further, a timer circuit 26 is connected to the sequence control circuit 25, which measures an unnecessary data discharge time Tl and a preparation time T2 ('l'2>"I',) which is slightly longer than n times the cycle of the clock signal a. There is.

Further, the CPU 21 outputs an output start command 1 to the sequence control circuit 25, and also sends a strobe signal to a receiving side data processing device (not shown).

The CPU 21 is programmed to execute the main routine shown in FIG.

That is, when a data output request command for serial data is input from the outside via, for example, an interface in S (step) 1, parallel data to be transmitted to the data memory 2 is sent to each address area in the data memory 2. Store in. Next, the data length DL indicated by the number of data included in each serial data C output from the output terminal 7 to the address counter 5 is determined as the length of the address area in the data memory 2 in which each data to be read at a time is stored. Set as . Then, an output start command i is sent to the sequence control circuit 25.

Note that if other processing requests occur in S2, the corresponding processing is executed.

Further, the sequence control circuit 25 executes the flowchart shown in FIG. 3 when the power is turned on or when a serial data output request occurs.

That is, in S3, a clock opening command f is sent to the clock inhibiting circuit 22 to inhibit input of the clock signal a to the frequency divider 4. Next, when an output start command i is input from the CPU 21 in S4, a reset signal is sent to the frequency divider 4 and address counter 5 in S5, and the frequency is divided by "a".
4 and address counter 5 are reset. Next, at 86, a data input prohibition command g is sent to the parallel data prohibition circuit 23.
, and prohibits parallel data from being input to multiplexer 3. Furthermore, in S7, an output level attenuation command e is sent to the output circuit 24 to control the signal level of the serial data C output from the output circuit 24 to approximately zero.

When the above processing is completed, the timer circuit 26 is activated in S8. Then, in S9, the clock prohibition command f applied to the clock prohibition circuit 22 is released, and the clock signal a is guided to the frequency divider 4. That is, since the clock signal a and the frequency-divided signal S are input to the multiplexer 3, the multiplexer 3 operates normally and each register 8a to
The unnecessary data remaining in 8d is sent to the output circuit 24 as serial data C. Also, during this time, logic 0 data is taken into each register 88-8d. However, since the output level attenuation command e is applied to the output circuit 24, the serial data C including unnecessary data is not output to the output terminal 7.

When the timer circuit 26 in the SIO measures the unnecessary data discharge time T1 from the startup time, the S11 outputs a clock prohibition command f to the clock prohibition circuit 22 to interrupt the clock signal a again. Next, in S12, the data input prohibition command g applied to the parallel data prohibition circuit 23 is canceled, and in S13, the data input prohibition command g applied to the frequency divider 4. Reset address count 5 again. Further, in S14, the output level attenuation command e applied to the output circuit 24 is canceled.

When the timer circuit 26 measures the preparation time T2 from the timer activation time 88 in S15, the clock prohibition command f applied to the clock prohibition circuit 22 is canceled and a strobe pulse is sent out in S16.

Thus, correct parallel data of 0 digits (n bits) is read out from the data memory 2 at the same time, and the multiplexer 3
The data is input to the multiplexer 3, converted into serial data C, and amplified to a prescribed signal level, such as 5V, by the output circuit 24, and then sent from the output terminal 7 to a data transmission path (not shown).

Next, the operation of the parallel/serial data converter configured as above will be explained with reference to the time chart shown in FIG.

That is, when a data output command is input from the outside at time to, each parallel data to be transmitted from the CPU 21 is stored in the data memory 2, and when the storage process is finished at time t1, an output start command i is input. The signal is applied to the sequence control circuit 25. Thus, clock signal a and parallel data are cut off, and frequency divider 4 and address counter 5 are reset. Furthermore, the output signal level of the output circuit 24 is attenuated.

When the above processing is completed at time t2, the timer circuit 26
is activated, and the cutoff of clock signal a is released. Therefore, each register 8a to 8 of the multiplexer 3 is
The unnecessary data stored in 8d is serial data C.
It is discharged as. Note that no new parallel data is input to multiplexer 3 during this period, and
The serial data C including unnecessary data is attenuated by the output circuit 24 and is not output from the output terminal 7.

When the unnecessary data discharge period T has elapsed at time t3, the clock signal a is cut off again, parallel data can be input, and the output level of the output circuit 24 returns to its original normal value. Then, at time t4, preparation time T2
When the period elapses, the cutoff of the clock signal a is released and the strobe signal is sent out. From then on, serial data C consisting of 0 digits (n bits) is sequentially output from the output terminal 7 every time the frequency-divided signal is input.

According to the parallel/serial data converter configured in this way, when newly outputting serial data,
The input of correct parallel data to the multiplexer 3 is stopped for a certain period of time T1 (unnecessary data discharge time), and each register 8a to 8 of the multiplexer 3 is
The unnecessary data remaining in d is discharged and attenuated by the output circuit 24. Therefore, unnecessary data is reliably prevented from being output before correct data is output.

Therefore, it is possible to prevent data processing errors caused by unnecessary data from occurring in the data processing device on the receiving side that receives this serial data.

Therefore, each register 8a to 8d of multiplexer 3
Since there is no need to provide a reset terminal in the parallel/serial data converter, the high frequency characteristics of the parallel/serial data converter do not deteriorate.

Note that the present invention is not limited to the embodiments described above. In the embodiment, a four-digit shift register is used as the multiplexer 3 to simplify the explanation, but in an actual device, a multi-stage shift register such as eight stages or 16 stages is used.

In addition, in the embodiment, the circuit example shown in FIG. 6 is shown as a multiplexer circuit, and in this circuit, a clock signal and a 1/4 clock signal are input from the outside, but only a clock is input, and the load signal generation circuit Alternatively, the load pulse may be generated by dividing the frequency by 1/4.

[Effects of the Invention] As explained above, according to the parallel/serial data conversion device of the present invention, a parallel data inhibition circuit and an output circuit are provided before and after multiplexing, and the multiplexer is disabled while parallel data is not input to the multiplexer. Eliminates unnecessary data stored in each register. Therefore, even if each register of the multiplexer is not provided with a reset terminal, it is possible to reliably prevent unnecessary data from being output before correct data is output. As a result, the reliability of the entire data conversion device can be significantly improved without degrading the frequency characteristics of the data conversion device.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing the entire data processing device incorporating the parallel/serial data conversion device of the embodiment, and FIGS. 2 and 3 are flow charts showing the operation of the embodiment. Fig. 4 is a time chart showing the operation of the same embodiment, and Fig. 5 is a conventional parallel/
FIG. 6 is a block diagram showing the entire data processing device incorporating the serial data converter, and FIG. 6 is a block diagram showing the multiplexer in the same device. 2...Data memory, 3...Multiplexer, 4...
...Frequency divider, 5...Address Kampf, 21...CP
U, 22... Clock prohibition circuit, 23... Parallel data prohibition circuit, 24... Output circuit, 25... Sequence control circuit,

Claims (1)

[Claims] Consisting of a frequency divider (4) that divides the frequency of the clock signal output from the clock signal generation source by 1/n, and a shift register with n stages, the output from the frequency divider is n (n≧2) input from the outside in response to the frequency division signal input
The data of each digit in the parallel data of digits is taken into each of the n-digit registers (8a to 8d), and in response to the input of the clock signal, the data of each digit taken into the register of each digit is transferred to the topmost register. In a parallel/serial data conversion device comprising a multiplexer (3) that sequentially performs digital multiplexing from a digit register and outputs it as a single serial data, the frequency divider of the clock signal responds to a clock prohibition command input. Clock prohibition circuit (22
), a parallel data prohibition circuit (23) that prohibits input of the parallel data to the multiplexer in response to a data input prohibition command, and an output circuit (24) that adjusts the signal level of the serial data output from the multiplexer. ), and in response to the serial data output command input,
data input/output prohibition control means (S6, S7) that sends a data input prohibition command to the parallel data prohibition circuit and an output level attenuation command to the output circuit; a clock prohibition control means (S11) that sends a clock prohibition command to the clock prohibition circuit after an unnecessary data discharge time longer than the time required to input the pulses has elapsed; data input/output prohibition release control means (S12, S14) for canceling the level reduction command; and clock prohibition release control for canceling the clock prohibition command after a preparation time longer than the unnecessary data discharge time has elapsed from the data input prohibition command sending time. A parallel/serial data conversion device comprising means (S16).