JPH02239656A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent impurities of both electrodes from diffusing in mixture by a method wherein an N<+> type polysilicon electrode an a P<+> type polysilicon electrode are connected through a metal film layer and covered with silicide while the metal layer is kept from becoming silicided on an oxide layer. CONSTITUTION:An electrode 1 made of N<+> type polysilicon and an electrode 2 made of P<+> type polysilicon are connected through a metal layer 9 which has been converted to silicide except its portion between the two electrodes, thereby electrically connecting both the electrodes without diffusion of impurities. That is, since the metal has properties in which impurities are scarcely diffused, a region which is not silicified is interposed between both the electrodes of the metal silicide for connecting the electrode 1 to the electrode 2. Thus, it can prevent impurities from diffusing in mixture.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention provides an electrode of N-PolySl and a P+-Pol
The present invention relates to a semiconductor device in which ySi electrodes can be connected without mutual diffusion and mixing of impurities.

(Prior art) N-Po1 is used as the gate electrode material of conventional NMOSPET.
NMOSFET. P
When forming a CMOS circuit in which both the MOSPET and the MOSPET are surface channel type, as shown in FIG. 2, regions 1.2 are formed by separately implanting N-type impurities and P-type impurities into one continuous polycrystalline silicon. The regions 1, 2 are connected to the source and drain 3, 4, respectively.

However, in the conventional method, both impurities diffuse and mix, which changes the work function of the gate electrode and causes the threshold voltage to fluctuate. Also, the third
As shown in the figure, region 1 of N-PolySi and P-P
If the distance d between the olySi regions 2 and 5 is increased, it is possible to prevent impurities from mixing, but LS
This impedes the high density of the I circuit, and also has problems such as high resistance since no impurities are contained between the two electrodes.

(Problems to be Solved by the Invention) As described above, in the conventional technology, N-type impurities and PW impurities diffuse and mix with each other, and in order to prevent this, it is necessary to There was a problem in that the distance d had to be increased.

The present invention provides an electrode made of N-PolySi and a P
- It is an object of the present invention to provide a semiconductor device that can electrically connect electrodes made of PolySi and prevent both impurities from diffusing and mixing with each other.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, an electrode made of N''-Po 1 yS i and an electrode made of P-PolySi are made of metal silicide on both electrodes. By connecting with a non-silicided metal film layer, both electrodes can be electrically connected without interdiffusion of impurities.

(Function) Since unsilicided metal has the property that impurities are difficult to diffuse, an unsilicided region is placed between the metal silicide electrodes connecting the electrode made of %N''-PolySt and the electrode made of P-PolySi. By sandwiching them, it is possible to prevent impurities from diffusing and mixing.

(Example) Hereinafter, an example of the present invention will be described using the drawings. FIG. 1(a) to FIG. 1(e) are cross-sectional views in the manufacturing process of an embodiment of the present invention. First, as shown in FIG. 1(a), after forming a P-well 7 for forming an NMOSFET and an N-well 8 for forming a PMOSFET on a semiconductor substrate 6, , an element region 4 and an element isolation region 3 are formed. Here, NMOSPE
As long as the region forming the T is of P type and the PMOSPET region is of N type, there is no problem even if it is configured with only one well (veil). Next, polycrystalline silicon is deposited on the entire surface, and boron is selectively implanted at a high dose into a predetermined region including at least the boundary between the adjacent and boron ion-implanted regions, as shown in Fig. 1 (b). ) The openings 12 are formed by photolithography and reactive ion etching. Next, a CVD film 9 is deposited over the entire main surface of the semiconductor including the opening (FIG. 1(C)). Next, the CVDM 13 is etched by reactive ion etching, and the process is completed when the polycrystalline silicon films 1 and 2 shown in FIG. 1 are exposed. Through this step, the filling step is completed such that the CVD film 9 remains in the opening (FIG. 1(d)). After this, at the gate electrode of NMOSPET: 6N-Poly
The Si layer 1' and the P-Polysi layer 2', which is the gate electrode of the PMOSFET (7), are selectively etched and patterned so that they are adjacent to each other through the insulator buried portion 9 of the opening.

Through this process, the N''-PolyS L layer 1' and P
-PolySi layer 2' becomes electrically insulated.

Next, the sources and drains of the NMOS-FET and PMOSFET are formed using the usual ion implantation method, and titanium. A metal such as molybdenum or tungsten is deposited on the entire surface by sputtering, and patterned so that at least the N+-PolySi layer 1' and the P-Poly-SL layer 2' are electrically connected. Next, heat treatment is performed at about 600°C to separate the metal N''-PolySi layer 1' and P''
- The metal film above the PolySt layer 2' is silicided to lower the resistance at the contact portion. At this time, N”-P
CV embedded between o1ysi and P+-PolySi
Since the metal film 10 on the D film is not silicided, the N''-P
By diffusing impurities of olySi and P''-PolySi,
It is possible to prevent them from being mixed in each other's areas. Next, normal wiring processes and passivation processes are performed to complete the semiconductor device.

[Effect of the invention] As described above, according to the present invention, N+Po 1
In the metal M layer connecting the yS i electrode and the P-PolySi electrode, the tops of both electrodes are silicided,
Since the top of the oxide film between both electrodes is not silicided,
Impurities in both electrodes can be prevented from diffusing and mixing with each other. Further, according to the present invention, in a CMOS circuit, PM
Since the P-PolySi layer 2 can be used for the gate electrode of the OSFET, a surface channel type can be realized, and leakage current near the surface, which has been a problem with conventional buried channel types, can be reduced.

[Brief explanation of drawings]

Figure 1 is a diagram showing the manufacturing process of the example, Figures 2 and 3.
The figure shows a conventional example. 1-N"-Po 1 yS i electrodes 1, 2 of NMOSPET... P"-PolySi electrodes 2, 3 of PMOSFET... source and drain of Nl40SFET,
4... Source and drain of PMOSPET, 5...
・PolysL region between N''-PolySL and P''-PolyS i, 6... semiconductor substrate, 7...
P well, 8... N well, 9... CVD film, 10
Metal, 11...Silicide, 12...Poly-S
i Membrane opening.

Claims (2)

[Claims] (1) An element region of a first conductivity type, an element region of a second conductivity type, and an element isolation region are formed on a semiconductor substrate, and an element region of the first conductivity type and an element region of a second conductivity type are formed on the main surface of the semiconductor. to MOS
a step of forming a gate oxide film for forming a MOS type transistor, a step of depositing a polycrystalline silicon film as a gate electrode of a MOS type transistor, and a step of depositing a polycrystalline silicon film at a predetermined position of the polysilicon film on the element region of the first conductivity type. a step of introducing an impurity of a first conductivity type; a step of introducing an impurity of a second conductivity type into a predetermined position of a polycrystalline silicon film on an element region of a second conductivity type; a step of providing an opening in a region including at least the boundary, a step of burying an insulator in the opening, and a step of forming the polysilicon of the first and second conductivity types including the opening into a gate electrode wiring pattern. 1. A method of manufacturing a semiconductor device, comprising: processing the gate electrode of the first conductivity type and the gate electrode of the second conductivity type with a metal film layer. (2) The first conductivity type gate electrode and the second conductivity type gate electrode made of polycrystalline silicon are electrically separated by a buried layer made of an insulator placed at the boundary, and the first conductivity type gate electrode made of polycrystalline silicon is electrically separated. Claim 1, further comprising a step of electrically connecting the gate electrode and the second conductivity type gate electrode with a metal film.
A method of manufacturing the semiconductor device described above.