JPH02239613A - Forming method of fine pattern - Google Patents

Forming method of fine pattern

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Publication number
JPH02239613A
JPH02239613A JP6167589A JP6167589A JPH02239613A JP H02239613 A JPH02239613 A JP H02239613A JP 6167589 A JP6167589 A JP 6167589A JP 6167589 A JP6167589 A JP 6167589A JP H02239613 A JPH02239613 A JP H02239613A
Authority
JP
Japan
Prior art keywords
film
approximately
regions
resist film
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6167589A
Other languages
Japanese (ja)
Inventor
Shunichi Kobayashi
俊一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP6167589A priority Critical patent/JPH02239613A/en
Publication of JPH02239613A publication Critical patent/JPH02239613A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form an overhang-shaped opening advantageous for a lift-off by using a resist film as a foundation pattern, selectively exposing the film, giving temperature difference in the thickness direction of the film and developing the film. CONSTITUTION:A resist film 11 is applied onto a substrate 10, and regions (b), (e) are exposed selectively. The width (w) of the exposed regions is brought to approximately the thickness of the film 11 at that time. Temperature difference is given to the film 11 in the thickness direction after pre-baking, and the thickness of the lower half of the film 11 is held at 20 deg.C and the thickness section 11b of an upper half at 40 deg.C. When the film 11 is exposed to a developer at approximately 40 deg.C under the state, the region (b) is melted and removed for approximately sixty sec, and the region (e) is melted and removed for approximately thirty-four sec. When developing is continued, regions (a), (c), (d), (f) are exposed to the developer, but the rates of dissolution in the regions (d), (f) are made larger than those of the regions (a), (c) by approximately threefold, thus increasing the opening radius r1 of the upper section 11b by approximately 294nm though the opening radius r2 of the lower section 11a is increased by approximately 840nm through developing for approximately seven min. Accordingly, the whole opening shape is formed in an overhang shape.

Description

【発明の詳細な説明】 本発明は微細パターンの形成方法に関し、例えば、半導
体装置における微細な電極パターンの形成にとって有用
である. (口》 従来の技術 半導体装置のための微細な電極パターンを形成する一手
法として、リフト才フ法が知られている.リフト才フ法
は、第6図に示す如く、基板(1)上にリフトオフ用下
地パターン(2》を形成する工程(同図A)、基板上か
ら1極材料を蒸着あるいはスパッタすることにより基板
(1》の露出表面及び下地パターン(2)の上に夫々寛
極膜(3a)(3b)を被着する工程(同図B)、そし
て、下地パターン(2》と共にその上に電極膜(3b)
を除去し、所望パターンの電極膜(3a)のみを残す工
程《同図C)を経るものである. Jフト才フ法において重要なことは、下地パターン(2
).}:の電極膜(3b)がシャープに完全にリフト才
フ除去できることであり、このためには、第6図の工程
において、両電極膜(3a)( 3b)が互いに橋絡す
るのを随止けねばならない。第6図Aに示す如く、下地
パターン(2)における開口を、小さい1部径d1と大
きい下部径d,とを有する形状、即ちオーバーハング形
状としているのは、前記橘絡防止のためである. 斯る才一バーハング形状の形成方法は、例えばJ.M.
Frary and P.Seese, ”’Lift
−off Techiniquasfor Fine 
Line Metal  Patterning,” 
 Semiconductar Internatio
nal,Vol.4,No.12,P.72 〜88(
198l)に見られる. 《ハ)発明が解決しようとする課題 本発明は、リフト才フ法における下地パターンの才一バ
ーハング形状を、より簡単に形成し得る、新規な方法を
提供するものである.〈二》 課題を解決するための手
段 本発明による微細パターンの形成あ法は、第3図に示す
如く、基板(10〉上にレジスト膜(11)を被着する
工程(同図A)、レジスト膜(1l)を所望パターンに
て選択露光(l2)する工程(同図B)、レジスト膜(
11)を、その厚み方向に温度差を付与した状態で現像
する工程(同図C)、斯る現像工程により露出した基板
表面(10a)及び残留するレジスト膜(1l》上に電
極材料等からなる所望膜(13a)(13b)を被着す
る工程(同図D》、残留レジスト膜(l1》と共に、そ
の上に被着された所望膜(13b)を除去する工程(第
3図E)、を順次経ることを特徴とする.(ホ》 作用 レジスト膜の溶解速度は現像液温度に大きく依存するこ
とが知られている.第2図はこの様子を示す。同図は、
ボジレジストであるOFPR−800(東京応化製)に
対し、85℃〜90゜C130分の条件でプノベークを
行ない、次いでCanon PLA−300Fで露光を
施した後、現像液としてNMD−3(東京応化製)を用
いて、各種の現像液温度で1分間現像を行なった場合の
残膜率を調べたものである.尚、ボストベークは120
℃、30分の条件で行なわれた.同図から明らかな如く
、現像液温度が低いほど、残膜率が小さく、即ち溶解速
度が犬さくなる.従来は、レジスト膜の溶解速度の差が
ほとんど生しないように、現像液温度を精密に制御して
いるが、本発明は、現像液温度の差に基づくレジスト膜
の溶解速度の差を積極的に利用したものである. 以下、本発明の原理を第1図にて説明するに、第1図A
は第3図Bに示す露光工程終了時の状態を示し、第1図
B乃至Dは第3図Cに示す現像工程における現像経過を
示している. 第1図Aにおいて、基板(10)上に被着されたレジス
トIll(11)は約1.74饅厚さのOFPR−80
0から構成きれ、図中点々で示す領域(b)(e)が露
光量50m)/cm”(露光波長436nm)で選択露
光されたものとする.このとき、露光領域幅Wは例えば
レジスト膜(l1)の厚み程度である。そして、ブリベ
ーク後、レジスト膜(11)の膜厚方向に温度差が付与
されるが、説明を簡単にするために、レジスト膜(1l
〉の下半分の厚み(lla)が20℃に、又上半分の厚
み部分(llb)が40℃に夫々保持されるものとする
. このとき、OFPR−800の特性として、図中点線で
区画された各領域(a)〜(f’)4こおけるレジスト
膜の溶解速度は下表の通りとなる. 断る状態でレジスト膜(1l)を、ほイ40℃の現像液
に曝らすと、約60秒で領域(b)が溶解除去され(第
1図B》、その後約34秒で領域(e)が溶解除去され
る(第1図C). 更に現像を続けると、領域(a)(c)及び(d)(f
’)が現像液に曝されるが、領域(d)(f’)におけ
る溶解速度は領域(a)(C)におけるそれよりも約3
倍大きく、従って約7分間の現像により、下部分(ll
a;の開口半径r,は約840am増加するのに対し、
上部分(llb>の開口半径r,は約294nm増加す
るだけであり、全体の開口形状は才−バーハング状とな
る《第1図D》. 実際には,レジスト膜《1l》中の温度は膜の厚み方向
において、階段的でなく、連続的に変化するので、得ら
れる開口も階段的でなく、基板《10》に向って徐々拡
開する才−バーハング状となる.(へ》 実施例 本発明における第1の実施例の現像工程を第4図にて説
明する.第1図における基板(1G)となるシリコンウ
エハ(10b)が真空チャック(l4)上に保持される
.ウエハ(10b)の表面には第1図と同様のレジスト
膜(1l)が被着され、この膜には所望パターンにて選
択露光が施されている.チャック(14)は回転可能で
あり、かつ温度調節機能を有する. そこで、チャック(14》の温度を20℃に紅持すると
共に、40℃の現像液ク15)をレジスト膜(11)上
にスズレーする。スプレーは間欠的に行い、その間隔は
、古い現像液が除かれるに充分な最短時間とする.スプ
レー中、チャック(14)は回転される.列ヤ・7・ク
(14〉温度と現像液(15)温度との間の温度差によ
りレシス1膜(11)の厚み方向に温度差が付与きれる
。シリコンウエハ(10b)の熱伝導度は4 X 10
−’cal/Cm−Sec * ’C程度であるのに対
し、レジスト膜(l1)のそれは7 X 10”’ca
l/cm ・see ・℃程度であり、後者の方が約3
桁小さく、従って、チャックと現像液の温度差はほとん
どレジスト膜《11)に集中し、レジスト膜(11》に
才−バーハング状の開口が能率良く形成される. 木発明における第2の実施例の現像工程を第5図にて説
明する。この実施例では、攪拌及び温度m整機能付きの
槽(16》に現像液(l5)が収容され、シリコンウエ
ハ(10b)に被着されたレジスト膜(11)が現像液
(15)の液面に接触すべく配置される.ウエハ(10
b)がチャック(14》に保持されることは第4図の場
合と同様である. よって、この場合も、レジスト膜(1l》に、その厚み
方向に温度差が付与され、オーバーハング状の開口が形
成される. 上記各実施例において、温度差の値は適宜変更し得.る
ことはもちろんである. (ト》  発明の効果 本発明によれば、リフト才7法における下地パターンと
してレジスト膜を用い、選択露光後、この膜にその厚み
方向に温度差を付与して現像するだけで、リフト才フに
有利な才−バーハング状の開口を形成することができる
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming fine patterns, and is useful for forming fine electrode patterns in semiconductor devices, for example. (Explanation) Conventional technology The lift-off method is known as a method for forming fine electrode patterns for semiconductor devices.The lift-off method, as shown in FIG. In the step of forming a base pattern (2) for lift-off on the substrate (A in the same figure), a monopolar material is vapor-deposited or sputtered from the substrate to form a soft polarized material on the exposed surface of the substrate (1) and on the base pattern (2), respectively. The step of depositing the films (3a) and (3b) (FIG. B), and the electrode film (3b) on top of the base pattern (2)
The process involves removing the electrode film (3a) of the desired pattern and leaving only the electrode film (3a) in the desired pattern (C in the same figure). The important thing in the J-Futosaifu method is the base pattern (2
). }: The electrode film (3b) can be sharply and completely removed by lifting, and for this purpose, in the process shown in FIG. It has to stop. As shown in FIG. 6A, the reason why the opening in the base pattern (2) is formed into a shape having a small diameter d1 at one part and a diameter d at a large lower part, that is, an overhang shape, is to prevent the above-mentioned tangling. .. A method of forming such a bar hang shape is described, for example, in J. M.
Frary and P. Seese, ”'Lift
-off Techiniquas for Fine
Line Metal Patterning,”
Semiconductor International
nal, Vol. 4, No. 12, P. 72 ~ 88 (
198l). <<C) Problems to be Solved by the Invention The present invention provides a novel method that can more easily form the vertical bar hang shape of the base pattern in the lift process. <2> Means for Solving the Problems The method for forming a fine pattern according to the present invention, as shown in FIG. 3, includes the steps of depositing a resist film (11) on a substrate (10) (A in the same figure); Step (B) of selectively exposing the resist film (1l) in a desired pattern (l2);
11) in a state where a temperature difference is applied in the thickness direction (C in the same figure); A step of depositing the desired films (13a) and (13b) (FIG. 3D) and a step of removing the desired film (13b) deposited thereon together with the residual resist film (11) (FIG. 3E) (e) It is known that the dissolution rate of the working resist film is largely dependent on the developer temperature. Figure 2 shows this situation.
OFPR-800 (manufactured by Tokyo Ohka), which is a body resist, was subjected to a punobake at 85°C to 90°C for 130 minutes, and then exposed with Canon PLA-300F, and then NMD-3 (manufactured by Tokyo Ohka) was used as a developer. ) was used to investigate the remaining film rate when development was performed for 1 minute at various developer temperatures. In addition, Bost Bake is 120
The experiment was carried out at ℃ for 30 minutes. As is clear from the figure, the lower the developer temperature, the lower the residual film ratio, that is, the slower the dissolution rate. Conventionally, the developer temperature is precisely controlled so that there is almost no difference in the dissolution rate of the resist film, but the present invention actively reduces the difference in the dissolution rate of the resist film due to the difference in developer temperature. It was used for Hereinafter, the principle of the present invention will be explained with reference to FIG. 1.
3B shows the state at the end of the exposure step, and FIGS. 1B to 1D show the progress of development in the development step shown in FIG. 3C. In FIG. 1A, the resist Ill (11) deposited on the substrate (10) is OFPR-80 with a thickness of about 1.74 cm.
Assume that the regions (b) and (e) indicated by dots in the figure are selectively exposed at an exposure dose of 50 m)/cm" (exposure wavelength 436 nm). At this time, the exposed region width W is, for example, a resist film. After the pre-baking, a temperature difference is applied in the thickness direction of the resist film (11).
> The thickness of the lower half (lla) is maintained at 20°C, and the thickness of the upper half (llb) is maintained at 40°C. At this time, as a characteristic of OFPR-800, the dissolution rate of the resist film in each region (a) to (f') 4 divided by dotted lines in the figure is as shown in the table below. When the resist film (1 liter) is exposed to a developer at 40°C, the area (b) is dissolved and removed in about 60 seconds (Fig. 1B), and then the area (e) is removed in about 34 seconds. ) are dissolved and removed (Fig. 1C). When development is continued further, areas (a), (c) and (d) (f
') is exposed to the developer, but the dissolution rate in regions (d) (f') is about 3% lower than that in regions (a) (C).
The lower part (ll
The aperture radius r of a; increases by about 840 am, whereas
The opening radius r of the upper part (llb>) increases by only about 294 nm, and the overall opening shape becomes a bar hang shape (Fig. 1D).In reality, the temperature in the resist film <1l> is In the thickness direction of the film, it changes continuously, not in a stepwise manner, so the resulting opening is not stepwise, but in the shape of a bar hang that gradually expands toward the substrate <<10>>. The developing process of the first embodiment of the present invention will be explained with reference to Fig. 4.A silicon wafer (10b) serving as a substrate (1G) in Fig. 1 is held on a vacuum chuck (l4). ) is coated with a resist film (1l) similar to that shown in Fig. 1, and this film is selectively exposed in a desired pattern.The chuck (14) is rotatable and has a temperature control mechanism. Therefore, the temperature of the chuck (14) is maintained at 20°C, and a developer solution (15) at 40°C is sprayed onto the resist film (11).The spraying is performed intermittently, and the intervals are set as follows. , the minimum time sufficient to remove the old developer. During spraying, the chuck (14) is rotated. By this, a temperature difference can be applied in the thickness direction of the Resis 1 film (11).The thermal conductivity of the silicon wafer (10b) is 4 x 10
-'cal/Cm-Sec *'C, whereas that of the resist film (l1) is 7 x 10"'ca
l/cm ・see ・℃, and the latter is about 3
Therefore, most of the temperature difference between the chuck and the developer is concentrated in the resist film (11), and a bar hang-shaped opening is efficiently formed in the resist film (11).Second Embodiment of the Wooden Invention The developing process will be explained with reference to FIG. 5. In this example, a developing solution (15) is contained in a tank (16) equipped with stirring and temperature control functions, and the resist deposited on the silicon wafer (10b) is A membrane (11) is placed in contact with the surface of the developer (15).
b) is held by the chuck (14) as in the case of Fig. 4. Therefore, in this case as well, a temperature difference is imparted to the resist film (1l) in its thickness direction, resulting in an overhang-shaped resist film (1l). An opening is formed.In each of the above embodiments, it goes without saying that the value of the temperature difference can be changed as appropriate. By using a film, after selective exposure, and developing the film by applying a temperature difference in its thickness direction, it is possible to form an opening in the form of a bar hang, which is advantageous for lift reduction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A乃至Dは本発明の現像原理を説明するための工
程別断面図、第2図は現像特性を示す曲線図、第3図A
乃至6Eは本発明を説明するための工程別断面図、第4
図及び第5図は、夫々本発明実施例の現像方法を説明す
゛るための模式図、第6区A乃至Cは従来方法お説明゛
4るための工程別断面図である. 第1図
Figures 1A to D are cross-sectional views for each step to explain the development principle of the present invention, Figure 2 is a curve diagram showing development characteristics, and Figure 3A.
6E to 6E are cross-sectional views according to steps for explaining the present invention;
5 and 5 are schematic diagrams for explaining the developing method according to the embodiment of the present invention, and sections A to C are sectional views for explaining the conventional method. Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)基板上にレジスト膜を被着する工程、前記レジス
ト膜を所望パターンにて選択露光する工程、前記レジス
ト膜を、その厚み方向に温度差を付与した状態で現像す
る工程、前記現像工程により露出した基板表面及び残留
するレジスト膜上に所膜膜を被着する工程、前記残留レ
ジスト膜と共に、その上に被着された前記所望膜を除去
する工程、を順次経ることを特徴とする微細パターンの
形成方法。
(1) A step of depositing a resist film on a substrate, a step of selectively exposing the resist film in a desired pattern, a step of developing the resist film while applying a temperature difference in the thickness direction, and the developing step The step of depositing a desired film on the exposed substrate surface and the remaining resist film, and the step of removing the desired film deposited thereon along with the residual resist film are sequentially performed. How to form fine patterns.
JP6167589A 1989-03-13 1989-03-13 Forming method of fine pattern Pending JPH02239613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6167589A JPH02239613A (en) 1989-03-13 1989-03-13 Forming method of fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6167589A JPH02239613A (en) 1989-03-13 1989-03-13 Forming method of fine pattern

Publications (1)

Publication Number Publication Date
JPH02239613A true JPH02239613A (en) 1990-09-21

Family

ID=13178063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6167589A Pending JPH02239613A (en) 1989-03-13 1989-03-13 Forming method of fine pattern

Country Status (1)

Country Link
JP (1) JPH02239613A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498769A (en) * 1992-12-21 1996-03-12 Nec Corporation Method for thermally treating resist film and forming undercut pattern
JP2003086531A (en) * 2001-09-07 2003-03-20 Seiko Instruments Inc Method for manufacturing pattern electrode, and pattern electrode manufactured by the method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498769A (en) * 1992-12-21 1996-03-12 Nec Corporation Method for thermally treating resist film and forming undercut pattern
JP2003086531A (en) * 2001-09-07 2003-03-20 Seiko Instruments Inc Method for manufacturing pattern electrode, and pattern electrode manufactured by the method

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