JPH02235142A - Control system for data speed conversion circuit - Google Patents

Abstract

PURPOSE:To convert the speed of data with a minimum delay value by preparing plural detecting circuits, detecting a reading or writing address together with a clock and recognizing the execution of respective operation. CONSTITUTION:A writing address detecting circuit 14 simultaneously detects a writing address generated from a writing address generating circuit 10 and a clock. A reading address detecting circuit 15 simultaneously detects a reading address generated from a reading address generating circuit 12 and a clock. The writing and reading addresses outputted from the circuits 14, 15 are detected by an overflow/underflow detecting circuit 13 and a memory 11 is initialized. Since the clock is simultaneously detected, the writing and reading of data in the detected address area can be recognized and the data speed is converted with the minimum delay value.

Description

[Detailed Description of the Invention] Overview This relates to a control method for a data speed conversion circuit that temporarily stores data in a memory whose write clock and read clock frequencies are different, and converts the data speed with a minimum amount of delay. The purpose of this is to write data into the memory according to the timing of the write clock and the address by the write address generation circuit, read the data in the memory according to the timing of the read clock and the address by the read address generation circuit, In a data speed conversion circuit control method that uses an overflow/underflow detection circuit to detect data writing or reading twice, a write address detection circuit that simultaneously detects a write address and a write clock by a write address generation circuit, and a read A read address detection circuit that simultaneously detects the read address and read clock by the address generation circuit is provided, and the overflow/underflow detection circuit detects the write address output from the write address detection circuit and the read address output from the read address detection circuit. Configure it to be detected by.

INDUSTRIAL APPLICATION FIELD The present invention relates to a control method for a data rate conversion circuit that temporarily stores data in a memory whose write clock and read clock have different frequencies and converts the data rate.

Today, with the diversification of communication services, there is an increasing demand for communication equipment that can efficiently process signals such as audio, images, and data. In order to meet such demands, distributed switching systems that can efficiently process multiple signals are beginning to attract attention in place of conventional centralized switching systems. This distributed switch system uses a data rate conversion circuit that converts the rate of data sent from various data terminals.

Under these circumstances, there is a demand for efficient data rate conversion using a data rate conversion circuit.

BACKGROUND OF THE INVENTION FIG. 4 shows a block diagram of a control method for a conventional data rate conversion circuit.

The frequencies of the write clock and read clock used in the memory 39 are different from each other.

Data is written in the data area of the memory 39 at the address specified by the write address in synchronization with the timing of the write clock. Further, in synchronization with the timing of the read clock, data stored in the data area of the address of the memory 39 specified by the read address is read out.

If the write clock frequency and read clock frequency are different from each other, data in the memory 39 will be written twice (overflow) or read twice (underflow). Alternatively, the memory 39 is initialized by detecting that an underflow state is approaching. Therefore, when the write address and read address get close to each other, this overflow/underflow detection circuit 4
0 initializes the memory 39. For example, when data is being written to the area at address n of the memory 39, if the read address approaches this address n, the overflow/underflow detection circuit 40 changes the write address from address n to address 0. The memory 39 is controlled to change.

Problems to be Solved by the Invention However, in the conventional control method of the data rate conversion circuit as described above, overflow/underflow is detected by comparing only the write address and read address, and the actual data I don't know about writing and reading. stomach. Therefore, when the write address and read address get close to some extent, this is detected (proximity alarm) and the memory is initialized, so the written data is not read out immediately and the data transmission delay tends to increase. there were.

The present invention has been made in view of these points, and an object thereof is to provide a control system for a data rate conversion circuit that can perform data rate conversion with a minimum amount of delay.

Means to solve problems FIG. 1 is a block diagram showing the principle of the present invention.

The data is transferred to the memory 11 according to the timing of the write clock and the address generated by the write address generation circuit 10.
Data speed conversion that reads the data in the memory 11 according to the timing of the read clock and the address by the read address generation circuit 12, and detects whether the data is written twice or read twice by the overflow/underflow detection circuit 13. In the circuit control system, a write address detection circuit 14 that simultaneously detects the write address and write clock generated by the write address generation circuit 10 and a read address detection circuit 15 that simultaneously detects the read address and read clock generated by the read address generation circuit 12 are provided. .

Then, the overflow/underflow detection circuit 13 detects the write address output from the write address detection circuit 14 and the read address output from the read address detection circuit 15.

4, the write address and the write clock are detected simultaneously, and the read address detection circuit 15 detects the read address and the read clock simultaneously. Therefore, it can be recognized that data is actually being written or read in the area of the detected address, so even if the write address and read address are close to each other, if there is an overflow or underflow state, Unless otherwise specified, data writing and reading operations can be continued, and data speed conversion can be performed with the least amount of delay.

When the write address and read address match and write/read is performed and an overflow or underflow occurs, the overflow/underflow detection circuit 1 is activated.
3, this overflow/underflow state is detected and the memory 11 is initialized.

Function According to the present invention, write address detection circuit 1 Embodiment Hereinafter, the present invention will be explained in detail based on an embodiment shown in the drawings.

FIG. 2 shows a circuit diagram of an embodiment of a control method for a data rate conversion circuit according to the present invention.

The memory 20 is composed of storage circuits 21-1 to 21-N each including a flip-7 flop circuit or the like. The write address counter 22 is composed of an n-bit counter 23 and an n-bit decoder 24, and the read address counter 26 is composed of an n-bit counter 27 and an n-bit decoder 28. AND circuits 25-1 to 25
-N takes the AND logic of the write address and the write clock, and sends the result to each of the storage circuits 2l-1 to 21-N. The AND circuits 29-1 to 29-N perform an AND logic of the read address and the read clock, and send the result to each of the storage circuits 21-1 to 21-N. The detection circuit at address 0 on the right side of the overflow/underflow detection circuit 30 is a flip-flop circuit (F/F
) 3 1 to 34 and differentiating circuits 41 and 42.

The detection circuits at addresses other than address O have the same configuration as the detection circuit at address 0, and are not shown. The OR circuit 35 sends pulses output from the flip-flops 32 and 34 corresponding to address 0 and the flip-flops (not shown) corresponding to addresses other than address 0 to the differentiating circuit 36.

The operation of such a configuration will be explained using the time chart of FIG.

First, the operation when writing data into the memory 20 will be explained.

The write clock via the NOT circuit 37 is input to the clock terminal of the counter 23 as a write address clock, and the counter 2 is input in synchronization with this write address clock.
3 is counted up (point a in FIG. 3), and this counted up value is decoded by the decoder 24 and outputted to the AND circuit 25 corresponding to the counted up value.
-1 to 25-N. At the same time, the write clock is also input to the AND circuits 25-1 to 25-N.

For example, when the write address output from the counter 23 is address 0, the decoder 24 outputs an AND circuit 25
-1, and a pulse is sent from this AND circuit 25-1 to the write terminal (W) of the memory circuit 21-1, so that data A is transmitted to this memory circuit 2'l-1 (
《Point b in Figure 3》 is stored at write address 0). still,
In this embodiment, after data is latched (point C in FIG. 3) in a latch circuit (not shown) provided in the preceding stage of the memory circuit 21-1, the data is transferred to the memory circuit 21-1 at the rising edge of the write clock. It is latched at -1.

Next, the operation when reading data in the memory 20 will be explained.

The read clock via the NOT circuit 38 is input to the clock terminal of the counter 27 as a read address clock, and the counter 2 is input in synchronization with this read address clock.
7 is counted up (point d in FIG. 3), and this counted up value is decoded by the decoder 28 and outputted to the AND circuit 29 corresponding to the counted up value.
-1 to 29-N are manually operated. At the same time, the read clock is also input manually to the AND circuits 29-1 to 29-N.

For example, when the read address output from the counter 27 is address 0, the AND circuit 29
-1, and this AND circuit 29-1 sends a pulse to the read terminal (R) of the memory circuit 21-1, thereby causing the memory circuit 21-1 (write address 0
) is read out. (Point e in Figure 3).

Further, a high level signal is always input to the input terminals (D terminals) of the flip-flops 31 and 33 in the overflow/underflow detection circuit 30, and the initial state of the output terminal is the same as that of the flip-flop 31. is low level,
Flip-flop 33 is at a high level.

When writing data to address 0 of the memory 20, the output of the AND circuit 25-1 is input to the clock terminal of the F/F 31, and the output signal of the F/F 31 is inverted to a high level. Then, when reading the data at address 0, the output of the AND circuit 29-1 is
The output signal of this F/F 33 is inverted to high level, and at the same time, this high level signal is input to the reset terminal (R) of F/F 31,
The output of F31 is inverted to low level.

In this way, if the operation after writing data at address 0 is a read operation, F/F 3 2
The output of the AND circuit 25 remains at a low level, but if the operation after writing the data is a write operation again (for example, writing twice), the AND circuit 25 -1 output signal is input to the clock terminal of F/F 32, and a high level signal is output from this F/F 32.

This high level signal is sent to the differentiating circuit 36 via the OR circuit 35 and becomes an instantaneous pulse, which is sent to the write address counter 22, read address counter 26 and memory 2.
0. Reset (initialize). The behavior of this initialization is
Since it is necessary to complete the process before the next write clock or read clock is generated, the pulse signal generated when overflow or underflow is detected is differentiated by the differentiating circuit 36 to create an instantaneous pulse. As a result, the operation of the reset pulse (instantaneous pulse) for initialization becomes faster than the operation of the write clock and read clock.

On the other hand, if the operation after reading data at address 0 is a write operation, the output signal (high level) of F/F 31 is input to the reset terminal of F/F 33, so no reset pulse is sent out. However, if the operation after reading the data is a read operation again, the high level output signal of F/F 33 will be transferred directly to the F/F 33.
Since it is latched by F 3 4 and output to the ○R circuit 35 side, the write address counter 22, read address counter 26, and memory 20 are reset.

For example, if you try to read data at address 2 to which nothing has been written after reading data B at address 1, as in the case of the read mark at point f in Figure 3 (2 For the overflow/underflow detection circuit 30, a high level signal is output from the F/F (not shown) corresponding to address 2 of the overflow/underflow detection circuit 30. This high-level signal is sent to the differentiating circuit 36 via the ○R circuit 35 and becomes a reset pulse (instantaneous pulse) (point g in Figure 3), which resets the write address counter 22, read address counter 26, and memory 20. .

As a result, both the write address and read address are set to address 0.

Effects of the Invention Since the control method of the data rate conversion circuit of the present invention is configured as detailed above, data rate conversion is performed with the minimum amount of data delay, and the buffer memory can be optimized. This has the effect of greatly contributing to improving the efficiency of data transmission.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram of an embodiment of the control method of the data rate conversion circuit according to the present invention, Fig. 3 is a time chart according to the embodiment of Fig. 2, and Fig. 4 is a conventional one. 2 shows a block diagram of a control method of the data rate conversion circuit of FIG. DESCRIPTION OF SYMBOLS 10... Write address generation circuit, 11... Memory, 12... Read address generation circuit, 13... Overflow/underflow detection circuit, 14... Write address detection circuit, 15... Read address detection circuit, 21-1 to 21-N...Storage circuit, 22...Write address counter, 25-1 to 25-N, 29-1 to 29-N...AND
Circuit, 26... Read address counter, 31-34... Flip-flop circuit.

Claims (1)

[Claims] Data is written into the memory (11) according to the timing of the write clock and the address generated by the write address generation circuit (10), and data is written into the memory (11) according to the timing of the read clock and the address generated by the read address generation circuit (12). 11), and an overflow/underflow detection circuit (13) detects whether the data is written twice or read twice.
A write address detection circuit (14) that simultaneously detects the write address and write clock by the read address generation circuit (12) and a read address detection circuit (15) that simultaneously detects the read address and read clock by the read address generation circuit (12) are provided. A control method for a data rate conversion circuit characterized in that an overflow/underflow detection circuit (13) detects a write address output from (14) and a read address output from a read address detection circuit (15). .