JPH02232635A - Camera with trimming photographing function - Google Patents

Abstract

PURPOSE:To prevent a poor photograph due to high magnification trimming by outputting an alarm signal, etc., to a photographer when factors other than film sensitivity exceed trimming magnification limits. CONSTITUTION:The camera is provided with a trimming magnification setting means setting plural different trimming ranges with respect to the same picture a storage part storing trimming magnification limits except film sensitivity, a means discriminating whether a set trimming magnification exceeds the limits, and a means outputting a signal indicating that the set magnification exceeds the limit if so. Factors determining the trimming magnification limits except film sensitivity include monochrome or color, negative or position, makers, etc. When factors other than film sensitivity exceed the trimming limits, the effect is informed. Consequently, a particle size of film is prevented from affecting film finishing. The adverse affect may be produced by raising the trimming magnification over a prescribed value.

Description

Detailed Description of the Invention [Field of Industrial Application 1] The present invention relates to a camera capable of switching between a normal shooting mode for shooting a normal shooting range and a trimming mode for setting a narrower trimming range. [Prior Art] Conventionally, in this type of camera, film sensitivity (
rso) to limit the trimming magnification, and when this limit is reached, the trimming magnification is set below a predetermined value (for example, Japanese Patent Laid-Open No. 62-50745).
(Refer to the publication). This is because the graininess of the film becomes a problem as the trimming magnification increases, and in particular, the higher the sensitivity of the film, the worse the graininess tends to be. However, even if the film sensitivity is the same, each film has different cropping limits, and even if the cropping magnification exceeds the limit, it is not possible to continue setting the magnification if the photographer wishes. Requested. [Issues to be Solved by the Invention] The present invention is in response to the above-mentioned requirements, and an object of the present invention is to provide a camera that notifies when the limit of the trimming magnification determined by factors other than film sensitivity is exceeded. , [Means for Solving the Problems] The present invention has a trimming shooting function that allows switching between a normal shooting mode for shooting a normal shooting range and a trimming mode for setting a narrower trimming range. In the camera, a trimming magnification setting means for setting a plurality of different cropping ranges for the same screen, a storage section for storing limits of trimming magnification other than film sensitivity, and determining whether or not the set trimming magnification exceeds the limit. Discrimination means and when it is determined that the limit has been exceeded,
It is also possible to arbitrarily set the magnification even if it exceeds the trimming magnification. Factors that determine the limits of cropping magnification other than film sensitivity include black and white and color, type of negative and positive, and differences between manufacturers. [Function] According to this configuration, when the trimming limit other than the film sensitivity exceeds the limit, that fact is notified. [Effects of the Invention] As described above, according to the present invention, it is possible to output a signal such as a warning to the photographer when the limit is exceeded due to a trimming limit other than film sensitivity, and it is possible to avoid unsightly photographs due to high-magnification cropping. This can prevent the formation of Furthermore, according to the embodiment, if the photographer desires, even if the limit is exceeded, the setting of the cropping magnification can be further varied. (Hereinafter, blank spaces) [Embodiment] Figure 1 shows the block configuration of the entire system consisting of a camera body and a film section according to an embodiment of the present invention. The control microcomputer (hereinafter referred to as CPU) 1 controls the entire camera.The color embellishing unit 2 that measures the light source color of the subject and the photometry unit 3 that measures the brightness of the subject measure the light and color data, respectively. is output to the CPUI as a digital signal.The display section 4 is composed of a liquid crystal display (LCD), etc., and displays various shooting information on the liquid crystal display board on the camera body and in the viewfinder.The lens section 5 is used for shooting and autofocus. The accessory 6 consists of an electronic flash device, a data imprint device, a comment input section to be described later, and others.
The distance measuring section 7 measures the distance to the subject using COD or the like. The driver unit 8 controls the aperture and shutter speed, controls the winding and rewinding of the film, and controls the charging of each a-ellipse such as the shutter and mirror based on the TV value and AV value calculated on the CPUI. , and performs lens autofocus control, etc. A power supply 9 is provided inside the camera body and supplies power to each block of the CPU. The film section 10 includes a film cartridge (hereinafter referred to as a cartridge) and a film.
The details will be explained later. Next, I will explain the switches. Switch S1 is for starting colorimetry, distance measurement, and photometry, and switch S2 is a release switch for starting exposure control. The switches S3 and S4 are used to set the trimming range, which will be described later. Each time the switch S3 is turned on, the trimming range is decreased by one step (that is, the trimming magnification is increased), and then the switch S4 is turned on. Each time you do this, increase the trimming range by one step (i.e., decrease the trimming magnification).
I can go there. Switch s5 is a switch for imprinting, and is turned on when inputting a comment.
Switch S6 is a mercury switch, etc., and is used to adjust the camera vertically and
It detects the horizontal, vertical, and downward postures, and the detection information from this posture detection switch S6 is also detected by the E2PII inside the cartridge.
ON (described later). Incidentally, specific examples of the detection switch are described in, for example, Japanese Patent Laid-Open No. 59-17543 and Japanese Patent Laid-Open No. 63-255611. Switch SPAI is a detection switch that turns ON when a cartridge is loaded. The resistor R1 and the capacitor C1, and the resistor R2 and the capacitor C2 are connected to the CPUI and the reset terminal RES of the film section 10, respectively, and perform a power-on reset. The oscillator 11 supplies the system clock φ to the CPU 1 and the cartridge internal circuit of the film unit 10. In addition,
The above CPUUI and each section 2, 3.4, 5.6.10 are serial input line SIN, serial output line SOUT
, are connected by a serial data bus consisting of a serial clock line SCK, and the CPU performs serial communication with each part. FIG. 2 shows a block configuration of the accessory 6 shown in FIG. 1. Comment data input from the input section 12, which is a switch matrix or the like, is temporarily stored in the register 13. The recognition unit 14 recognizes input characters based on data from the dictionary unit 15. The storage unit 16 stores data regarding characters recognized by the recognition R unit 14. During comment writing, the display control unit 17 displays data (characters, etc.) from the register 13 on the LCD 18, and also displays character data stored in the storage unit 16. Further, a font is set in the font section 19, and the output section 20 is set in the storage section 1.
Output the characters stored in 6 to the CPUI as comment data in the set font. Note that this output is output only when the imprinting switch S5 is turned on.

Figure 3 is a schematic flowchart showing the operation of the CPU within the camera body. When power is supplied from the power supply 89, the CPU starts operating and waits for the film cartridge to be loaded (
#1). "Film cartridge is loaded and switch"
When the FAT is turned ON, a read signal is output to the film unit 10, and the ID (index) code ICP Fl1H is input from the cartridge side (#2).This input ICP FUN is compared with the ID code on the camera side. As a result, if the film cartridge is compatible (NCP FILM OK), the camera-specific code ICP CAMERA is output to the film unit 10 (#4).This code ICP CAMERA is verified on the cartridge side. If it is determined that the camera is compatible with the cartridge (ICP CAHER＾0κ)
, FILM such as film characteristic data or shooting information
Since DATA is output (details will be explained later), CP
Enter it in the UI (#5). Here, #2 ICP FILH and #4 ICP CA
l4ERA will be explained using Figure 5. 1lI
Each cartridge has a different ICP than other cartridges.
FIIN and unique ICP CAMERA Ref
I have this code in memory. Suppose now that a cartridge is loaded and an ICP FILM code of "A" is sent to the camera body (same for lab equipment). The camera body has all compatible ICP FILH and corresponding ICP CAMERA code combinations, including the ICP CAMERA code "a" that corresponds to the "A" code from the cartridge.
” to the cartridge. If the code “A” is not present on the camera body, or if film that does not have a memory IC (i.e. regular film) is loaded, the camera will issue a warning and stop the film loading process. The cartridge has the code "a" from the camera body and the ICP CAMERA Ref stored in the memory on the cartridge side.
(In this case, "aH" is compared, and if they match, memory access is enabled and data communication (described later) is performed; however, if they do not match, communication of shooting information is prohibited as in the case of the camera body side described above. . Return to the flowchart in Figure 3 and continue the explanation. In #6, do not input FIL14 Whether or not DATA is OK (
For example, whether the film is within its expiration date, etc.), and then OK.
Then 7 Raku 208F = 1 (#10) #1
Proceed to 1. On the other hand, cartridge compatible 1 loaded in #3
, Naka7':') (ICP FILHfj'OK is not OK), FIIH DATA is not OK in #6 (for P4, the film expiration date has expired), or the cartridge side determines that the camera is not aligned. If the FIIH D^TA is not sent from the cartridge because of the error, the flag ZOκF is set to O (#7>, a warning indicating that data communication is not possible is issued (#8), and the film data is set to a certain value. (For example, set fs010(1) <#9) and move on to #11. Note that the shooting operation itself may be prohibited as explained earlier. Also, in #6, the shooting operation from the film cartridge is completed. Input the frame number data (contents of the film counter (see Figure 16)) and the specified shooting frame number data, and if the two match, this will be notified to the photographer through a pictorial display or sound display.
You can prohibit future shooting, depending on whether the switch SP^■ has changed from OFF to ON.
In other words, it is determined whether or not the cartridge is newly loaded. If the cartridge is newly loaded, initial loading is performed (#12>, and then the film counter is displayed (#13>. If the cartridge is newly loaded, If so, skip #12 and proceed to #13 to display the film counter.Next, proceed to #14 in Fig. 4, and determine whether switch S1 is ON.Switch S1 is ON. If,
Colorimetry is performed by sending a start signal to the colorimeter 2 (#1.5). Next, set the trimming (#16
, the setting method will be explained in Fig. 6), distance measuring section 7
, sends a start signal to the photometer 3, and performs distance measurement and photometry (#17, #18). Next, perform exposure calculations based on the information obtained (or set) in #15 to #18 to calculate data necessary for exposure control, such as TV values and AV values (#19), and use the calculated values. Display on the display unit 4 (#20). Next, the camera's vertical/horizontal information, accessory information, etc. are set (#21), and it is determined whether the release switch/y switch S2 is ON or not (#22).
If not N, determine whether switch S1 is ON or not (#
23), if switch S1 remains ON, CPU1
are #15 to #21. Release switch S2 is turned on or switch S1 is turned off for a series of sequences at t.
Execute repeatedly until If the switch Sl is OFF in #14 or #23, the process moves to #24. Here, trimming settings are performed, and then, similar to #21, camera information is set (#25). Next, determine whether ZOKF=1 or not (#2 6), and if ZQKF≠1, select #14
Move to . If 10κF=1, the presence or absence of a comment input is checked as explained in FIG. ).Then, proceed to #14 and repeat the above operation.Here, the reason why the comment is written to the address of the previous frame is that it is common to actually write the comment after the shooting is completed. Note that you may enter a comment before shooting, or you may be able to enter a comment on any frame.If no comment is entered, or even if a comment is entered, If switch S5 is OFF, proceed directly to #14. On the other hand, if switch S2 is ON in #22, exposure control is performed based on the data obtained in #19 (#30).
．． Next, it is determined whether ZOκF=4 (#31
If 1, 20κF = 1, that is, if data communication is possible, each piece of information is written to the internal memory of the cartridge (
#32), wind the film one frame (#33). #31
If 70KF≠1 is found, wind the film without writing any information (#33). In addition, in #32, data is output that increments the contents of the film counter (see FIG. 6) in the cartridge internal memory by 1. #3
The details of how to write the information in step 2 will be described later. #3
After 3, advance the film counter one frame and display #
34, #35》, move on to #14 and repeat the sequence described above. Next, the above (#1 6. #24)
The trimming settings will be explained using the flowchart in Figure 6. First, determine whether 20KF=1 is exposed or not (#401
, 10KF≠1, it is determined whether the trimming setting switch S3 or S4 is ON (#4
6'). If ZOKF≠1, information cannot be written, so either switch 33 or 34 is turned on.
If so, issue a warning and return (#47); if neither switch S3 or S4 is turned on, return without issuing a warning. If ZOKF=1 in #40, F1114 input in #5 above 1) Determine whether or not trimming is prohibited based on cartridge-specific trimming information of ATA (#4 1). For example, if the film is a slide film, trimming is prohibited. If trimming is not prohibited, determine whether the trimming magnification has reached the limit value (#423. If trimming is prohibited and the trimming magnification has reached the limit value,
Move to #46 and press switch S3 or S as before.
4 and if it is ON, issue a warning and return. The above cropping prohibition and cropping magnification limit values are as follows:
When the film cartridge is loaded, FJLH DA
Entered as TA. The limitation of trimming magnification arises because, for example, the higher the ISO sensitivity of the film, the more the cropping magnification is increased beyond a predetermined value.
This is because the graininess of the film does not affect the quality of the photograph. Furthermore, since black and white film generally has better graininess than color film, the image quality of the photograph does not deteriorate even if the cropping magnification of black and white film is greater than that of color film. Therefore, the limit value of the cropping magnification can be set higher for black and white film than for color film. Furthermore, even with the same sensitivity and the same type of film, the graininess differs between manufacturers, and the limit value of the trimming magnification also differs. If the trimming magnification has not yet reached the limit value in #42, it is determined whether the switch S3 or s4 is ON (#43). Both switches S3 and S4 are O.
If it is FF, the trimming magnification is not changed or the trimming setting is completed and the process returns. If either is ON, the contents of the trimming register are set to 1.
Change the stage (#44), and switch 33 and S4 are set to O.
The trimming magnification may be changed only when changing from FF to ON, so that even if the switches S3 and S4 are kept ON by mistake, the contents of the trimming register only change by one step. This trimming register is a register that stores the current trimming magnification, and when the contents of the register are changed by one step, the print range is displayed on the finder screen as shown in Figure 7.
#45), return to #42. In addition, in the above embodiment, trimming is prohibited or limited,
Furthermore, if switch S3 or S4 is pressed,
Although a warning is given to prevent the photographer from changing the cropping settings, if the photographer so desires, it may be possible to continue to make further cropping settings while giving the warning.
As a result, the trimming setting range can be freely expanded. Fig. 7 shows the display mode within the viewfinder field of view (inside the screen) by a liquid crystal display (LCD). The example shown here allows you to set up to three levels of trimming. The liquid crystal display device has four types of 71z-me FO and P according to the trimming range.
i, F2, and F3 are provided, and any one of them is configured to be selectively displayed depending on the contents of the trimming register. That is, in the normal shooting mode in which no trimming is performed within the viewfinder field of view, the frame FO is displayed, and each time the switch s3 is turned on, the frame FO is displayed.
Each frame is displayed in the order of O → F1 → F2 → F3, and each time Sui-Tsuchi s4 is turned on, F3 → F2 → Pi-F
Each frame is displayed in the order of O. This display allows the photographer to confirm the glint area. Next, according to FIGS. 8 and 9, #2 in FIG.
4 NCP FILM input. ! : ICP CAM
The ERA output flowchart will be explained. First, for the ICP FIIJI input, set the read mode designation data to the transmission register in the CPUI (#60
>>, also set the number of received bytes, that is, the number of bytes of ICP FILl4, in the transmit register (#6 1)
．． Next, the circuit selection signal CS, which has the function of controlling circuit operations within the cartridge and controlling the serial data input/output terminals (SIN, SOUT), is set to high level (#62), enabling data input/output with the cartridge. Then, the read mode designation data and the number of received bytes set in #6o and #61 are output to the cartridge side according to the serial clock (#63).When the output is completed, the ICP FII of the memory in the cartridge is
Set the address of H in the transmission register (#64) and output it (#65). Then, after waiting for a predetermined time for processing on the cartridge side (described later) (#66),
Input ICP FHI4 according to the serial clock (
#67), and stores the data in the memory within the CPUI (#68). Finally, the communication is ended by shifting the CS signal to low level (#69). Next, in the ICP CAl4ER^ output shown in Figure 9, write mode designation data is set in the transmission register (#70
), and also sets the number of write bytes, that is, the number of bytes of ICP CAHER^, in the transmission register (#71).
Next, as with the ICP FILM input, the CS signal is set to High level to enable data input/output (#
72), the write mode designation data and the number of write bytes are output to the cartridge side according to the serial clock (#73). When the output is completed, the address to which ICP GAMERA in the cartridge internal memory is written is set in the transmission register (#7 4. >, and this is output (#75). When the address output is completed, the read/write on the cartridge side is performed. Write mode determination and ICP CAl4
After waiting for a time to determine whether it is an ERA address or not (#751), the ICP CAHERA data is set in the transmission register (#76), and the data is output according to the serial clock (#77).Next After waiting a predetermined time for the cartridge to determine whether the camera is compatible with the cartridge (#771), the CS signal is set to Lo.
Set to W level (#78) and end communication. Next, the processing at the time of reading and writing data will be explained with reference to FIGS. 10 and 11. First, when reading, that is, when inputting FIL}l DATA, set the read mode designation data to the transmission register in the CPUI (#80), and also set the total number of bytes of information to be read to the transmission register ( #81)
．． Next, the CS signal is set to High level to enable data input/output (#82), and according to the serial clock,
#80. Output the data set in #81 to the cartridge side (#83). When the output of the read mode designation data and the number of input bytes is completed, the start address of the cartridge internal memory where the input data is stored is set in the transmission register (#84), and this is output (#8
5). Wait for processing time in the cartridge (#86), and input data corresponding to the output address according to the serial clock (#87). The input data is sent to the CPU
Stored at the corresponding address in memory in I (#8
8). Next, determine whether all data has been input (
#89), if all data has not been entered yet, #8
Return to step 6 and enter data until all data is entered. When all data has been input, the CS signal is set to low level (#90) and communication is terminated. Next, we will explain the processing during writing. First, write mode specification data and the total number of bytes of write data are set in the transmission register (#91, #92》.Next, the CS
Set the signal to High level (#93》, #91, #9
In step 2, output the data to the transmission register to the cartridge side (#94). When the output is completed, set the start address where the data in the cartridge internal memory will be written to the transmission register (#95>, and output it (#94). 96).When the address output is completed, the data (i.e., ICP
After waiting for a time to determine whether the data is (other than CAHEII^) (#961), the write data is set in the transmission register (#97), and output according to the serial clock (198>, Next, it is determined whether the output of all data has been completed (#99), and if it has not been completed, the process returns to #97 and the next data is output.When the output of all data is completed, the CSI number is set to Low level (#100), and the communication is terminated. In addition, in Figures 10 and 11, the data address specification is the first address (sequential access).
However, before data is input/output, the address to which the data will be successively output/written may be specified at any time (random access). The operation of the camera side has been explained above, and now the structure and operation of the first embodiment on the film cartridge side will be explained. Figure 12 shows the block configuration of the cartridge. It has eight terminals for communication with the camera and for power supply. Vo, GND are terminals for power supply. φ is the terminal for inputting the system clock φ for circuit operation inside the cartridge from the camera. RESET is executed by a microcomputer (hereinafter referred to as μ) that controls each block in the cartridge.
This terminal is abbreviated as COM and resets 50. When a cartridge is loaded into the camera and the camera is turned on, a RESET signal is input. CS is a terminal into which the CS signal for input/output control from the camera mentioned above is input. SIN, SOUT, and SCK are terminals for serial communication, and each signal is serial data input, serial data output, and serial clock. is given, and data communication with the camera is performed through these three terminal lines. The μCOM50 has an internal memory of a RAM area tIA51 and a ROM area 52, and when the CS signal from the camera becomes 'H', an interrupt (INTI) is generated and the μCOM
50 starts data communication operation. 53 is SIN, S
An interface that controls the OUT and SCK signals. Data input/output is controlled by signals from μCOM50.
J9 cheat. 54 is a register for temporary storage, and E2P
When writing data to ROl455, write data is stored once, and at the timing when CS is inverted to 'H', 'empty' and 'L', this stored data is written to E2PRQH55 by a signal from μCOM50. When reading data, the read data is once captured and output to the camera via the interface 53 in response to the SCK signal.Furthermore, the write/erase control unit 56 writes data to the E2PROH5 and erases the data. The booster 57 generates a high voltage for the E2PROH55.The control H56 and booster 57 operate according to control signals from the μCOM50.The μCOM50, interface 53, and register 54 are connected by a data bus 58. mutual data communication is performed through this data bus 58. Next, the processing of μCOM 50 is shown in FIG.
This will be explained using Figures 14 and 15. When a film cartridge is loaded into the camera and the power of the camera is turned on, the process of the RESET flowchart shown in FIG. 13 is performed. t. First, perform a normal microcomputer reset operation (#110). Next, enable the interrupt INTI by the CS signal from the camera (#111), and wait for the CS signal to become "H1gh" (that is, the interrupt INT1 is applied). The CS signal is
When it becomes ``H'', it moves to the INT1 routine shown in Fig. 14.In the INTI routine shown in Fig. 14, INTI
interrupts (#120) and input the obecode (#121), where the obecode indicates the data indicating continuous output mode or write mode and the total number of bytes communicated (#60, # 61. #70, #71, #
80. See #81, #91, #92》. Next, input the start address of the data (#122). And #12
Based on the obecode input in step 1, it is determined whether or not data is to be read (#123), and if it is a read, the process goes to the READ routine, and if it is not a read, that is, if it is a data write, the process goes to the WRITE routine shown in FIG. In the READ routine, the input address is ICP FIll4
(#124), and determines whether the address is JCP FI
If LH No. 7 de 1 and 4 are present, the ICP FILM stored in the ROM 52 is output (#125>, CS=L
Wait for (completion of communication) (#130), enable the INTI interrupt (#131), and wait for the interrupt INT1 to occur again. If it is not the address of ICP FIIH in #124 above, the data is related to photography, so the data corresponding to the address is transferred from the E2PROH55 to the register 54 (#126), and the data is output (#127).
, Next, it is determined whether all data to be communicated (all data requested from the camera) has been output (#128).
, if the output is not completed, increment the address in the E" PROM 5 by 1 (#129), return to #126, and repeat from #126 to #12 until all data has been output.
Repeat the routine up to 9. When the output of all data is completed, the process moves to #130, waits for the CS signal to become 'L', enables the INTI interrupt (#131), and waits for the interrupt INTI to be applied again. Above #123 If it is determined that it is in the write mode, the process moves to the WFt I TE routine shown in Figure 15. First, the address input in #122 above is the ICP G
Determine whether it is an AMERA address (#140),
If it is an ICP CAMERA address, enter the ICP CAMERA from the camera side (#141), then enter the unique ICP CA of each film cartridge.
MERA Ref and input NCP CAMERA
(# 142, # 143 >>. As a result of the comparison, if the two do not match, the operation of μCOM50 is stopped. This prevents reading and writing of incorrect data and prevents malfunctions. If they match, wait for the CS signal to become “Yes” (#144)
．． Enable interrupts (#145), then interrupt INT again.
Wait for I to be called. On the other hand, in #140 above, if the address input in #122 is not the address of ICP CAMERA, write/erase control is performed from the address input in #122 to the number of bytes input in #121 of E2PROI455 data. 56 ($146). When the erasure is completed, the input data is temporarily stored in the register 54 (#147), and the data continues to be stored in the register 54 until all data input is completed (#148).
, it is assumed that the register 54 has a capacity to store all data related to single-frame photography. When input of all data is completed, wait until the CS signal becomes "off" (completion of communication) (#149), write the data stored in the register 54 to the E2PROH 55 (#150), and then Enable INT1 interrupts (#145),
Wait for the interrupt INTI to be issued again. Figure 16 shows E2PRO1455 in the cartridge internal memory.
This shows the relationship between addresses and stored data. The address indicated by the upper two bits is obtained from the lower two bits of the above-mentioned obecode. Also, lower addresses are expressed in hexadecimal to simplify the diagram. Each piece of data is stored in the order in which a plurality of pieces of data are determined for each frame, starting from the first frame of the film, that is, in the order of shooting year, month, day, cropping magnification, and so on. In addition, data stored after 80H is mainly used in DP stores and laboratories.
This information includes information on film characteristics and film properties. in this way,
All data is stored at predetermined addresses. Next, a second embodiment of the film cartridge internal circuit will be explained using FIG. 17. The power cartridge has five terminals for connecting to the camera. Terminals V, o, SCK, CS, and GND are the same as in the first embodiment. SIN/OUT terminal is the 12th
The serial input terminal SIN and serial output terminal SOUT shown in the figure are combined into one terminal, and input/output can be switched by analog switches 113 and 114. Data input from the S IN/OUT terminal is stored, for example, one byte at a time in the shift register 100, and latched in the operation code latch 1103, address latch unit 104, and data register 105, respectively, and the latching timing is determined by the counter 101 and decoder 102. It is determined by Of the data latched by the operation code latch unit 103, read/write/erase mode designation data is input to a decoder 109, byte number data to a comparator 106, and address data to a counter 108. Then, the designated data from the decoder 109 is E
2PROH 111, and control signal WR
ITE, ERASE, READ are each decoder 1
02, erase g51jo for erasing the data in the E2PROH 111, and output to the read control unit 112 for reading the data. Counter 107 counts clock pulses from terminal AN4 of decoder 102. The converter 106 compares the counter value of the counter 107 with the total number of transmitted and received data bytes, and if they match, outputs a low level signal CQHP to the counter 101. Based on the address data from the counter 108, the write data from the data register 105, and the erase data from the eraser 110, the E2P
Data at the specified address of ROl4 111 is erased and written. Each part in the cartridge having the above structure in FIG. 18 shows the counter 101 in FIG. 17,
Details of the decoder 102 and data register 105
This is a diagram showing the s configuration. In the figure, when the CS signal from the camera changes from Low level to High level, the reset of counter 115 and counter 119 is released. Next, the serial Kuroduku SCK from the camera is at counter 115.
The counter 115 counts the serial clock pulses. Binary outputs 01, C2, C3 from the counter 115 are AND circuit 116
and the output COHP from the converter 106 is at the “H i g I].” level, the AND circuit 1
16, a high level signal is output for each byte (ANI). Output A from AND circuit 116
N1 is input to the delay circuit 117, and is also input to one of the AND circuits 148 in the decoder 102.The output delayed by the delay circuit 117 by a predetermined time is:
The signal is inverted and input to the one-shisit circuit 118. The output of the one-shot circuit 118 is input to the clock terminal CK of the counter 119, and is also input to the AND circuit 120, 1.
21, 128-143 are input by one person. Counter 119 counts the output from F#I118 once and y times, and depending on the count value, terminals C4C5,
Output binary signals from C6, C7, and C8. Output 0
4 to C8 are input to AND circuits 120 and 121, and are also input to AND circuit 12 via AND circuits 123 to 127.
8 to 143, and furthermore, AND circuits 145 and N
AND circuits 123 to 1 which are also input to the OR circuit 144
WRIT from the decoder 109 is input to the other input of 27.
E signal is input. In other words, when writing data (W
Only when RITE = ``H'', the AND circuits 123 to 127 become active, and the output C4 is output to the AND circuits 128 to 143.
~The output of C8 is input. Table 1 below shows the outputs of AND circuits 120, 121 and AND circuits 128 to 143 during data writing, and output 0.
This shows the relationship between 4 and CB. From Table 1, when the outputs of AND circuits 128 to 143 go from "L" to "H",
Register A of the data register 105 corresponding to each
~P receives data from the shift register 100. Further, the output of the NOR circuit 144 and the output of the AND circuit 145 are input to an OR circuit 146, the output of the OR circuit 146 is input to one of the OR circuits 147, and the WRITE signal is input to the other input. The output signal IN/OUT of the OR circuit 147 is connected to the analog switches 113 and 114.
This is the signal used by ffilJ. That is, the signal IN/O
When UT is "H", the analog switch 113 is conductive and the analog switch 114 is non-conductive, and data from the camera side is input to the shift register 100. Then, when the signal IN/OUT is "L", the analog switch 113 becomes non-conductive and the analog switch 114 becomes conductive, so that data is output from the power cartridge to the camera. In addition, the output AN3 of the AND circuit 121
is input to the set terminal of the flip-flop 150. In the above configuration, we will explain the operation when communicating data with the camera. At the beginning of data communication, signal C
S becomes "H" and the counter 115 starts counting the serial clock CS. Note that at this time, the output COHP of the converter 106 is "14". The obecode from the camera is input to the shift register 100 according to the evening lock, and when the input of the obecode (1 byte) is completed, the output of the AND circuit 116 becomes 'H' and a pulse is output from the one-shot circuit 118.Counter 11
9 was reset until the signal CS became "H", so its outputs 04 to C8 are all "Yes". Therefore, the AND circuit 120 outputs the opcode latch timing signal AN2. This signal AN2 causes the data in the shift register 100 to be transferred to the operation code latch section 103.
is input into . The output of the one-shot circuit 118 is 'L''
Then, the output C4 of the counter 119 becomes "H".
Next, when the second byte of data (address data) is input to the shift register 100, a pulse is output from the one-shot circuit 118 in the same way as the first byte.At this time, only C4 is output from the counter 119. Since the address latch timing signal AN3 is high, the AND circuit 121 outputs the address latch timing signal AN3. This allows shift register 10
Address data of 0 is input to the address latch unit 104. When the obecode is latched, the decoder 10 of FIG.
9 sets the output READ to "I{" in the case of reading, sets the output WR I'l to "H" in the case of writing, and sets the output ERASE to "H" in the case of erasing. Therefore, input data is transferred to the data register 105 in accordance with the timing signals of the AND circuits 128 to 143 only in the case of data writing. Then, when the signal CS becomes "Yes", the contents of the data register 105 are changed to E2PRO in response.
It is written to the specified address of H111. The details of reading and erasing will be explained later. Also, the first two bytes are always the signal IN by the NOR circuit 144, AND circuit 145, and OR circuits 146 and 147.
/OUT becomes “H” and enters write mode (input). After that, if the WRITE signal is "H", the signal IN/OUT remains "H", that is, the write mode remains, and if the WRITE signal is "L", the signal I
N/OIIT becomes “L” and the read mode becomes “output”. Next, the relationship between addressing and the number of bytes will be explained using FIGS. 17 and 18. Among the obecodes latched by the opcode latch timing signal AN2, communication byte number data is input to the comparator 106. On the other hand, the address data latched by the address latch timing signal AN3 and the address data in the previously latched obecode are input to the preset input terminal of the counter 108. At this time, the signal AN3 is input to the set terminal of the flip-flop 150, so after the communication of 2 bytes is completed, the signal AN3 is always input to the set terminal of the flip-flop 150.
The Q output becomes "H", and the AND circuit 148 becomes active. Every time one byte of communication is completed, the signal ANI is
The output AN4 of the AND circuit 148 becomes H' and the output AN4 of the AND circuit 148 becomes Hn.Then, the counters 107 and 108 count the output AN4 of the AND circuit 148.On the other hand, it does not indicate that the communication of the first two bytes has been completed. The signal AN3 is also input to the delay circuit 151,
When the address is input to the preset enable terminal PE of the counter 108 after a delay of a predetermined time, the address that was checked earlier is input to the E2PRON 111. Thereafter, each time one byte of communication is completed, the counter 108 increments the address by one. During this time, the counter 107 outputs the number of transmitted and received bytes to the comparator 106, and when the first latched number of bytes (that is, the total number of transmitted and received bytes) matches the current number of bytes, the COHP signal is set to "L". Since this signal is a single input of the AND circuit 116 in FIG. 18, when the required number of bytes of communication is completed, the AND circuit 116 becomes non-conductive and the counters 107 and 108 stop counting. In addition, the counters 107 and 108 are input when the signal CS is w.
It is reset when it reaches L n. Note that when writing data, if data has already been written to the memory area in which the E2PROM data should be written (i.e., when exchanging data), write to that memory head area immediately before writing the data. Erases the stored data.The operation of this data erase is explained below.When writing as described above, data is written for the specified number of bytes in order from the specified start address. . 19 shows the configuration of the readout control unit 112, etc.;
Erase and read control will be explained. There are two types of erasing: erasing all stored data and erasing old data when writing new data. When erasing all data, when command data for erasing all data is set in the OBE code, the erasing section 110 is activated by the ERASB signal from the decoder 109, and all data in the E2PRIM 111 is erased. To erase data, signal CS is “H”
This is done at the timing of the change from ``shi'' to ``shi''. on the other hand,
When writing new data, first set the command data for partial erasure in the OBE code, and specify the address to write and the number of bytes of data to write. Then, the signal CS is “L”
”, the data stored in the memory area of the specified number of bytes starting from the specified address will be erased.
After that, data is written as described above. Next, read control will be explained. When the data indicating the read mode and the address of the ICP FHH are input, the IC stored in the E2PIIOH 111
PFILM is transferred to ICP FILM read register 153. The trigger terminal PIN of the register 153 has
It is connected to the output terminals of AND circuits 121 and 148 via an AND circuit 149, a delay circuit 152, and an OR circuit. The register 153 is connected to the AND circuit 121.
The output AN3 of the AND circuit 148 or the output AN4 of the AND circuit 148 is “
ICP F is not transferred after a predetermined period of time after it becomes H”.
Import IIH one byte at a time. And the same register 1
When ICP FILM is input to 53, the clock SC
According to K, ICP FILM is connected to SIN/OtlT terminal, l:') output saler. At this time, FHl4 DATA
The output from the read register 154 is always 'L'. Also, the control signal IN/ of the analog switch 114
OUT is "L" and the analog switch 114 is in a conductive state.IcP CA}4ER from the camera
When ^ is written to the PflOH111, the written ICP CAMERA and JCP CAMERA Ref data previously stored in the E2PIIOH111 are transferred to the respective registers 1ss and ise, and the data is further transferred to the comparator 151. IC written in
Determine whether it matches P CAMERA. If they match, the signal ROK is set to "H" to enable data reading. This signal ROK is input to gate 158. If they do not match, the signal ROK is set to "off" to prohibit data reading. If gate 158 is enabled, the first data is input to register 154 in response to address latch timing signal AN3 and clock SC
Output according to K. Note that the cteiay circuit 152
Therefore, the timing at which data is input to the register 154 is delayed by a predetermined time from the time when the signal AN3 becomes "H".
The next data is input to register 154 in response to byte completion signal AN4. In this way, data is output until the necessary data is output or until the signal CS becomes "L". Note that the address specification when reading is the same as when writing. Also, even when writing, the counter 108
The data stored at the address specified by is in register 1.
However, since the READ signal is "L", the output of the AND circuit 149 does not become 'H', and the registers 153 and 154 do not take in the data. shows the timing chart of the data communication explained above. Fig. 20 shows the timing during normal data communication. When the signal CS becomes "H" (to), data communication starts. SCK is input, and in accordance with it, an obecode (read/write and erase mode and number of bytes of communication data) is input from Sl/0@child.
As shown in the figure, the clock SCK remains at the "L" level for a predetermined period of time after the continuous pulse 8a. When the input of the obecode is completed (t1), the AN2 signal becomes "H", thereby latching the obecode. Next, the data address is input according to the clock SCK, and when the input is completed (t2), the AN3 signal is
This causes the address to be latched into the address latch section. When the input of the obecode and address is completed, data communication is performed. When the obecode is latched, the mode is determined, and in the case of read mode, In the case of data output and write mode, data is input.And, in the erase mode, the data in all memory areas of the E2PROM or the specified memory area is erased.One byte of data is Once the input/output is complete,
The counters 107 and 108 perform the operations described above in response to the AN4 signal. When the second byte data communication is completed (t
The same applies to 4). Data communication is performed as described above, and when all necessary data has been communicated, the COHPm signal from the converter 106 changes from "H" to "L".
As a result, the AN4 signal remains at the Low level, and the counters 107 to 108 stop their counter operations. Then, when the signal CS becomes "L" (70), data communication ends. Note that in the case of write mode, data is written from the register 105 to the E2PIIOH 111 at time t6. Figure 21 shows ICP FILI4 and ICP GAMER
This is a timing chart regarding the communication of ^, and the latch timing etc. are the same as in Fig. 20. First, enter the obe code. This sets the read mode for the camera to read ICP FILM one after another, and the number of bytes of ICP FIll4 (1 byte in Fig. 21, but it may be multiple bytes). Once you have completed entering the obecode, enter the icprIv address. When the address input is completed, the IN/OUT signal switches from low to high, and the ICP outputs according to the clock SCK.
FILM is output from Kartori Tsuji to the camera.
When the ICP FIIH output is completed, the C from the camera is
The S signal goes low and communication ends. The camera then receives the ICP FJLM and determines whether the cartridge is compatible. Then, if the cartridge is compatible, the camera outputs ICP CAMERA, but before that, first, in order to erase the old ICP CAMERA stored in the memory in the cartridge, erase mode is set on the obe code. ICP CAHE
Outputs the RA address (1 byte in the figure). Then, when the camera finishes outputting the address of ICP CAHER^, it sets the signal CS to "L" (t7), and the signal C
When S becomes "L", the eraser 110 erases the previously stored ICP CAHER^. Once the erasure is complete, the camera will use the new ICP CAHER^, i.e. the ICPF I input from the loaded cartridge.
I. Outputs ICP CAMERA corresponding to H. i.e. write mode and ICP CAM in opcode
The number of bytes of ERA (1 byte in the figure) is set and output, and then the address of ICP CAHER^ is output. When the cartridge completes the input of the OBE code and address, it inputs ICP CAMERA, and the signal CS is output. When it becomes 'L'' (t8), ICP to E2PROl4 river
Write CAM[RA. The cartridge is a written IC
P CAMERA and ICP CAHE stored in advance
IIA Ref is compared by the comparator 151, and if the two match, the signal ROK from the comparator 157 is set to "H" (time t9) to enable reading of information (data). As shown, the gate 158 becomes conductive and data reading becomes possible.ICP
If CAHER^ and ICP C^HERA Ref do not match, the signal ROK remains "[," and the gate 158 remains non-conductive, making it impossible to read data. The data exchange between the camera and the film cartridge has been explained above, but as shown in Figure 16, the memory inside the cartridge also stores data used at the DP store and the laboratory, and the data exchange with the equipment at the DP store and the laboratory is also stored. Data communication is also performed in the same manner as in the above embodiment. (Hereafter, blank space) Table 1

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the entire system of a camera according to an embodiment of the present invention, FIG. 2 is a block diagram of the accessory 6 shown in FIG. 1, and FIGS. 3 and 4 are CPUs in the camera body.
FIG. 5 is a flowchart showing the operation of FIG. 5 is a diagram explaining the ID code communicated between the camera side and the cartridge side. FIG. 6 is a flowchart of the trimming setting operation.
The figure shows the display mode within the viewfinder field of view, Figure 8 is a flowchart showing the operation of code ICP FILH input, Figure 9 is a flowchart showing the operation of code ICP CAMERA output, and Figure 10 shows the operation of FIIH DATA input. 11 is a flowchart showing the data writing operation, FIG. 12 is a block diagram of the first embodiment on the cartridge side, and FIG. 13 is a RESE
FIG. 14 is a flowchart showing the INT1 routine, FIG. 15 is a flowchart showing the WRITE routine, FIG. 16 is a diagram showing the relationship between addresses and data in the memory in the cartridge, and FIG.
18 is a detailed configuration diagram of the decoder 102 etc. in FIG. 17, FIG. 19 is a configuration diagram of the readout control unit 112, and FIGS. 20 and 21 are This is a timing chart of data communication. DESCRIPTION OF SYMBOLS 1... Control microcomputer (including discrimination means and output means), 10... Film section, 5o... Microcomputer, 52...
ROM, 55...E2 FIROM (memory section}, 33
．． 34...Trimming setting switch (trimming magnification setting means). Figure Applicant: Agent for Minolta Camera Co., Ltd.
Yasuo Itaya, Patent Attorney

Claims (1)

[Claims] (1) Trimming magnification setting means for setting a plurality of different cropping ranges for the same screen in a camera that can switch between a normal shooting mode for shooting a normal shooting range and a trimming mode for setting a narrower cropping range. a storage section for storing limits of trimming magnification other than film sensitivity; a determining means for determining whether or not the set trimming magnification exceeds the limit; What is claimed is: 1. A camera having a trimming photographing function, characterized in that it is equipped with an output means for outputting an output.