JPH022315B2 - - Google Patents

Info

Publication number
JPH022315B2
JPH022315B2 JP55149464A JP14946480A JPH022315B2 JP H022315 B2 JPH022315 B2 JP H022315B2 JP 55149464 A JP55149464 A JP 55149464A JP 14946480 A JP14946480 A JP 14946480A JP H022315 B2 JPH022315 B2 JP H022315B2
Authority
JP
Japan
Prior art keywords
linear expansion
laminate
fiber
semiconductor device
cloth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55149464A
Other languages
Japanese (ja)
Other versions
JPS5773990A (en
Inventor
Tetsuo Kumazawa
Hiroaki Doi
Yasuo Myadera
Atsushi Fujioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Hitachi Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP14946480A priority Critical patent/JPS5773990A/en
Publication of JPS5773990A publication Critical patent/JPS5773990A/en
Publication of JPH022315B2 publication Critical patent/JPH022315B2/ja
Granted legal-status Critical Current

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 本発明はリード線レス半導体装置の実装構造に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mounting structure for a lead wireless semiconductor device.

リード線レス半導体装置とは金属リードの電極
を持たず、はんだなどの電極を持つセラミツクな
どで作られた半導体用ケース例えば、チツプキヤ
リア、リードレス・インバーテツド・デバイスま
たはシリコン素子などを指す。
A leadless semiconductor device refers to a semiconductor case made of ceramic or the like that does not have a metal lead electrode but has an electrode such as a solder, such as a chip carrier, a leadless inverted device, or a silicon element.

従来のリード線レス半導体装置の実装構造の一
例を第1図および第2図に示す。
An example of the mounting structure of a conventional lead wireless semiconductor device is shown in FIGS. 1 and 2.

第1図a,bはシリコン素子1をアルミナ基板
2へはんだなどのろう材3により接続したものを
示しており、この接続法はフリツプチツプボンデ
イングと呼ばれている。
FIGS. 1a and 1b show a silicon element 1 connected to an alumina substrate 2 by a brazing material 3 such as solder, and this connection method is called flip-chip bonding.

第2図a,bはアルミナ材のチツプキヤリア4
をガラス布製基材にエポキシ樹脂を含浸させた印
刷配線板5へはんだなどのろう材6により接続し
たものを示している。
Figure 2 a and b show alumina chip carrier 4.
is connected to a printed wiring board 5 made of a glass cloth base material impregnated with epoxy resin by a brazing material 6 such as solder.

第1図および第2図に示すようなシリコン素子
1またはチツプキヤリア4をアルミナ基板2また
は印刷配線板5にろう材3,6により接続した構
造では、温度変化が繰り返し加わると、ろう材
3,6が疲労破壊する。
In a structure in which a silicon element 1 or a chip carrier 4 is connected to an alumina substrate 2 or a printed wiring board 5 by brazing fillers 3 and 6 as shown in FIGS. 1 and 2, repeated temperature changes may cause the brazing fillers 3 and 6 to will fail due to fatigue.

これを第2図a,bに示すチツプキヤリア4を
例にあげて、第3図により説明する。
This will be explained with reference to FIG. 3, taking as an example the chip carrier 4 shown in FIGS. 2a and 2b.

第3図は第2図に示したチツプキヤリア4のろ
う材6の部分を拡大した図で、第3図において、
アルミナ材のチツプキヤリア4はガラス布製基材
にエポキシ樹脂を含浸させた印刷配線板5上の導
体7へろう材6により接続されている。
FIG. 3 is an enlarged view of the brazing material 6 of the chip carrier 4 shown in FIG.
A chip carrier 4 made of alumina material is connected by a brazing material 6 to a conductor 7 on a printed wiring board 5 made of a glass cloth substrate impregnated with epoxy resin.

この構造において、温度変化△Tが加わると、
印刷配線板5の伸びと、チツプキヤリア4の伸び
の差が生じ、ろう材6の印刷配線板5側とチツプ
キヤリア4側にずれ△l △l=l・△α・△T/2 ……(1) が生ずる。(1)式において、△αは印刷配線板5と
チツプキヤリア4の線膨張係数の差で、lはチツ
プキヤリア4の大きさである。
In this structure, when a temperature change ΔT is added,
There is a difference between the elongation of the printed wiring board 5 and the elongation of the chip carrier 4, and the brazing filler metal 6 shifts between the printed wiring board 5 side and the chip carrier 4 side △l △l=l・△α・△T/2 ...(1 ) occurs. In equation (1), Δα is the difference in linear expansion coefficient between the printed wiring board 5 and the chip carrier 4, and l is the size of the chip carrier 4.

このずれ△lにより、ろう材6には近似的にせ
ん断ひずみγ γ=△l/h ……(2) が生ずる。(2)式において、hはろう材6の厚さで
ある。
This deviation Δl causes approximate shear strain γ γ=Δl/h (2) in the brazing filler metal 6. In equation (2), h is the thickness of the brazing filler metal 6.

温度変化が繰り返されると、(以下温度サイク
ルと呼ぶ。)ろう材6にせん断ひずみγが繰り返
し生じ、ろう材6が疲労破壊する。ろう材6の疲
労破壊までの温度変化の繰返し数(以下温度サイ
クル寿命と呼ぶ。)Nは N=C/γ2 ……(3) と表わされる。(1),(2)式を(3)式へ代入すると、 N=C(2h/l・△α・△T)2 ……(4) と表わされる。(4)式において、Cははんだの材質
などにより決る定数である。
When temperature changes are repeated (hereinafter referred to as temperature cycles), shear strain γ is repeatedly generated in the brazing filler metal 6, causing fatigue failure of the brazing filler metal 6. The number of repetitions of temperature changes (hereinafter referred to as temperature cycle life) of the brazing filler metal 6 until fatigue failure occurs is expressed as N=C/γ 2 (3). Substituting equations (1) and (2) into equation (3), it is expressed as N=C(2h/l・△α・△T) 2 ...(4). In equation (4), C is a constant determined by the material of the solder.

(4)式より温度サイクル寿命は、チツプキヤリア
4と印刷配線板5の線膨張係数の差が小さいとき
には長く、差が大きいときには短いことがわか
る。
From equation (4), it can be seen that the temperature cycle life is long when the difference in linear expansion coefficient between the chip carrier 4 and the printed wiring board 5 is small, and short when the difference is large.

シリコン、アルミナ、ガラス布製基材エポキシ
樹脂の線膨張係数はそれぞれ3×10-6-1,6〜
8×10-6℃,13〜20×10-6℃と差が大きいため、
シリコン素子1をアルミナ基板2に接続したり、
アルミナ材のチツプキヤリア4をガラス布製基材
エポキシ樹脂を含浸させた印刷配線板5に接続し
た場合、これらの接続の温度サイクル寿命はかな
り制限される。
The linear expansion coefficients of silicone, alumina, and glass cloth base epoxy resin are 3×10 -6-1 and 6~, respectively.
Because there is a large difference between 8×10 -6 ℃ and 13 to 20×10 -6 ℃,
Connecting the silicon element 1 to the alumina substrate 2,
When alumina chip carriers 4 are connected to a glass cloth substrate epoxy resin impregnated printed wiring board 5, the temperature cycling life of these connections is considerably limited.

最近、このようなリード線のない半導体装置を
実装できる基板の積層用クロスとして負の線膨張
係数を有する芳香族系のポリアミド繊維製クロス
例えば、ケブラー繊維クロス(デユポン社の登録
商標)が使用されている。このクロスを用いて、
基板を製作する場合、基板の線膨張係数はクロス
の繊維含有率によつて決る。
Recently, aromatic polyamide fiber cloth with a negative coefficient of linear expansion, such as Kevlar fiber cloth (registered trademark of DuPont), has been used as a lamination cloth for substrates on which semiconductor devices without lead wires can be mounted. ing. Using this cross,
When manufacturing a substrate, the coefficient of linear expansion of the substrate is determined by the fiber content of the cloth.

第4図は芳香族系のポリアミド繊維としてケブ
ラ繊維クロスを用い、熱硬化性樹脂としてエポキ
シ樹脂を用いて基板を製作した場合のケブラー繊
維の体積含有率と基板の線膨張係数の関数を示し
たものである。
Figure 4 shows the function of the volume content of Kevlar fibers and the coefficient of linear expansion of the substrate when the substrate is manufactured using Kevlar fiber cloth as the aromatic polyamide fiber and epoxy resin as the thermosetting resin. It is something.

しかしながら、上述の芳香族系のポリアミド繊
維製クロスはガラスクロスに比べて極めて高価で
あり、また、マトリツクスとして使用するエポキ
シ樹脂、シリコン樹脂、不飽和ポリエステル樹脂
等の樹脂との親和性がガラスクロスに比べて劣る
ため、積層板中でクロスを境面にして剥離が生じ
易いという問題点を有する。
However, the above-mentioned aromatic polyamide fiber cloth is extremely expensive compared to glass cloth, and glass cloth is less compatible with the resins used as matrices, such as epoxy resin, silicone resin, and unsaturated polyester resin. Since it is inferior in comparison, there is a problem in that peeling tends to occur in the laminate at the cross border.

一方、半導体装置は動作中に発熱する。半導体
装置が正確に動作するためにはこの熱を放熱し、
半導体装置の過熱を防ぐ必要がある。半導体装置
で生じた熱は半導体装置の表面から放出された
り、基板へ伝導したりして放散される。
On the other hand, semiconductor devices generate heat during operation. In order for semiconductor devices to operate accurately, this heat must be dissipated.
It is necessary to prevent overheating of semiconductor devices. Heat generated in a semiconductor device is dissipated by being released from the surface of the semiconductor device or conducted to the substrate.

従つて、半導体装置が塔載される基板は熱伝導
率が大きいことが望ましい。
Therefore, it is desirable that the substrate on which the semiconductor device is mounted has high thermal conductivity.

しかし、芳香族系のポリアミド繊維は熱伝導率
が比較的小さいので、この繊維と熱硬化性樹脂か
ら成る基板の熱伝導率は、ガラス布基材エポキシ
樹脂基板やアルミナ基板に比べて小さいため、芳
香族系のポリアミド繊維と熱硬化性樹脂から成る
基板に搭載された半導体装置は過熱し易くなると
いう欠点を有する。
However, aromatic polyamide fibers have a relatively low thermal conductivity, so the thermal conductivity of a substrate made of these fibers and a thermosetting resin is lower than that of a glass cloth-based epoxy resin substrate or an alumina substrate. Semiconductor devices mounted on substrates made of aromatic polyamide fibers and thermosetting resins have the disadvantage of being easily overheated.

更に、積層板中の繊維含有率が多過ぎた場合や
少な過ぎた場合には、樹脂中の繊維の配列が乱れ
易く、積層板中に局部的に繊維含有率の不均一な
部分を生じることがある。このような不均一な部
分を持つ積層板は寸法の経時変化が積層板の各部
で異なり、積層板の配線の相互位置のずれを生じ
させる。この現象をレジストレーシヨンと呼ぶ。
Furthermore, if the fiber content in the laminate is too high or too low, the arrangement of the fibers in the resin tends to be disordered, resulting in locally uneven fiber content in the laminate. There is. A laminate having such non-uniform portions has different dimensions over time in different parts of the laminate, resulting in misalignment of the wiring in the laminate. This phenomenon is called registration.

従つてこのレジストレーシヨンが発生すると、
多層配線基板(表面に導体配線を持つ積層板(第
一のプリプレグ。通常は所定枚数のプリプレグ層
の集合である。)を複数枚重ね合わせ、その際に、
各積層板の間にプリプレグ(第二のプリプレグ)
をはさんで加圧、加熱した印刷配線基板。通常、
第一のプリプレグと第二のプリプレグとは同材質
である。)や両面銅張り基板(複数枚のプリプレ
グ積層物の上下両面に銅配線を施した印刷配線基
板)においては各層の導体配線が水平方向に移動
して垂直方向に位置ずれを起こす。尚、片面(一
層)にのみ導体配線を施した印刷配線基板におい
てはレジストレーシヨンにより水平方向への配線
ずれを生じることになる。とりわけ配線(導通)
不良は垂直方向のずれをもたらす多層配線基板や
両面銅張り基板において重要な問題である。
Therefore, when this registration occurs,
Multilayer wiring boards (laminated boards with conductor wiring on the surface (first prepreg, usually a set of a predetermined number of prepreg layers) are stacked together, and at that time,
Prepreg between each laminate (second prepreg)
A printed wiring board that is pressurized and heated by sandwiching it. usually,
The first prepreg and the second prepreg are made of the same material. ) and double-sided copper-clad boards (printed wiring boards with copper wiring on both the upper and lower surfaces of a plurality of prepreg laminates), the conductor wiring in each layer moves horizontally, causing misalignment in the vertical direction. In addition, in a printed wiring board in which conductor wiring is provided only on one side (single layer), wiring deviation in the horizontal direction occurs due to registration. Especially wiring (continuity)
Defects are an important problem in multilayer wiring boards and double-sided copper-clad boards that cause vertical misalignment.

しかし、上述のケブラー繊維クロスから成る積
層板で所望の線膨張係数を持つ配線基板を作成す
るとき、この所望の線膨張係数を実現するための
積層板やプリプレグにおける芳香族系のポリアミ
ド繊維の繊維含有率は第4図に示すように決まつ
ているため、この繊維含有率においては基板作成
時にレジストレーシヨンが生じ易くなる場合があ
る。
However, when creating a wiring board with a desired coefficient of linear expansion using a laminate made of the above-mentioned Kevlar fiber cloth, aromatic polyamide fiber fibers in the laminate or prepreg are used to achieve the desired coefficient of linear expansion. Since the fiber content is determined as shown in FIG. 4, registration may easily occur at this fiber content when producing a substrate.

本発明者達は、従来技術が有する上記問題点を
解決すべく鋭意検討した結果、芳香族系のポリア
ミド繊維とガラス繊維とを組み合わせた複合クロ
スがマトリツクスとして使用する樹脂との親和性
が良く、積層板中でクロスを境面にして剥離が生
じ難く、熱伝導率が良く、かつ、レジストレーシ
ヨンが発生し難い実装構造を提供できることとを
見い出し、本発明に至つた。
As a result of intensive studies to solve the above-mentioned problems of the conventional technology, the present inventors found that a composite cloth made by combining aromatic polyamide fibers and glass fibers has good affinity with the resin used as a matrix. The present inventors have discovered that it is possible to provide a mounting structure in which peeling does not easily occur in a laminated board at cross boundaries, has good thermal conductivity, and is difficult to cause registration, and has thus arrived at the present invention.

本発明は上記の事柄にもとづいてなされたもの
で、マトリツクスとして使用する樹脂との親和性
が良く、積層板中でクロスを境面にして剥離が生
じ難く、熱伝導率が良く、且つレジストレーシヨ
ンが発生し難い長い温度サイクル寿命を得ること
ができるリード線レス半導体装置を提供すること
を目的とするものである。
The present invention has been made based on the above-mentioned points, and has good affinity with the resin used as a matrix, is difficult to peel off at the interface of the cloth in a laminate, has good thermal conductivity, and has good compatibility with the resin used as a matrix. It is an object of the present invention to provide a lead wire-less semiconductor device that can have a long temperature cycle life in which shock is less likely to occur.

本発明の特徴とするところは芳香族系のポリア
ミド繊維とガラス繊維とを混合撚糸した複合糸の
製織物から成る複合クロスを基材として使用し、
この複合クロスに熱硬化性樹脂を含浸させること
によりプリプレグを形成する。このプリプレグを
複数枚重ね合わせ、その表面に金属箔を導体配線
して中間積層物を形成し、更にこの中間積層物同
士を同じプリプレグで積層して加熱、加圧成形す
ることにより多層配線基板とする。或いはこのプ
リプレグを所定枚数積層してその両面に金属箔を
導体配線し同じく加熱、加圧成形して両面配線基
板とする。要するに複数枚数のプリプレグと複数
の金属配線層とを加熱、加圧成形して印刷配線基
板とする。リード線レス半導体装置の線膨張係数
にこれらの印刷配線基板の線膨張係数を合わせ
て、これらの印刷配線基板上にリード線レス半導
体装置を塔載するようにしたものである。
The present invention is characterized by using as a base material a composite cloth made of a composite yarn made of mixed twisted aromatic polyamide fibers and glass fibers,
A prepreg is formed by impregnating this composite cloth with a thermosetting resin. A multilayer wiring board is formed by stacking multiple sheets of prepreg, wiring metal foil as a conductor on its surface to form an intermediate laminate, and then laminating these intermediate laminates with the same prepreg and molding them under heat and pressure. do. Alternatively, a predetermined number of sheets of this prepreg are laminated, metal foil is conductor wired on both sides of the prepreg, and the same is heated and pressurized to form a double-sided wiring board. In short, a plurality of prepregs and a plurality of metal wiring layers are heated and pressure-molded to form a printed wiring board. The linear expansion coefficients of these printed wiring boards are matched to the linear expansion coefficients of the lead wireless semiconductor devices, and the lead wireless semiconductor devices are mounted on these printed wiring boards.

以下、本発明のリード線レス半導体装置の実装
構造の一実施例を第5図により説明する。
Hereinafter, one embodiment of the mounting structure of the lead wireless semiconductor device of the present invention will be described with reference to FIG.

第5図a,bは本発明のリード線レス半導体装
置の実装構造の一例として多層配線基板の場合を
示すものである。
FIGS. 5a and 5b show the case of a multilayer wiring board as an example of the mounting structure of the lead wireless semiconductor device of the present invention.

芳香族系のポリアミド繊維の一種であるケブラ
ー49繊維とガラス繊維を撚り合わせた複合糸を平
織りしたクロスに熱硬化性樹脂を含浸させること
によりプリプレグを作成し、これを所定枚数積層
してその一面に銅箔を重ねて加熱、加圧成形して
銅張積層板8とする。
Prepreg is created by impregnating a thermosetting resin into a plain-woven cloth made from composite yarns made by twisting Kevlar 49 fiber, a type of aromatic polyamide fiber, and glass fiber, and then laminating a predetermined number of sheets to create a prepreg. A copper clad laminate 8 is obtained by overlapping copper foil and heating and press-forming.

この銅張積層板8をホトエツチングし、表面に
銅配線9を形成し、さらにこの銅張積層板8を数
枚と前記プリプレグを相互に重ね合わせて加圧、
加熱し、穴明け、スルーホールメツキ、外層の銅
配線をホトエツチングで形成するなどの作業を行
うことにより印刷配線板が作られる。
This copper-clad laminate 8 is photo-etched to form copper wiring 9 on its surface, and then several copper-clad laminates 8 and the prepreg are stacked on top of each other and pressed.
Printed wiring boards are made by heating, drilling holes, plating through holes, and photo-etching copper wiring on the outer layer.

このように内部に銅配線9を有し、スルーホー
ル10を持つ銅張積層板8つまり印刷配線板には
コンピユータ用LSIを入れたアルミナ材のチツプ
キヤリア11がはんだ12により接続されてい
る。
As described above, an alumina chip carrier 11 containing a computer LSI is connected by solder 12 to the copper-clad laminate 8, ie, the printed wiring board, which has the copper wiring 9 inside and has the through holes 10.

第6図a,bは本発明のリード線レス半導体装
置の実装構造の他の例を示すもので、自動車用制
御ICであるシリコン素子の塔載構造の例である。
FIGS. 6a and 6b show another example of the mounting structure of the lead wireless semiconductor device of the present invention, which is an example of a structure in which a silicon element, which is a control IC for an automobile, is mounted.

スルーホール13や銅配線14を持つ積層板1
5つまり基板へシリコン素子16がはんだ17に
より接続されている。この積層板15は第5図に
示した多層印刷配線基板と同様な方法で作られ
る。この積層板15の線膨張係数はシリコン素子
16の線膨張係数に合わせてあり、自動車内は温
度変化が大きく、シリコン素子16と積層板15
とが等しい線膨張係数を持つことがシリコン素子
16の接続の信頼性を保つのに重要である。
Laminated board 1 with through holes 13 and copper wiring 14
5, a silicon element 16 is connected to the substrate by solder 17. This laminate 15 is made in the same manner as the multilayer printed wiring board shown in FIG. The coefficient of linear expansion of the laminate 15 is matched to that of the silicon element 16, and since there are large temperature changes inside an automobile, the coefficient of linear expansion of the laminate 15 is matched to that of the silicon element 16.
It is important to maintain the reliability of the connection of the silicon element 16 that they have the same coefficient of linear expansion.

上述の実施例では複合クロスを製作するのに芳
香族系のポリアミド繊維とガラス繊維を撚り合わ
せた複合系を平織りしている。
In the above-described embodiment, a composite cloth made by twisting aromatic polyamide fibers and glass fibers is plain-woven.

上述の積層板は複合クロスと熱硬化性樹脂の含
有率を変化させることにより、ある程度の範囲で
任意の線膨張係数を設定することができる。複合
クロスと熱硬化性樹脂の含有率の変化と積層板の
線膨張係数との関係は次の通りである。
The above-mentioned laminate can have an arbitrary coefficient of linear expansion within a certain range by changing the content of the composite cloth and thermosetting resin. The relationship between the change in the content of the composite cloth and thermosetting resin and the linear expansion coefficient of the laminate is as follows.

積層板の線膨張係数と繊維体積含有率(複合ク
ロスが積層板に占める割合。従つて積層板全体積
から熱硬化性樹脂の体積を差し引いたもの。)の
関係は近似的に次式(1)で示される。
The relationship between the coefficient of linear expansion of the laminate and the fiber volume content (the proportion of the composite cloth in the laminate; therefore, the volume of the thermosetting resin is subtracted from the total volume of the laminate) is approximately expressed by the following equation (1 ).

αisp=1/2〔(α11+α22) +(E11−E22)・(α11−α22)/E11+(1+2ν
12)・E22〕(1) αispは積層板の線膨張係数であり、(1)式中の各
記号は以下の(2)〜(7)式で示される。
α isp = 1/2 [(α 11 + α 22 ) + (E 11 − E 22 )・(α 11 − α 22 )/E 11 + (1+2ν
12 )・E 22 ](1) α isp is the linear expansion coefficient of the laminate, and each symbol in equation (1) is represented by the following equations (2) to (7).

α11=Vf・Ef・αf+Vn・En・αn/Vf・Ef+Vn・En(2
) α22=(1+νf)・Vf・αf +(1+νn)・Vn・αn−α11・ν12 (3) ν12=Vf・νf+Vn・νn (4) E11=Vf・Ef+Vn・En (5) E22=1+2Vf・η/1−Vf・η・En (6) η=Ef/Em−1/Ef/Em+2 (7) ここにfは繊維、mは樹脂、11は繊維方向、
22は繊維直角方向、Vは体積含有率、Eはヤン
グ率、αは線膨張係数、νはポアソン比を夫々意
味している。
α 11 =V f・E f・α f +V n・E n・α n /V f・E f +V n・E n (2
) α 22 = (1+ν f )・V f・α f + (1+ν n )・V n・α n −α 11・ν 12 (3) ν 12 = V f・ν f +V n・ν n (4) E 11 =V f・E f +V n・E n (5) E 22 =1+2V f・η/1−V f・η・E n (6) η=Ef/Em−1/Ef/Em+2 (7) Here, f is fiber, m is resin, 11 is fiber direction,
22 means the direction perpendicular to the fibers, V means the volume content, E means Young's modulus, α means the coefficient of linear expansion, and ν means Poisson's ratio.

また、以上の式により混合撚糸による複合繊維
の線膨張係数とヤング率とは近似的に次式(8),(9)
で表わされる。
Also, based on the above equations, the linear expansion coefficient and Young's modulus of composite fibers made of mixed twisted yarn can be approximately calculated using the following equations (8) and (9).
It is expressed as

αf=Vk・Ek・αk+VG・EG・αG/Vk・Ek+VG・EG(8) Ef=Vk・Ek+VG・EG (9) ここにKは芳香族ポリアミド繊維を示し、Gは
ガラス繊維を示す。
α f =V k・E k・α k +V G・E G・α G /V k・E k +V G・E G (8) E f =V k・E k +V G・E G (9) Here K indicates aromatic polyamide fiber and G indicates glass fiber.

第7図は番手22.5テツクス(1テツクスは10-6
Kg/m)のガラス繊維1本と番号22.5テツクスの
芳香族ポリアミド繊維(具体的には、ポリ―P―
フエニレンテレフタルアミド繊維)2本との混合
撚糸を平織りした複合クロスとエポキシ樹脂とよ
りなる積層板の繊維の体積含有率と積層板の線膨
張係数との関係を式(1)乃至式(9)を用いて計算した
結果(図中の実線)と測定した結果(図中の丸
印)であり、両者がほぼ一致していることがわか
る。この図に従い、複合クロス(又は熱硬化性樹
脂)の含有率を選べば、積層板の線膨張係数を決
定可能である。
Figure 7 shows the number 22.5 tex (1 tex is 10 -6
Kg/m) of glass fiber and aromatic polyamide fiber of 22.5 tex (specifically, poly-P-
Expressions (1) to (9) express the relationship between the volume content of fibers and the coefficient of linear expansion of the laminate of a laminate made of epoxy resin and a composite cloth prepared by plain weaving mixed yarns of two phenylene terephthalamide fibers. ) and the measured results (circles in the figure), and it can be seen that they almost match. By selecting the content of the composite cloth (or thermosetting resin) according to this figure, it is possible to determine the linear expansion coefficient of the laminate.

また、この複合クロスを用いた積層板は芳香族
系のポリアミド繊維のみから成るクロスより成る
積層板に比べて熱伝導率が大きく、積層板におけ
る繊維含有率をレジストレーシヨンを生じ難い値
のままでは複合クロスにおける芳香族系のポリア
ミド繊維とガラス繊維の複合割合を適切に決め、
所望の線膨張係数を持つ積層板を作成することが
できる。芳香族ポリアミド繊維とガラス繊維との
複合割合と積層体の線膨張係数との関係は、次の
通りである。
In addition, laminates using this composite cloth have higher thermal conductivity than laminates made of cloth made only of aromatic polyamide fibers, and the fiber content in the laminate remains at a value that does not easily cause registration. Then, we determined the appropriate composite ratio of aromatic polyamide fiber and glass fiber in the composite cloth.
A laminate having a desired coefficient of linear expansion can be created. The relationship between the composite ratio of aromatic polyamide fiber and glass fiber and the linear expansion coefficient of the laminate is as follows.

先ず上記の式(1)乃至(9)を用い、一例として複合
繊維の体積含有率が44.8%の場合のポリ―P―フ
エニレンテレフタルアミド繊維の体積含有率(繊
維の全体積に対するポリ―P―フエニレンテレフ
タルアミド繊維の体積割合)と積層板の線膨張係
数の関係を計算して第8図に実線で示す。図中の
丸印は番手22.5テツクスのガラス繊維1本と番手
22.5テツクスのポリ―P―フエニレンテレフタル
アミド繊維2本の混合撚糸を平織りした複合クロ
スを用いたポリ―P―フエニレンテレフタルアミ
ド繊維の体積含有率が77.6%の場合の実測値であ
る。
First, using the above formulas (1) to (9), as an example, when the volume content of the composite fiber is 44.8%, the volume content of poly-P-phenylene terephthalamide fiber (poly-P with respect to the total volume of the fiber) The relationship between the volume ratio of phenylene terephthalamide fibers and the coefficient of linear expansion of the laminate is calculated and shown as a solid line in Figure 8. The circle mark in the diagram is one glass fiber with a count of 22.5 tex and the count
This is an actual value when the volume content of poly-P-phenylene terephthalamide fiber is 77.6% using a composite cloth made by plain weaving two mixed twisted yarns of poly-P-phenylene terephthalamide fiber of 22.5 tex.

従つて第8図に従い、芳香族ポリアミド繊維の
含有率を選べば、積層板の線膨張係数を決定可能
である。
Therefore, by selecting the aromatic polyamide fiber content according to FIG. 8, the linear expansion coefficient of the laminate can be determined.

更に、熱硬化性樹脂の複合クロスへの含有率と
繊維の複合割合との関係を次に説明する。
Furthermore, the relationship between the content rate of thermosetting resin in the composite cloth and the composite ratio of fibers will be explained next.

上述の通り繊維体積含有率を変えることにより
所望の線膨張係数の積層板を得ることができる
が、実用的にはレジストレーシヨンを防ぐために
繊維体積含有率は40から60%が望ましい。樹脂と
芳香族ポリアミド繊維との組み合わせでは、所望
の線膨張係数を得られる繊維体積含有率が40%以
下になることがある。この点、芳香族ポリアミド
繊維とガラス繊維の混合撚糸では繊維の複合割合
を変化させることにより、繊維体積含有率は40か
ら60%で所望の線膨張係数の積層板を作成するこ
とができる。
As mentioned above, a laminate with a desired coefficient of linear expansion can be obtained by changing the fiber volume content, but in practical terms, the fiber volume content is preferably 40 to 60% in order to prevent registration. In the case of a combination of resin and aromatic polyamide fiber, the fiber volume content at which a desired coefficient of linear expansion can be obtained may be 40% or less. In this regard, by changing the composite ratio of fibers in a mixed twisted yarn of aromatic polyamide fibers and glass fibers, it is possible to create a laminate with a fiber volume content of 40 to 60% and a desired coefficient of linear expansion.

次に、実装する上で、基板の適正な線膨張係数
の範囲と搭載するリード線レス半導体装置の内容
について以下に説明する。
Next, upon mounting, the appropriate range of linear expansion coefficient of the substrate and the content of the lead wireless semiconductor device to be mounted will be explained below.

リード線レス半導体装置の接合はんだの疲労寿
命は基板とリード線レス半導体装置の熱膨張差と
使用環境の温度により生じる接合はんだのひずみ
の繰返しが原因である。この為、リード線レス半
導体装置を実装する基板の適切な線膨張係数の範
囲は、接合はんだのひずみがリード線レス半導体
装置に必要とされる寿命ではんだが破壊しないひ
ずみになるようなリード線レス半導体装置との熱
膨張差による。装置に必要とされる寿命は装置の
設計者が決めることになるが、接合はんだに発生
するひずみは以下の原因により決まる。
The fatigue life of the solder joint of a lead wireless semiconductor device is caused by the repeated strain of the joint solder caused by the difference in thermal expansion between the substrate and the lead wireless semiconductor device and the temperature of the environment in which it is used. For this reason, the appropriate linear expansion coefficient range for the board on which the lead wireless semiconductor device is mounted is such that the strain in the bonding solder is such that the solder does not break during the life required for the lead wireless semiconductor device. Due to the difference in thermal expansion with the non-contact semiconductor device. The lifespan required for the device is determined by the device designer, and the strain that occurs in the solder joint is determined by the following causes.

(a) 基板とリード線レス半導体装置の熱膨張差、 (b) 使用環境温度、 (c) リード線レス半導体装置の大きさ、並びに (d) 接合はんだの高さと形状。(a) Difference in thermal expansion between the substrate and the lead wireless semiconductor device, (b) Operating environment temperature; (c) Size of lead wireless semiconductor device and (d) Height and shape of solder joint.

例えば、対角線で20mm(従つて一辺14.142mm)
の正方形の形状の線膨張係数6.4×10-6K-1のセラ
ミツクチツプキヤリアを基板に高さh=0.1mmの
40Pb-60Snで接合し、電源の投入と切断を1日1
回行うことにより温度変化△T=40℃を生じる使
用環境で10年間(3650回)の寿命を保証する場合
を検討する。
For example, 20mm diagonally (so 14.142mm on a side)
A square ceramic chip carrier with a linear expansion coefficient of 6.4×10 -6 K -1 is mounted on a substrate with a height h = 0.1 mm.
Bonded with 40Pb - 60Sn, power on and off once a day
We will consider a case where a lifespan of 10 years (3650 times) is guaranteed in a usage environment where the temperature change △T = 40°C occurs by repeating the test twice.

40%Pb−60%Snが3650回の寿命となるひずみ
は△γ=0.83%であり、このひずみをセラミツク
チツプキヤリアと基板の線膨張係数差△αとの関
係は近似的に次式(10)で表わされる。
The strain at which 40%Pb-60%Sn reaches a life of 3650 cycles is △γ = 0.83%, and the relationship between this strain and the linear expansion coefficient difference △α between the ceramic chip carrier and the substrate is approximately expressed by the following equation (10 ).

△γ=l・△α・△T/h (10) 式(10)より△α=1.5×10-6K-1となり、基板の線
膨張係数は4.9×10-6から7.9×10-6K-1となる。
△γ=l・△α・△T/h (10) From equation (10), △α=1.5×10 -6 K -1 , and the linear expansion coefficient of the substrate is 4.9×10 -6 to 7.9×10 -6 It becomes K -1 .

次に、本発明について実施例を示し、具体的に
説明する。
Next, the present invention will be specifically explained by showing examples.

実施例 1 臭素化ビスフエノールA型エポキシ樹脂(エポ
キシ当量480g/eq)90重量部、クレゾールノボ
ラツク型・エポキシ樹脂(エポキシ当量220g/
eq)10重量部、ジシアンジアミド4重量部、ベ
ンジルジメチルアミン0.2重量部に溶媒としてメ
チルエチルケトンとメチルセロソルブを加え、濃
度37%のワニスを作つた。
Example 1 Brominated bisphenol A type epoxy resin (epoxy equivalent: 480 g/eq) 90 parts by weight, cresol novolak type epoxy resin (epoxy equivalent: 220 g/eq)
eq) Methyl ethyl ketone and methyl cellosolve were added as solvents to 10 parts by weight, 4 parts by weight of dicyandiamide, and 0.2 parts by weight of benzyldimethylamine to prepare a varnish with a concentration of 37%.

一方、22.5テツクスのガラス繊維と21.7テツク
スのポリ―P―フエニレンテレフタルアミド繊維
を1本ずつ撚り合わせて複合糸を作り、これを製
織して線密度37本×37本/25mm幅の複合クロスを
作つた。
On the other hand, 22.5 tex glass fibers and 21.7 tex poly-P-phenylene terephthalamide fibers are twisted together one by one to make a composite yarn, and this is woven into a composite cloth with a linear density of 37 x 37 yarns/25 mm width. I made it.

上記ワニスの中にこの複合クロスを浸漬し、
160℃で5分間乾燥し、プリプレグを得た。この
プリプレグ中の樹脂分は29.5重量%(約35容量
%)であつた。
Dip this composite cloth into the above varnish,
It was dried at 160°C for 5 minutes to obtain a prepreg. The resin content in this prepreg was 29.5% by weight (approximately 35% by volume).

次に、このプリプレグ(プリプレグの線膨張係
数は5.8×10-6K-1であつた)8枚と2枚の銅箔
(厚さ35μ)を上下に置き、170℃で60分プレス
し、厚さ1.03mmの両面銅張積層板を作成した。
Next, eight sheets of this prepreg (the coefficient of linear expansion of the prepreg was 5.8×10 -6 K -1 ) and two sheets of copper foil (thickness 35μ) were placed on top of each other and pressed at 170°C for 60 minutes. A double-sided copper-clad laminate with a thickness of 1.03 mm was created.

この銅張積層板の表面銅箔を塩化第二鉄液でエ
ツチングすることにより、銅配線パターンを形成
し、両面印刷配線基板を作成した。従つて銅箔は
プリプレグ層に対し極めて薄くしかも配線パター
ンを残して除去されていることから基板の線膨張
係数は実質的にプリプレグを変わらないものとみ
なせる。この両面印刷配線基板上の電極パターン
上へはんだペーストを塗布し、このパターンへチ
ツプキヤリアを載せ、フロリナートFC70の蒸気
中で215℃まで加熱し、約16mm角のアルミナ製で
線膨張係数が6.4×10-6K-1のチツプキヤリアと両
面印刷配線基板を40%Pb―60%Snのはんだで接
続した。
A copper wiring pattern was formed by etching the surface copper foil of this copper-clad laminate with a ferric chloride solution, and a double-sided printed wiring board was produced. Therefore, since the copper foil is extremely thin relative to the prepreg layer and is removed leaving a wiring pattern, the coefficient of linear expansion of the substrate can be considered to be substantially the same as that of the prepreg. Solder paste was applied onto the electrode pattern on this double-sided printed circuit board, a chip carrier was placed on this pattern, and the chip carrier was heated to 215°C in the steam of Fluorinert FC70.It was made of alumina with a linear expansion coefficient of 6.4 x 10 approximately 16 mm square. -6 K -1 chip carrier and double-sided printed circuit board were connected using 40%Pb-60%Sn solder.

チツプキヤリアを塔載した両面印刷配線基板を
温度サイクル試験槽に入れ、125℃〜−65℃、1
サイクル/時間の温度サイクル試験を実施した。
Place the double-sided printed wiring board on which the chip carrier is mounted in a temperature cycle test chamber and heat it at 125℃ to -65℃ for 1
A cycle/hour temperature cycling test was conducted.

はんだ接続部の疲労破壊を抵抗測定と外観観察
で検出した結果200サイクルの温度サイクルの後
でも、はんだ接続部が破断せず、抵抗も殆んど変
化しなかつた。
Fatigue fractures in the soldered joints were detected by resistance measurements and external observations, and the results showed that even after 200 temperature cycles, the soldered joints did not break and the resistance hardly changed.

また、JISC6481の引きはがし試験法に準拠し
て測定したら、実装構造における層間接着性は1
Kg/cm以上であつた。
In addition, when measured according to the peel test method of JISC6481, the interlayer adhesion in the mounting structure is 1.
It was over Kg/cm.

比較例 1 実施例1と同様のワニスを用いて、ガラスクロ
スに含浸させ、プリプレグを作り、このプリプレ
グ8枚と銅箔2枚を上下に置き、両面銅張積層板
を作成し、実施例1と同様な方法で両面印刷配線
基板を作成し、チツプキヤリアとこの両面印刷配
線基板をはんだ接続した。これによれば、層間接
着性は1Kg/cm以上で良好だつたが、実施例1と
同様な疲労試験を実施したところ、40〜50サイク
ルの温度サイクルの後に、はんだ接続部が破断
し、抵抗が無限大になつた。
Comparative Example 1 Using the same varnish as in Example 1, glass cloth was impregnated to make a prepreg, and 8 sheets of this prepreg and 2 sheets of copper foil were placed one above the other to create a double-sided copper-clad laminate. A double-sided printed wiring board was created in the same manner as above, and the chip carrier and this double-sided printed wiring board were connected by soldering. According to this, the interlayer adhesion was good at 1 kg/cm or more, but when a fatigue test similar to that in Example 1 was conducted, the solder joint broke after 40 to 50 temperature cycles, and the resistance has become infinite.

比較例 2 フエノールノボラツク型エポキシ樹脂(エポキ
シ当量180g/eq)40重量部、臭素化フエノール
ボラツク型エポキシ樹脂(エポキシ当量285g/
ep)60重量部、ジシアンジアミンド6.4重量部、
ベンジルジメチルアミン0.1部にメチルエチルケ
トンとメチルセロソルブを加えて濃度37.5%のワ
ニスを作つた。このワニスをポリ―P―フエニレ
ンテレフタルアミド繊維からなるクロスに含浸さ
せ、温度160℃、塗工速度1.5n/minの条件で塗
工布を得た。
Comparative Example 2 40 parts by weight of phenol novolak epoxy resin (epoxy equivalent: 180 g/eq), brominated phenol volak epoxy resin (epoxy equivalent: 285 g/eq)
ep) 60 parts by weight, dicyandiamine 6.4 parts by weight,
A varnish with a concentration of 37.5% was made by adding methyl ethyl ketone and methyl cellosolve to 0.1 part of benzyldimethylamine. A cloth made of poly-P-phenylene terephthalamide fibers was impregnated with this varnish to obtain a coated cloth at a temperature of 160° C. and a coating speed of 1.5 n/min.

このプリプレグを10枚と35μmの厚さの銅箔を
2枚重ねて、170℃、1時間、80Kg/cm2の圧力で
プレスして厚さ0.8mmの両面銅張積層板を作成し、
実施例1と同様な方法で、両面印刷配線基板を作
成し、チツプキヤリアとこの両面印刷配線基板を
はんだ接続した。これによれば疲労試験において
は実施例1と同様に200サイクルの温度サイクル
の後でもはんだ接続部が破断しなかつたが、層間
接着力は0.7Kg/cmであつた。
Ten sheets of this prepreg and two sheets of 35 μm thick copper foil were stacked together and pressed at 170°C for 1 hour at a pressure of 80 kg/cm 2 to create a double-sided copper-clad laminate with a thickness of 0.8 mm.
A double-sided printed wiring board was prepared in the same manner as in Example 1, and the chip carrier and this double-sided printed wiring board were connected by soldering. According to this, in the fatigue test, the solder joint did not break even after 200 temperature cycles as in Example 1, but the interlayer adhesive strength was 0.7 kg/cm.

以上の実施例および比較例からわかるように、
比較例1では温度サイクルが短く、比較例2では
層間接着力が弱く、それぞれ実用性の面で致命的
な欠陥があるが、実施例では温度サイクルが200
サイクルの後でもはんだ接続部が破断せず、かつ
層間接着力も大きく、実用的に使用可能であるこ
とがわかる。
As can be seen from the above examples and comparative examples,
Comparative Example 1 has a short temperature cycle, and Comparative Example 2 has weak interlayer adhesion, both of which have fatal flaws in terms of practicality. However, in the example, the temperature cycle is 200
It can be seen that the soldered joints do not break even after cycling, and the interlayer adhesion is strong, making it usable for practical use.

以上のように本発明によれば、マトリツクスと
して使用する樹脂との親和性が良く、積層板中で
クロスを境面にして剥離が生じ難く、熱伝導率が
良く、且つレジストレーシヨンが発生し難い信頼
性が高く温度寿命サイクルのリード線レス半導体
装置の実装構造を得ることができる。
As described above, according to the present invention, it has good affinity with the resin used as a matrix, is difficult to peel off at the interface of the cloth in the laminate, has good thermal conductivity, and does not cause registration. It is possible to obtain a lead wireless semiconductor device mounting structure that has high reliability and a temperature life cycle that is difficult to achieve.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は従来のリード線レス半導
体装置の実装構造の構成を示すもので、第1図a
はフリツプチツプのアルミナ基板への接続を示す
断面図、第1図bは第1図aの上面図、第2図a
はチツプキヤリアの印刷配線板への接続を示す断
面図、第2図bは第2図aの上面図、第3図は第
2図に示す実装構造におけるろう材に生ずるひず
みを説明するための図、第4図は芳香族系のポリ
アミド繊維の体積含有率と基板の線膨張係数との
関係を示す図、第5図および第6図は本発明のリ
ードレス半導体装置の実装構造の一実施例を示す
もので、第5図aはチツプキヤリアの印刷配線板
への接続を示す断面図、第5図bは第5図aの上
面図、第6図aはシリコン素子の基板への接続を
示す断面図、第6図bは第6図aの上面図、第7
図は複合繊維の体積含有率と積層板の線膨張係数
との関係を示す特性図、第8図は複合繊維におけ
るポリ―P―フエニレンテレフタルアミド繊維の
体積含有率と積層板の線膨張係数との関係を示す
特性図である。 8……積層板、9……銅配線、10……スルー
ホール、11……チツプキヤリア、12……はん
だ、15……積層板、16……シリコン素子、1
7……はんだ。
Figures 1 and 2 show the configuration of the mounting structure of a conventional lead wireless semiconductor device.
is a cross-sectional view showing the connection of a flip chip to an alumina substrate, FIG. 1b is a top view of FIG. 1a, and FIG. 2a is a top view of FIG.
2 is a cross-sectional view showing the connection of the chip carrier to the printed wiring board, FIG. 2b is a top view of FIG. 2a, and FIG. , FIG. 4 is a diagram showing the relationship between the volume content of aromatic polyamide fibers and the linear expansion coefficient of the substrate, and FIGS. 5 and 6 are examples of the mounting structure of the leadless semiconductor device of the present invention. 5a is a sectional view showing the connection of the chip carrier to the printed wiring board, FIG. 5b is a top view of FIG. 5a, and FIG. 6a is the connection of the silicon element to the substrate. A cross-sectional view, Fig. 6b is a top view of Fig. 6a, Fig. 7
The figure is a characteristic diagram showing the relationship between the volume content of the composite fiber and the linear expansion coefficient of the laminate. Figure 8 is the volume content of poly-P-phenylene terephthalamide fiber in the composite fiber and the linear expansion coefficient of the laminate. FIG. 8... Laminate board, 9... Copper wiring, 10... Through hole, 11... Chip carrier, 12... Solder, 15... Laminate board, 16... Silicon element, 1
7...Solder.

Claims (1)

【特許請求の範囲】[Claims] 1 複数枚数のプリプレグと複数の金属配線層と
を加熱加圧成形してなる印刷配線基板上にリード
線レス半導体装置を搭載したリード線レス半導体
装置の実装構造において、前記プリプレグは複数
クロスに熱硬化性樹脂を含浸せしめたものであ
り、該複合クロスは芳香族系のポリアミド繊維と
ガラス繊維とを混合撚糸した複合糸の製織物であ
り、前記リード線レス半導体装置の線膨張係数に
前記印刷配線基板の線膨張係数を合わせるように
したことを特徴とするリード線レス半導体の実装
構造。
1. In a lead wireless semiconductor device mounting structure in which a lead wireless semiconductor device is mounted on a printed wiring board formed by heat-pressing molding of a plurality of prepregs and a plurality of metal wiring layers, the prepreg is heated in a plurality of crosses. The composite cloth is impregnated with a curable resin, and the composite cloth is a woven fabric of composite yarn made by mixing and twisting aromatic polyamide fibers and glass fibers, and the linear expansion coefficient of the lead wireless semiconductor device has the aforementioned printing. A lead wireless semiconductor mounting structure characterized by matching the linear expansion coefficient of the wiring board.
JP14946480A 1980-10-27 1980-10-27 Leadless semiconductor device mounting structure Granted JPS5773990A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14946480A JPS5773990A (en) 1980-10-27 1980-10-27 Leadless semiconductor device mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14946480A JPS5773990A (en) 1980-10-27 1980-10-27 Leadless semiconductor device mounting structure

Publications (2)

Publication Number Publication Date
JPS5773990A JPS5773990A (en) 1982-05-08
JPH022315B2 true JPH022315B2 (en) 1990-01-17

Family

ID=15475696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14946480A Granted JPS5773990A (en) 1980-10-27 1980-10-27 Leadless semiconductor device mounting structure

Country Status (1)

Country Link
JP (1) JPS5773990A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS533487A (en) * 1976-06-30 1978-01-13 Matsushita Electric Works Ltd Laminates
JPS5530974A (en) * 1978-08-29 1980-03-05 Toray Industries Fabric construction for composite material
JPS5553497A (en) * 1978-10-14 1980-04-18 Matsushita Electric Works Ltd Method of manufacturing multilayer printed circuit board

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4896258U (en) * 1972-02-18 1973-11-15

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS533487A (en) * 1976-06-30 1978-01-13 Matsushita Electric Works Ltd Laminates
JPS5530974A (en) * 1978-08-29 1980-03-05 Toray Industries Fabric construction for composite material
JPS5553497A (en) * 1978-10-14 1980-04-18 Matsushita Electric Works Ltd Method of manufacturing multilayer printed circuit board

Also Published As

Publication number Publication date
JPS5773990A (en) 1982-05-08

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