JPH0223008Y2 - - Google Patents

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Publication number
JPH0223008Y2
JPH0223008Y2 JP1982169255U JP16925582U JPH0223008Y2 JP H0223008 Y2 JPH0223008 Y2 JP H0223008Y2 JP 1982169255 U JP1982169255 U JP 1982169255U JP 16925582 U JP16925582 U JP 16925582U JP H0223008 Y2 JPH0223008 Y2 JP H0223008Y2
Authority
JP
Japan
Prior art keywords
wiring
board
circuit
electronic circuit
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982169255U
Other languages
Japanese (ja)
Other versions
JPS5974751U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16925582U priority Critical patent/JPS5974751U/en
Publication of JPS5974751U publication Critical patent/JPS5974751U/en
Application granted granted Critical
Publication of JPH0223008Y2 publication Critical patent/JPH0223008Y2/ja
Granted legal-status Critical Current

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  • Combinations Of Printed Boards (AREA)

Description

【考案の詳細な説明】 本考案は複合電子回路に関し、特に分割基板に
よる増幅器等の複合電子回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite electronic circuit, and more particularly to a composite electronic circuit such as an amplifier using a split substrate.

電子回路は益々集積化されつつある。集積化に
は種々の方法があり、所定目的の電子回路を一定
の設計原理の下に統一的に集積化すること、或い
はコンデンサ、コイル、トランジスタなどの部分
的な集積化すること、など色々である。前者は回
路の集積化が高いけれども個別生産となるので汎
用性はない。また後者では集積化は不十分であ
る。
Electronic circuits are becoming increasingly integrated. There are various methods of integration, such as uniformly integrating electronic circuits for a given purpose based on a certain design principle, or partially integrating capacitors, coils, transistors, etc. be. Although the former has a high level of circuit integration, it is not versatile because it is produced individually. Furthermore, in the latter case, integration is insufficient.

本考案は集積度の十分に高い、汎用性の高い、
組立ての容易は複合電子回路を提供することを目
的とする。本考案は、複合電子回路の多くが規格
化した回路部分から構成されうることに注目し、
複合電子回路の全部を機能別に分割し、それらを
それぞれ所定の集積基板の内部及び(又は)表面
に能動又は受動素子及び配線パターンを施したも
のとして構成し、またこれらの基板の引出部は基
板周辺部に集めて膜状の外部端子とし、そしてこ
のように構成した部分集積回路をプリント配線基
板(以下マザーボードと言う)に塔載して部分集
積回路の外部端子とマザーボードの配線との間に
半田接続を行う。必要ならばこのマザーボードは
さらに大型プリント配線基板に塔載して三重集積
型にすることも可能である。この最後の場合は複
雑な回路の実現に効果を発揮する。
This invention has a sufficiently high degree of integration and is highly versatile.
Ease of assembly is aimed at providing complex electronic circuits. The present invention focuses on the fact that many complex electronic circuits can be composed of standardized circuit parts,
All of the composite electronic circuits are divided according to function, and each of them is configured as a predetermined integrated board with active or passive elements and wiring patterns applied inside and/or on the surface, and the lead-out portions of these boards are They are gathered at the periphery to form a film-like external terminal, and the partially integrated circuit configured in this way is mounted on a printed wiring board (hereinafter referred to as a motherboard) and connected between the external terminals of the partially integrated circuit and the wiring of the motherboard. Make solder connections. If necessary, this motherboard can be further mounted on a larger printed wiring board to form a triple integrated type. This last case is effective in realizing complex circuits.

このように集積化すると、汎用回路部分が多量
生産化でき、又少量生産を要する部分が少なくて
済むので経済性が増し、部分回路の規格化及び外
形の統一化により複合電子回路の組立てが容易に
なるなどの利益が提供できる。
By integrating in this way, general-purpose circuit parts can be mass-produced, fewer parts need to be produced in small quantities, which increases economic efficiency, and it is easier to assemble complex electronic circuits by standardizing partial circuits and unifying external shapes. It can provide benefits such as:

以下、図面を参照して本考案の複合電子回路を
詳しく説明する。
Hereinafter, the composite electronic circuit of the present invention will be described in detail with reference to the drawings.

第1図は本考案の複合電子回路を示し、この回
路はセラミツク、プラスチツク等で製作された平
板の表面にプリント配線11を施して成るマザー
ボード10と、その表面に塔載された機能別の部
分集積回路1,2,3,4,5,6,7,8とか
ら構成されている。部分集積回路1〜8は、それ
ぞれ外周辺に引出された薄膜状の接続端子を有
し、マザーボード上の配線との間に所定の半田接
続を有する。部分集積回路は1がUHF高周波増
幅器セル、2は段間接続セル、3はAFCセル、
4は局部発振セル、5は入力フイルターセル、6
はRF増幅セル、7は選択回路セル、及び8はIF
増幅器セルである。
FIG. 1 shows a composite electronic circuit of the present invention, which consists of a motherboard 10 consisting of a flat plate made of ceramic, plastic, etc. with printed wiring 11 on the surface, and functional parts mounted on the surface of the motherboard 10. It is composed of integrated circuits 1, 2, 3, 4, 5, 6, 7, and 8. Each of the partially integrated circuits 1 to 8 has a thin film-like connection terminal drawn out to the outer periphery, and has a predetermined solder connection with the wiring on the motherboard. As for the partially integrated circuit, 1 is a UHF high frequency amplifier cell, 2 is an interstage connection cell, 3 is an AFC cell,
4 is a local oscillation cell, 5 is an input filter cell, 6
is the RF amplification cell, 7 is the selection circuit cell, and 8 is the IF
It is an amplifier cell.

部分集積回路1〜8の具体例の1つを第2図に
示す。第2図は1つの機能回路を含む部分集積回
路がチツプ状積層部品として構成されており、こ
のものは、絶縁体または誘電体20の内部に、コ
ンデンサ電極21,22,23等、配線導体2
4、マスク用絶縁体層25、他の配線や回路要素
を迂回するジヤンパー導体26、引出導体27な
どが積層された焼結体より構成され、また導電ペ
ーストの塗布及び低温焼付けで形成された半田適
性の良い外部端子28が設けられている。また表
面にはトランジスタ29などが塔載され配線30
に半田接続されている。さらに、抵抗膜やダイオ
ード、或いはインダクタなどを塔載することがで
きる。例えば第3図のような回路を1つのチツプ
状部品として構成することができる。第3図は増
幅回路である。周辺に形成される外部電極28は
半田によりマザーボード(第1図)へ塔載固定さ
れる。
One specific example of partially integrated circuits 1 to 8 is shown in FIG. In FIG. 2, a partially integrated circuit including one functional circuit is constructed as a chip-like laminated component, which includes capacitor electrodes 21, 22, 23, etc.
4. It is composed of a sintered body in which a mask insulator layer 25, a jumper conductor 26 for bypassing other wiring and circuit elements, a lead-out conductor 27, etc. are laminated, and solder is formed by applying conductive paste and baking at low temperature. A suitable external terminal 28 is provided. In addition, transistors 29 and the like are mounted on the surface, and wiring 30
is connected by solder. Furthermore, a resistive film, a diode, an inductor, etc. can be mounted. For example, a circuit as shown in FIG. 3 can be constructed as a single chip-like component. FIG. 3 shows an amplifier circuit. The external electrodes 28 formed around the periphery are mounted and fixed to the motherboard (FIG. 1) by soldering.

以上のように構成したから、前述した種々の利
益が得られ、斯界に資するところが大きい。
With the configuration as described above, the various benefits mentioned above can be obtained, and it will greatly contribute to this field.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の複合電子回路の平面図、第2
図は部分電子回路の一部を破断して示した拡大斜
視図である。第3図は本考案が適用される回路例
である。図中主な部分は次の通りである。 1,2,3,4,5,6,7,8:機能別部分
電子回路、10:マザーボード、11:プリント
配線、12:内部配線。
Figure 1 is a plan view of the composite electronic circuit of the present invention;
The figure is an enlarged perspective view showing a partially cut away partial electronic circuit. FIG. 3 shows an example of a circuit to which the present invention is applied. The main parts in the figure are as follows. 1, 2, 3, 4, 5, 6, 7, 8: Functional partial electronic circuit, 10: Motherboard, 11: Printed wiring, 12: Internal wiring.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1つの最終機能を有する電子回路を機能別部品
に分割して、各機能別部品毎に、1つの積層基板
に搭載して構成し、しかも各機能別部品に必要な
内部配線の交差部は絶縁体を介して同機能別部品
内で行ない、該積層基板の外周部に接続端子を薄
層状に形成し、前記積層基板をプリント配線基板
の所定位置に搭載して構成し、前記接続端子とプ
リント配線基板に設けた前記積層基板間の接続用
配線とを半田接続してなる複合電子回路。
An electronic circuit with one final function is divided into functional parts, and each functional part is mounted on a single laminated board, and the intersections of internal wiring required for each functional part are insulated. The connection terminals are formed in a thin layer on the outer periphery of the multilayer board, and the multilayer board is mounted at a predetermined position on a printed wiring board, and the connection terminals and the printed A composite electronic circuit formed by soldering a wiring board and connecting wiring between the laminated boards provided on a wiring board.
JP16925582U 1982-11-10 1982-11-10 complex electronic circuit Granted JPS5974751U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16925582U JPS5974751U (en) 1982-11-10 1982-11-10 complex electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16925582U JPS5974751U (en) 1982-11-10 1982-11-10 complex electronic circuit

Publications (2)

Publication Number Publication Date
JPS5974751U JPS5974751U (en) 1984-05-21
JPH0223008Y2 true JPH0223008Y2 (en) 1990-06-21

Family

ID=30369805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16925582U Granted JPS5974751U (en) 1982-11-10 1982-11-10 complex electronic circuit

Country Status (1)

Country Link
JP (1) JPS5974751U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5022257A (en) * 1973-07-02 1975-03-10
JPS5687395A (en) * 1979-12-18 1981-07-15 Fujitsu Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5022257A (en) * 1973-07-02 1975-03-10
JPS5687395A (en) * 1979-12-18 1981-07-15 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS5974751U (en) 1984-05-21

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