JPH0222845A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0222845A JPH0222845A JP17176888A JP17176888A JPH0222845A JP H0222845 A JPH0222845 A JP H0222845A JP 17176888 A JP17176888 A JP 17176888A JP 17176888 A JP17176888 A JP 17176888A JP H0222845 A JPH0222845 A JP H0222845A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- cracks
- coated insulating
- caused
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000009499 grossing Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 9
- 238000010304 firing Methods 0.000 abstract description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000002904 solvent Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 7
- 238000000576 coating method Methods 0.000 abstract 7
- 230000008602 contraction Effects 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
この発明は、半導体装置の製造方法、特に塗布絶縁膜の
形成工程を含む半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of forming a coated insulating film.
（従来の技術）
従来、集積回路等の製造工程において配線層間の平坦化
等を目的として塗布絶縁膜を形成する方法が広く用いら
れている。一般に、前記塗布絶縁膜は膜質が良好でない
ため前記膜質改善のために焼成工程を行なう、しかしな
がら前記焼成工程を行うと塗布絶縁膜の体積収縮に伴な
ういくつかの問題が生じる。この問題について以下図面
を用いて説明する。第２図（ａ）〜（Ｃ）は、配線層間
絶縁膜を平坦化する工程断面図である。(Prior Art) Conventionally, in the manufacturing process of integrated circuits and the like, a method of forming a coated insulating film for the purpose of flattening between wiring layers, etc. has been widely used. Generally, the coated insulating film has poor film quality, so a baking process is performed to improve the film quality.However, when the baking process is performed, several problems arise due to volumetric shrinkage of the coated insulating film. This problem will be explained below using the drawings. FIGS. 2A to 2C are cross-sectional views of the process of planarizing the wiring interlayer insulating film.
第２図（ａ）は、シリコン基板（２１）に素子（図示せ
ず）を形成し、更に、前記基板（２１）上にアルミニウ
ム配線（２２）を形成し、さらにその上に層間絶縁膜と
して気相成長法（以下ＣＶＤと呼ぶ。）により全面に二
酸硅素膜（２３）を堆積したものである。In FIG. 2(a), an element (not shown) is formed on a silicon substrate (21), an aluminum wiring (22) is further formed on the substrate (21), and an interlayer insulating film is formed on the aluminum wiring (22). A silicon dioxide film (23) is deposited on the entire surface by a vapor phase growth method (hereinafter referred to as CVD).
次に、前記層間絶縁膜（２３）の平坦化を目的として塗
布絶縁膜、例えばスピンオンガラス（例えば。Next, for the purpose of planarizing the interlayer insulating film (23), a coated insulating film, for example spin-on glass (for example) is applied.
二酸化硅素５％をアルコール溶媒中に溶解したもの、以
下ＳＯＧと呼ぶ、）を塗布し、ＳＯＧ膜（２４）を形成
する（第２図（ｂ）） 。A solution of 5% silicon dioxide dissolved in an alcohol solvent (hereinafter referred to as SOG) is applied to form an SOG film (24) (FIG. 2(b)).
次に、前記ＳＯＧ膜（２４）の膜質改善のための焼成を
例えば、４５０℃の窒素雰囲気中での熱処理によって行
う、ところが、この工程で、以下のような問題が発生す
る。Next, the SOG film (24) is fired to improve its film quality, for example, by heat treatment at 450° C. in a nitrogen atmosphere. However, the following problem occurs in this step.
すなわち、■焼成に伴う堆積収縮により、Ｓ。That is, ① S due to deposition shrinkage accompanying firing.
Ｇ膜（２４）に亀裂（２５）を生じる。A crack (25) is generated in the G film (24).
■焼成に伴う堆積収縮により、５ＯＧＩＦＪ（２４）に
引張応力が生じ、二酸化硅素膜（２３）に亀裂（２６）
を生じる。■ Tensile stress occurs in 5OGIFJ (24) due to deposition shrinkage due to firing, and cracks (26) occur in the silicon dioxide film (23).
occurs.
前記ＳＯＧ膜（２４）ヘノ亀裂（２５）、ＳＯＧ膜（２
４）が、薄い場合に多く発生し、一方、前記二酸化硅素
膜（２３）への亀裂（２６）は、ＳＯＧ膜（２４）が、
厚い場合に多く発生する（第２図（Ｃ））。The SOG film (24), the crack (25), the SOG film (2)
4) is more likely to occur when the silicon dioxide film (23) is thin, while cracks (26) to the silicon dioxide film (23) occur when the SOG film (24) is thin.
This often occurs when the thickness is thick (Fig. 2 (C)).
これらの亀裂（２５）、 （２６）は１本来の目的であ
る平坦性を損ない、配線（２２）や、後に形成する上層
配線の信頼性を著しく劣化させる。このように。These cracks (25) and (26) impair the flatness, which is the original purpose of 1, and significantly deteriorate the reliability of the wiring (22) and the upper layer wiring that will be formed later. in this way.
層間平坦化において塗布絶縁膜を形成した後その焼成を
行うと、塗布絶縁膜自身や、配線に予め堆積した層間絶
縁膜に亀裂を発生する危険があり、この亀裂は、集積回
路の製造歩留まりや信頼性を著しく劣化させるため大き
な問題となっている。If a coated insulating film is formed and then baked in interlayer planarization, there is a risk of cracks occurring in the coated insulating film itself or in the interlayer insulating film pre-deposited on the wiring, and these cracks will affect the manufacturing yield of integrated circuits. This is a major problem because it significantly degrades reliability.
（発明が解決しようとする課題）
本発明は、このように層間平坦に塗布絶縁膜を形成した
後、膜質改善のための焼成を行うと、塗布絶縁膜自身や
、配線に予め堆積した層間絶縁膜に亀裂発生する危険が
あり、この亀裂は、集積回路の製造歩留まりや信頼性を
著しく劣化させるという従来の問題点を解決するもので
塗布絶縁膜の形成工程を含む半導体装置の製造方法を提
供するものである。゛
〔発明の構成〕
（課題を解決するための手段）
この発明は、塗布絶縁膜を形成した後、その焼成工程で
の塗布絶縁膜自身あるいは前記焼成工程に伴なう層間絶
縁膜への亀裂の発生を実質的に抑えることを目的とし、
−旦第一の塗布絶縁膜を薄く形成し、十分な焼成を行な
うと同時に塗布絶縁膜に亀裂を発生せしめ、次に第二の
塗布絶縁膜を形成して前記亀裂を平坦化あるいは平滑化
するようにしたものである。(Problems to be Solved by the Invention) The present invention provides that, after forming a coated insulating film with flat interlayers as described above, when baking is performed to improve the film quality, the coated insulating film itself and the interlayer insulation previously deposited on the wiring are removed. This method solves the conventional problem that there is a risk of cracks occurring in the film, which significantly deteriorates the manufacturing yield and reliability of integrated circuits.We provide a method for manufacturing semiconductor devices that includes a process of forming a coated insulating film. It is something to do.゛ [Structure of the Invention] (Means for Solving the Problems) This invention solves the problem of cracks in the applied insulating film itself or in the interlayer insulating film during the baking process after forming the applied insulating film. The purpose is to substantially suppress the occurrence of
- First, a first coated insulating film is formed thinly, and at the same time cracks are generated in the coated insulating film by sufficient baking, and then a second coated insulating film is formed to flatten or smooth the cracks. This is how it was done.
（作 用）
本発明によれば、第一の塗布絶縁膜から予め堆積した下
地の層間絶縁膜に作用する引張り応力は、前記第一の塗
布絶縁膜に発生した亀裂により大幅に緩和され、従って
前記層間絶縁膜に発生する亀裂を抑制できる。また、第
一の塗布絶縁膜に発生した亀裂は、第二の塗布絶縁膜に
よって平坦化。(Function) According to the present invention, the tensile stress acting on the underlying interlayer insulating film deposited in advance from the first coated insulating film is significantly alleviated by the cracks generated in the first coated insulating film. Cracks occurring in the interlayer insulating film can be suppressed. In addition, cracks that occur in the first coated insulating film are flattened by the second coated insulating film.
平滑化されるので基板表面は亀裂のない平坦形状を得る
ことができる。Since the surface of the substrate is smoothed, a flat shape without cracks can be obtained.
（実施例）
本発明による一実施例を配線層間絶縁膜の平坦化を例と
して挙げ１図面を用いて詳細に説明する。(Embodiment) An embodiment of the present invention will be described in detail with reference to one drawing, taking planarization of a wiring interlayer insulating film as an example.
第１図は１本発明による一実施例を示す工程断面図であ
る。第１図（ａ）は、シリコン基板（１１）に素子（図
示せず）を形成し更に、前記基板（１１）上に素子に接
続されるパターニングされたアルミニウム配線（１２）
を形成し、その上に層間絶縁膜としてＣＶＤ法により二
酸化硅素ＩＰｉ （１３）を全面に堆積したものである
。FIG. 1 is a process sectional view showing an embodiment according to the present invention. FIG. 1(a) shows an element (not shown) formed on a silicon substrate (11), and a patterned aluminum wiring (12) connected to the element on the substrate (11).
is formed, and silicon dioxide IPi (13) is deposited on the entire surface as an interlayer insulating film by the CVD method.
このような基板表面に第１図（ｂ）に示すように第一の
塗布絶縁膜１例えば二酸化硅素をアルコール溶媒中に例
えば５％溶解したＳＯＧ膜（１４）を薄く塗布する。こ
の５ＯＧＷＡ（１４）の形成は前記パタニングされた配
線（１２）上に堆積された層間絶縁膜の溝部の全部又は
一部に埋め込むように形成する。As shown in FIG. 1(b), a first coated insulating film 1, for example, an SOG film (14) prepared by dissolving, for example, 5% silicon dioxide in an alcohol solvent, is thinly applied to the surface of such a substrate. The 5OGWA (14) is formed so as to be buried in all or part of the groove of the interlayer insulating film deposited on the patterned wiring (12).
次に、前記ＳＯＧ膜（１４）の膜質改善のための焼成を
、例えば４５０℃で１Ｏ−２Ｔｏｒｒの真空中で熱処理
によって行う。この熱処理により前記ＳＯＧ膜（１４）
に焼成に伴う堆積収縮が生じ、ＳＯＧ膜（１４）には、
第１図（ｃ）のように亀裂（１５）が生じる。前記亀裂
（１５）は、焼成の温度を高くしたり、プラズマ中での
ガス処理を施したり、あるいは、大気圧を下回る圧力で
真空度を上げることにより発生し易くせしめることが可
能である。Next, the SOG film (14) is fired to improve its film quality by heat treatment, for example, at 450° C. in a vacuum of 1 O −2 Torr. Through this heat treatment, the SOG film (14)
Deposition shrinkage occurs due to firing, and the SOG film (14) has the following properties:
A crack (15) is generated as shown in FIG. 1(c). The cracks (15) can be made more likely to occur by increasing the firing temperature, performing gas treatment in plasma, or increasing the degree of vacuum at a pressure below atmospheric pressure.
その後、第１図（ｄ）に示すように第二の塗布絶縁膜と
してＳＯＧ膜（１６）を全面に塗布し、前記亀裂（１５
）を被覆するように表面の平坦化を行う。Thereafter, as shown in FIG. 1(d), an SOG film (16) is applied to the entire surface as a second applied insulating film to fill the cracks (15).
) The surface is flattened to cover the surface.
上記工程により、第一の塗布絶縁膜（１４）から堆積し
た層間絶縁膜（１３）に作用する引張り応力は、前記塗
布絶縁膜（１４）に発生した亀裂（１５）により大幅に
緩和され、従来層間絶縁ＩＦＪ（１３）に発生する亀裂
を抑制することができる。また、第一の塗布絶縁（１４
）に発生した亀裂（１５）を第二の塗布絶縁膜（１６）
によって平坦化するので、最終的には亀裂のない層間平
坦形状が達成でき、集積回路の製造歩留まりや信頼性を
著しく向上することが可能となる。Through the above process, the tensile stress acting on the interlayer insulating film (13) deposited from the first coated insulating film (14) is significantly alleviated by the cracks (15) generated in the coated insulating film (14), and Cracks occurring in the interlayer insulation IFJ (13) can be suppressed. In addition, the first coated insulation (14
) The crack (15) that occurred in the second coated insulating film (16)
As a result, a flat interlayer shape without cracks can be finally achieved, making it possible to significantly improve the manufacturing yield and reliability of integrated circuits.
尚、本実施例は、アルミニウム配線層間絶縁膜平坦化工
程を例に説明したが、実際にはアルミニウム配線層間絶
縁膜平坦化工程に限定されるものではなく、他の材料配
線や、半導体基板自身に設けられた段差の平坦化工程で
も同様の効果が得られることは言までもない。Although this embodiment has been described using the aluminum wiring interlayer insulation film planarization process as an example, the process is not actually limited to the aluminum wiring interlayer insulation film flattening process, and may be applied to other material wiring or the semiconductor substrate itself. It goes without saying that a similar effect can be obtained in the step of flattening the steps provided in the substrate.
本発明によれば亀裂を生じることなく平坦性を達成し得
る塗布絶縁膜を形成することが可能である。According to the present invention, it is possible to form a coated insulating film that can achieve flatness without causing cracks.
第１図は、本発明の一実施例を示す工程断面図。
第２図は、従来の工程を示す断面図である。
１１・・・シリコン基板 １２・・・配線１３・・
・二酸化硅素膜 １４・・・第１の塗布絶縁膜１５
・・・亀裂 １６・・・第２の塗布絶縁膜
代理人 弁理士 則 近 憲 佑
同 松山光之
第１図
第２図FIG. 1 is a process sectional view showing an embodiment of the present invention. FIG. 2 is a sectional view showing a conventional process. 11... Silicon substrate 12... Wiring 13...
・Silicon dioxide film 14...first coated insulating film 15
...Crack 16...Second coated insulating film agent Patent attorney Noriyoshi Chika Yudo Mitsuyuki Matsuyama Figure 1 Figure 2
Claims (3)
程を含む半導体装置の製造方法において、第一の塗布絶
縁膜を形成する工程と、前記第一の塗布絶縁膜に亀裂を
発生せしめる工程と、前記第一の塗布絶縁膜上に第二の
塗布絶縁膜を形成し、前記亀裂の生じた第一の塗布絶縁
膜表面を平坦化若しくは平滑化する工程とを含むことを
特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device including a step of forming a coated insulating film on one main surface of a semiconductor substrate, cracks occur in the step of forming a first coated insulating film and the first coated insulating film. and a step of forming a second coated insulating film on the first coated insulating film and flattening or smoothing the cracked surface of the first coated insulating film. A method for manufacturing a semiconductor device.
る工程は、前記半導体基板の一主面に予め形成された段
差の平坦若しくは平滑化を行うものであることを特徴と
する請求項１記載の半導体装置の製造方法。(2) A claim characterized in that the step of forming a coated insulating film on one main surface of the semiconductor substrate flattens or smoothes a step formed in advance on one main surface of the semiconductor substrate. Item 1. A method for manufacturing a semiconductor device according to item 1.
は、熱処理、プラズマガス処理、あるいは大気圧を下回
る圧力下での処理により行なうことを特徴とする請求項
１記載の半導体装置の製造方法。(3) Manufacturing the semiconductor device according to claim 1, wherein the step of generating cracks in the first coated insulating film is performed by heat treatment, plasma gas treatment, or treatment under pressure below atmospheric pressure. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17176888A JPH0222845A (en) | 1988-07-12 | 1988-07-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17176888A JPH0222845A (en) | 1988-07-12 | 1988-07-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0222845A true JPH0222845A (en) | 1990-01-25 |
Family
ID=15929319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17176888A Pending JPH0222845A (en) | 1988-07-12 | 1988-07-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0222845A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018088487A (en) * | 2016-11-29 | 2018-06-07 | キヤノン株式会社 | Semiconductor device and method of manufacturing the same |
-
1988
- 1988-07-12 JP JP17176888A patent/JPH0222845A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018088487A (en) * | 2016-11-29 | 2018-06-07 | キヤノン株式会社 | Semiconductor device and method of manufacturing the same |
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