JPS61265824A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61265824A
JPS61265824A JP60108611A JP10861185A JPS61265824A JP S61265824 A JPS61265824 A JP S61265824A JP 60108611 A JP60108611 A JP 60108611A JP 10861185 A JP10861185 A JP 10861185A JP S61265824 A JPS61265824 A JP S61265824A
Authority
JP
Japan
Prior art keywords
silicon oxide
oxide film
semiconductor substrate
deposited
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60108611A
Other languages
Japanese (ja)
Inventor
Kichiji Ogawa
吉司 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60108611A priority Critical patent/JPS61265824A/en
Publication of JPS61265824A publication Critical patent/JPS61265824A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Abstract

PURPOSE:To prevent the yield of cracks in the succeeding processes and to improve the reliability of a semiconductor substrate, by alleviating the internal stress of an insulating film by a specified method. CONSTITUTION:On the back surface of a semiconductor substrate, on the upper surface of which an electric wiring and the like are formed, a silicon oxide film 2 is deposited by a vapor deposition method, A semiconductor substrate 1 is mounted on a susceptor 3 kept at 450 deg.C. The semiconductor substrate 1 is curved in a convex shape. SiH4 gas 4 and O2 gas 5 are supplied on the surface of the substrate. Thus a silicon oxide film 6 is deposited as an interlayer insulating film. A resist 7 is applied on the silicon oxide film 6. After burning and solidifying, the silicon oxide film 2 at the back surface is removed. Then the semiconductor substrate 1 tends to return to the original shape by an elastic force. Compression stress is yielded with respect to the silicon oxide film 6, and the internal stress in the silicon oxide film 6 is alleviated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に亀裂(クラ
ック)の発生しない絶縁膜の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an insulating film without generating cracks.

〔従来の技術〕[Conventional technology]

半導体装置の絶縁膜として通常、シリコン酸化膜あるい
はケイ酸ガラス膜(PSG膜)等が使用されておシ、こ
れらの膜は一般的に常圧気相成長法にて形成されている
A silicon oxide film, a silicate glass film (PSG film), or the like is usually used as an insulating film in a semiconductor device, and these films are generally formed by atmospheric vapor phase growth.

従来、常圧気相成長法では適当な温度に保持さと れた基板支持金(サセプター]上に牛導体基板装置き、
反応ガスを該半導体基板上に供給することにより、半導
体基板の表面にシリコン酸化膜るるいはP2O膜等が堆
積していた。
Conventionally, in the normal pressure vapor phase growth method, a conductor substrate device is placed on a substrate support (susceptor) maintained at an appropriate temperature.
By supplying a reactive gas onto the semiconductor substrate, a silicon oxide film, a P2O film, or the like was deposited on the surface of the semiconductor substrate.

C発明が解決しようとする問題点〕 上述した従来法で堆積されたシリコン酸化膜あるいはP
SG膜等は膜内部に引張り応力が発生し、その後の工程
において熱的おるいは機械的帰因によりクラックが発生
する。特に絶縁性あるいはバッジベージ冒ン性等を高め
るためにシリコン酸化膜あるいはPSG膜等の膜厚を厚
くするとクラックの発生率が、ますます高くなシ、クラ
ックによる電気配線間の短絡やクラックからの水分やア
ルカリイオンなどの不純物の侵入によるデバイス特性の
悪化など半導体装置の信頼性の低下を招くという重大な
欠点があった。またシリコン酸化膜あるいはPSG膜等
の膜厚を薄くするとクラックの発生率は減少するが、電
気配線間の絶縁性や不純物などの侵入に対するパッシベ
ーション性が低下し、やはり信頼性上の低下を招くこと
になる。
Problems to be solved by the invention C] Silicon oxide film or P deposited by the above-mentioned conventional method
Tensile stress is generated inside the SG film and the like, and cracks occur in subsequent steps due to thermal or mechanical factors. In particular, when the thickness of silicon oxide film or PSG film is increased to improve insulation properties or badge-base susceptibility, etc., the incidence of cracks increases even more. This has had serious drawbacks, such as deterioration of device characteristics due to the intrusion of impurities such as alkali ions and alkali ions, resulting in decreased reliability of semiconductor devices. Furthermore, if the thickness of the silicon oxide film or PSG film is made thinner, the incidence of cracks will decrease, but the insulation between electrical wiring and the passivation property against the intrusion of impurities will decrease, which will also lead to a decrease in reliability. become.

本発明の目的は、このような欠点を除去し、信頼性の高
い絶縁膜の製造方法を提供することにるる。
An object of the present invention is to eliminate such drawbacks and provide a highly reliable method for manufacturing an insulating film.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、半導体基板の一主面上に気相成長法により絶
縁膜を堆積する工程において、該半導体基板の他主面上
に気相成長法によりシリコン酸化膜を堆積しておき、次
に該半導体基板一主面上に所望の絶縁膜を堆積した後、
該他主面上に堆積された該シリコン酸化膜を除去するこ
とを特徴とする。
In the process of depositing an insulating film on one principal surface of a semiconductor substrate by vapor phase epitaxy, the present invention deposits a silicon oxide film on the other principal surface of the semiconductor substrate by vapor phase epitaxy, and then After depositing a desired insulating film on one main surface of the semiconductor substrate,
The method is characterized in that the silicon oxide film deposited on the other main surface is removed.

本発明を用いれば、半導体基板の他主面上に気相成長法
により堆積されたシリコン酸化膜の内部応力により半導
体基板の一生面側が凸状に曲げられる。そしてこの凸状
に曲げられた半導体基板の一主面上に気相成長法によシ
堆積された絶縁膜は、他主面上に堆積されたシリコン酸
化膜を除去することにより、半導体基板の弾性力により
半導体基板から圧縮応力を受け、その後の工程において
熱的あるいは機械的作用によるクラックの発生率が減少
する。
According to the present invention, the surface side of the semiconductor substrate is bent into a convex shape due to the internal stress of the silicon oxide film deposited on the other principal surface of the semiconductor substrate by vapor phase growth. The insulating film deposited by vapor phase epitaxy on one principal surface of the convexly bent semiconductor substrate is removed by removing the silicon oxide film deposited on the other principal surface. Compressive stress is received from the semiconductor substrate due to the elastic force, reducing the incidence of cracks caused by thermal or mechanical effects in subsequent steps.

〔実施例〕〔Example〕

次に本発明の実施例について説明する。第1図ないし第
3図は本発明を半導体装置の層間絶縁膜の製造方法に適
用した例である。
Next, examples of the present invention will be described. 1 to 3 show examples in which the present invention is applied to a method of manufacturing an interlayer insulating film of a semiconductor device.

先ず表面に電気配線等が形成された半導体基板lの裏面
に気相成長法にてシリコン酸化膜2t−1μm堆積し、
次に第1図に示したように、450℃に保たれたサセプ
ター3上に半導体基板1を置き、半導体基板lの表面に
SiH4ガス4と02 ガス5を供給することによυ層
間絶縁膜としてシリコン酸化膜6を1μm堆積する。こ
こで半導体基板1の裏面上に堆積されたシリコン酸化膜
2は450″Cの温度で4X10  dyn/cm  
8度の引張応力が発生するため、同図に示したごとく、
半導体基板1は凸状に曲げられ、層間絶縁膜としてのシ
リコン酸化膜6はこの凸状に曲げられた半導体基板lの
表面に堆積される。
First, a 2t-1 μm silicon oxide film was deposited on the back surface of the semiconductor substrate l on which electrical wiring etc. were formed by vapor phase growth.
Next, as shown in FIG. 1, the semiconductor substrate 1 is placed on the susceptor 3 maintained at 450°C, and SiH4 gas 4 and 02 gas 5 are supplied to the surface of the semiconductor substrate 1 to form an interlayer insulating film. Then, a silicon oxide film 6 is deposited to a thickness of 1 μm. Here, the silicon oxide film 2 deposited on the back surface of the semiconductor substrate 1 has a thickness of 4×10 dyn/cm at a temperature of 450″C.
Since a tensile stress of 8 degrees is generated, as shown in the figure,
The semiconductor substrate 1 is bent into a convex shape, and a silicon oxide film 6 as an interlayer insulating film is deposited on the surface of the semiconductor substrate l which is bent into a convex shape.

次に層間絶縁膜としてのシリコン酸化膜6上にレジスト
7を塗布し、焼き固めた後、裏面のシリコン酸化膜2t
−7ツ酸系の液にて除去する(第2図)。
Next, a resist 7 is applied on the silicon oxide film 6 as an interlayer insulating film, and after baking and hardening, the silicon oxide film 2t on the back side is
-Remove with a 7tu acid-based solution (Figure 2).

次にレジスト7を有機溶剤にて除去する(第3図)。こ
こで裏面のシリコン酸化膜2が除去されると半導体基板
1よ弾性力によりもとの形状にもどろうとするため、層
間絶縁膜としてのシリコン酸化膜6に対して圧縮応力が
発生し、その結果として層間絶縁膜としてのシリコン酸
化膜6の英効的な内部応力(引張り応力〕は緩和され、
従来法と比較して著しく小さくなる。
Next, the resist 7 is removed using an organic solvent (FIG. 3). When the silicon oxide film 2 on the back surface is removed, the semiconductor substrate 1 tries to return to its original shape due to its elastic force, and compressive stress is generated on the silicon oxide film 6 as an interlayer insulating film. As a result, the effective internal stress (tensile stress) of the silicon oxide film 6 as an interlayer insulating film is relaxed,
It is significantly smaller than the conventional method.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は絶縁膜の内部応力を緩和さ
せることにより、その後の工程での熱的あるいは機械的
起因によるクシツクの発生を著しく低減し、クシツクに
よる電気配線間の短絡やクラックからの不純物の侵入を
防ぐことができ、半導体装置の信頼性を著しく同上させ
る効果がある。
As explained above, the present invention significantly reduces the occurrence of cracks due to thermal or mechanical causes in subsequent processes by relaxing the internal stress of the insulating film, and prevents short circuits and cracks between electrical wiring caused by cracks. It is possible to prevent the intrusion of impurities, which has the effect of significantly improving the reliability of the semiconductor device.

本発明の製造方法は層間絶縁膜に限定されることなく気
相成長法で堆積されるいかなる絶縁膜に対しても適用で
きる。
The manufacturing method of the present invention is not limited to interlayer insulating films, but can be applied to any insulating film deposited by vapor phase growth.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本発明の詳細な説明した断面図で
ある。 1・・・・・・電気配線等が形成された半導体基板、2
・・・・・・気相成長法による裏面シリコン酸化膜、3
・・・・・・サセプター、4・・・・・・8iH4ガス
、5・・・・・・O:ガス、6・・・・・・層間膜とし
てのシリコン酸化膜、7・・・・・・レジスト。
1 to 3 are cross-sectional views illustrating details of the present invention. 1... Semiconductor substrate on which electrical wiring etc. are formed, 2
・・・・・・Backside silicon oxide film by vapor phase growth method, 3
...Susceptor, 4...8iH4 gas, 5...O: gas, 6...Silicon oxide film as interlayer film, 7...・Resist.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板の一主面上に気相成長法により絶縁膜を堆
積する工程において、予め該半導体基板の他主面上に気
相成長法によりシリコン酸化膜を堆積しておき、次に該
半導体基板の一主面上に所望の絶縁膜を堆積した後、該
他主面上に堆積された該シリコン酸化膜を除去すること
を特徴とする半導体装置の製造方法。
In the step of depositing an insulating film on one principal surface of a semiconductor substrate by vapor phase epitaxy, a silicon oxide film is deposited in advance on the other principal surface of the semiconductor substrate by vapor phase epitaxy, and then the semiconductor substrate is deposited by vapor phase epitaxy. 1. A method of manufacturing a semiconductor device, comprising depositing a desired insulating film on one main surface of the semiconductor device, and then removing the silicon oxide film deposited on the other main surface.
JP60108611A 1985-05-20 1985-05-20 Manufacture of semiconductor device Pending JPS61265824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60108611A JPS61265824A (en) 1985-05-20 1985-05-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60108611A JPS61265824A (en) 1985-05-20 1985-05-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61265824A true JPS61265824A (en) 1986-11-25

Family

ID=14489186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60108611A Pending JPS61265824A (en) 1985-05-20 1985-05-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61265824A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332356A (en) * 2005-05-26 2006-12-07 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing method
WO2020184337A1 (en) * 2019-03-13 2020-09-17 東京エレクトロン株式会社 Substrate processing method and substrate processing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332356A (en) * 2005-05-26 2006-12-07 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing method
WO2020184337A1 (en) * 2019-03-13 2020-09-17 東京エレクトロン株式会社 Substrate processing method and substrate processing device

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