JPH02228065A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor resistant layer or a wiring layer and a transistor element to be formed on the same substrate by forming a resist pattern, which covers the second semiconductor layer left on the second insulating film and includes the first semiconductor layer at an opening area, and then performing isotropic etching to the first semiconductor layer. CONSTITUTION:After formation of a polysilicon gate electrode 18, a resist pattern 20, which covers this gate electrode and includes a polysilicon resistant layer 13 in an opening area, is formed, and polysilicon of gate material left at the side face, etc., of the polysilicon resistant layer in the opening area is removed by a chemical dry etching method, so dust generation by exfoliation, etc., of polysilicon left on the side face, etc., of the resistant layer disappears. Accordingly, in a gate electrode formation process, is obviates the necessity of especially considering whether the gate material is not etched and left at the side face, etc., of the polysilicon resistant layer, and it can also prevents overetching of a gate oxide film. Hereby, it becomes possible to form a semiconductor resistant layer or a wiring layer and a transistor element, which is equipped with a semiconductor electrode, on the same substrate.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention provides a first semiconductor layer (for example, a polysilicon resistance layer, etc.) and a second semiconductor layer (for example, a polysilicon gate electrode or a polysilicon emitter layer). The present invention relates to a method for manufacturing a semiconductor integrated circuit (hereinafter abbreviated as IC) having a second semiconductor layer (e.g., electrodes, etc.), in particular, without etching unnecessary portions of the constituent material of the second semiconductor layer (e.g., polysilicon, etc.). This is one type of manufacturing method that prevents it from remaining in the layer.

(Prior Art) As an example, an IC in which a polysilicon resistance layer (first semiconductor layer) and a fine MOS (MOS) transistor provided with a polysilicon gate electrode (second semiconductor layer) are mounted on the same substrate is taken as an example.
The prior art will be explained below.

It is a well-known technique to grow polysilicon on an insulating film, pattern the polysilicon layer, and then dope impurities such as boron (B) or phosphorus (P) to form a resistor. Polysilicon resistors have smaller parasitic capacitance and less voltage dependence than diffused resistors and the like, so they are widely used in analog ICs that require high-precision resistors.

Conventionally, isotropic etching such as chemical dry etching (hereinafter abbreviated as CDB) has been used as an etching method when patterning polysilicon resistors. Recently, anisotropic etching, reactive ion etching (R
eactive Ion [tch+nQ, hereinafter RIE
) is widely used.

On the other hand, in MO3FETs, the gate oxide film is becoming thinner with the progress of miniaturization, and for a gate length of 1.2 μm, the gate oxide film thickness is 250 μm, and for a gate length of 0.8 μm, the gate oxide WAN is as thin as 100 to 150 μm. ing. A polysilicon layer with a thickness of 3,000 to 4,000 wafers is usually used as the gate electrode, and RIE is used for processing. When processing the gate electrode, it is preferable to stop etching when the polysilicon film to be etched is removed and the underlying gate oxide film is exposed. However, considering the variation in the thickness of the polysilicon film, some overetching is necessary. Usually, 10 to 20% overetching is performed. However, as a result of this overetching, the underlying gate oxide film is also slightly etched, so the amount of overetching is decreasing as devices become finer and the thickness of the gate oxide film becomes thinner.

If an attempt is made to realize a polysilicon resistor together with a fine MOS FET using the well-known method as described above, the following problems arise. FIGS. 3A and 3B are cross-sectional views showing the manufacturing process of the IC for explaining this problem. As shown in FIG. 1A, a polysilicon resistance layer 5 is formed on field oxide 11A2 selectively formed on silicon semiconductor substrate 1. As shown in FIG. Next, after forming an oxide film 4 covering the surfaces of the gate oxide film 3 and the resistance layer 5 by thermal oxidation, a polysilicon layer 6 is grown on the oxide film.

As shown in FIG. 6B, selective anisotropic etching is performed on the polysilicon layer 6 to form a gate pole 6a.

In this step, polysilicon, which is the gate electrode material, remains on the side surfaces of the polysilicon resistance layer 5 as sidewalls 6b. The gate electrode of this sidewall polysilicon layer B has a thickness of 3,000 to 40,000 mm at most, and when the oxide 11!4 is etched in the subsequent process, it may peel off from the sides and become dust, reducing the yield. . However, when forming the gate 11fi 6a, 11
If 11 is over-etched so that 6b is not formed, the exposed gate oxide film 3a will be etched, and the underlying silicon substrate 1 may be etched, which is not preferable.

(Problems to be Solved by the Invention) As described in the prior art, for example, fine MOS
When manufacturing an IC in which FFs, Ts, and a polysilicon resistance layer are mounted on one semiconductor substrate, when a polysilicon gate electrode is formed by RIE, polysilicon, which is the gate electrode material, remains on the sidewalls of the resistance layer and There is a problem that it peels off during the process and becomes dust, reducing the yield.

The present invention has been made in view of the above-mentioned drawbacks, and when an electrode made of a semiconductor is formed by RIE, the electrode material is the m1 of a semiconductor resistance layer or wiring layer mounted on the same substrate.
A semiconductor device in which a semiconductor resistance layer or a wiring layer and a transistor element can be formed on the same substrate without etching remaining on the surface and without substantially etching the insulating film interposed between the electrode and the substrate. The purpose is to provide a manufacturing method.

[Structure 1 of the Invention (Means for Solving the Problems) The present invention is a method for manufacturing a semiconductor device characterized by including the following steps.

(a) A step of selectively forming a first insulating film (for example, a field oxide film) on the main surface of the semiconductor substrate.

<b> A step of selectively forming a first semiconductor layer (for example, a polysilicon resistance layer) on the first insulating film.

(C) Element formation region of the semiconductor substrate (for example, MOS
A second insulating film (e.g., gate oxidation plA> and a third
The process of forming an insulating film.

(d) After providing an opening in the semiconductor substrate surface including the second insulating film and the third insulating film (for example, when forming a semiconductor layer with an MO3 structure) or in the second insulating film reaching the semiconductor substrate surface,
A step of growing a second semiconductor layer on the semiconductor substrate surface including the second insulating film and the third insulating film including this opening (for example, when forming tM of a bipolar transistor).

(e) A step of subjecting the second semiconductor layer to selective anisotropic etching to leave the second semiconductor layer on the second insulating film or on the second insulating film including the opening.

([) A step of forming a resist pattern that covers the remaining second semiconductor layer (eg, gate electrode) and includes the first semiconductor layer in the opening region.

(9) Using this pattern as a mask, the second
A process of isotropic etching (eg CDE) of a semiconductor layer.

(h) A step of doping impurities into the first semiconductor layer using the pattern as a mask.

If the order of the steps described in (a) to h) above is not necessarily the order described, for example, after step (h), (
There are cases where the step g) is performed.

Furthermore, in the step described in (C), the second insulating film and the third insulating film may be formed in the same step or in separate steps. In this specification, for convenience, silicide is
Considered a semiconductor.

(Function) Polysilicon resistance layer and MOS FE'! The operation will be explained below, taking as an example a semiconductor device in which "" and "are mounted on a single substrate."

In the manufacturing method of the present invention, polysilicon gate electrode formation (
After the step described in (e)), a resist pattern covering the gate electrode and including the polysilicon resistance layer in the opening region is formed (step described in Since the remaining polysilicon of the gate material is removed by the CDE method (step described in (g)), the generation of dust due to peeling of the polysilicon remaining on the side surfaces of the resistance layer, etc., which was observed in the prior art, is eliminated. Therefore, in the gate electrode forming process, there is no need to pay particular attention to whether or not the gate material remains unetched on the side surfaces of the polysilicon resistance layer, and over-etching of the gate oxide film can also be prevented.

Note that the oxide film (third insulating film) on the surface of the polysilicon resistance layer
acts as a protection layer for the polysilicon resistance layer against etching by the RIE method and CDE method.

Furthermore, in the case where a bipolar transistor is mounted instead of the MOS FET in the example of the semiconductor device, the emitter electrode may be used instead of the gate electrode, and the effect of the present invention is almost the same as described above.

(Example) As an example of the present invention, a method for manufacturing a conductor device including a MOS FET and a polysilicon resistance layer will be described below. FIG. 1 is a sectional view showing the manufacturing process of this semiconductor device.

As shown in the figure <A), a MOS FET formation region 8 and a field oxidation layer 1 are formed on the silicon substrate 7 by a known method.
Forming 1i9 (first insulating film) Next, as shown in the same figure (B), an oxide film 10 with a thickness of 100 to 1000X is formed on the MOS FET formation region 8 by thermal oxidation, and then Then, undoped polysilicon 11 is formed by LPCVD. Next, as shown in FIG.
A polysilicon resistance layer (first semiconductor layer) 13 is formed by etching by RIE using the resist pattern 12 as a mask. Next, the resist pattern 12 is removed, and the oxide film 10 is etched away using NH and F solutions. Next, as shown in the same figure (D), gate oxidation JI! is performed by thermal oxidation. (Second insulating film) 14 is a MOS
It is formed in the FET formation region 8. At that time, the surface of the polysilicon resistance layer 13 is oxidized! (The third insulation 11 and 15 are formed.

Next, as shown in FIG. 5E, polysilicon, which is a gate electrode material, is grown on the substrate surface including the gate oxide film 14 and the oxide film 15 by the PCVD method, and a polysilicon layer (second
A semiconductor layer 16 is formed, and impurities are doped into this polysilicon layer 16 by phosphorous diffusion or the like. Next, the same figure (F
), resist no. (turn 17) is formed by photolithography technique, and anisotropic etching is performed using resist no. (turn 17) as a mask by RIE to form a polysilicon gate electrode 18 (remaining no. At this time, side walls 19 made of polysilicon, which is the gate material, are left without being etched on both sides of the polysilicon resistance layer 13, sandwiching the oxide 1i 115. Next, as shown in FIG. As shown in FIG.
A resist pattern 20 is formed which covers 1 s and includes the polysilicon resistance layer 13 and sidewalls 19 in the opening region. Next, as shown in FIG. 3H, using the resist pattern 20 as a mask, the sidewall 19 made of polysilicon contained in the opening area is removed by isotropic etching such as CDB.
At this time, the MO8FET formation region 8 is covered with the resist 20, so the gate oxide film 14 is not etched.Also, compared to RIE, CDB allows the etching rate of the oxide film to be lower than the etching rate of polysilicon. , is the preferred etching method. Subsequently, as shown in the same figure (1), using the resist pattern 20 as a mask, for example, a 2x10" a of boron is applied at 40 keV.
The polysilicon resistance layer 13 is doped by ion implantation at a dose of 12 tons/cl to determine its resistance value.

After that, by going through known steps, a semiconductor device including a polysilicon resistance layer and a MOS FET is obtained.

According to the manufacturing method of the present invention, when forming the polysilicon gate pole 18, the polysilicon layer 16 is not over-etched more than necessary, and the gate material polysilicon remains on the side surface of the polysilicon resistance layer. It can be prevented. Also, resist pattern 20 used at that time
Since this serves as a mask when ion-implanting impurities into the polysilicon resistance layer 13, there is no need to add an extra resist pattern forming process compared to the conventional technology. Since the silicon resistance layer and the silicon resistance layer can be formed on the same substrate, it has become possible to create an IC that combines a highly accurate analog circuit and a highly integrated CMO8 circuit.

In the above embodiment, the first semiconductor layer is a polysilicon resistance layer, but the present invention is not limited thereto.

That is, it goes without saying that the first semiconductor layer may be a resistance layer or a wiring layer made of a semiconductor containing silicide. In this embodiment, the second semiconductor layer left on the second insulating film is the gate electrode formed on the gate oxide film of the MOS FET, but is not limited to this. For example, as shown in FIG. Of course, the manufacturing method of the present invention can also be applied to cases where a transistor and a polysilicon resistance layer are mounted together. In the same figure,
Reference numeral 50 is a semiconductor substrate, and reference numerals 51, 52 and 53 are a first insulating film, a second insulating film provided with an opening, and a third insulating film, respectively. Further, reference numeral 54 denotes a polysilicon resistance layer (first
(semiconductor layer), 55 and 57 are an emitter and a collector, respectively! (TA-treated second semiconductor layer).

[Effects of the Invention] As described above, according to the method for manufacturing a semiconductor device of the present invention, when electrodes made of semiconductor are formed by selective anisotropic etching, the electrode materials are mounted on the same substrate. The semiconductor resistance layer or wiring layer and the transistor element including the semiconductor electrode are etched without leaving any residue on the side surfaces of the semiconductor resistance layer or the wiring layer, and without substantially etching the insulating film interposed between the electrode and the substrate. It is now possible to form it on a substrate.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a sectional view showing one embodiment of the manufacturing method of the present invention, FIG. 2 is a sectional view showing another embodiment of the manufacturing method of the present invention, and FIG. 3 is a sectional view showing a conventional manufacturing method. It is a sectional view showing a manufacturing method. 7... Semiconductor substrate, 8... Element formation region of semiconductor substrate, 9... First insulating film, 13... First semiconductor layer, 14... Second insulating film, 15... Third 3 insulation film,
16... Second semiconductor layer, 18... Remaining second semiconductor layer, 20... Resist pattern. (B) (C) Figure (2) Figure (1) Figure (3)

Claims (1)

[Claims] 1. A step of selectively forming a first insulating film on the main surface of a semiconductor substrate, a step of selectively forming a first semiconductor layer on the first insulating film, and a step of selectively forming a first semiconductor layer on the main surface of the semiconductor substrate. A step of forming a second insulating film and a third insulating film on the surface of the semiconductor layer, respectively, and reaching the semiconductor substrate surface including the second insulating film and the third insulating film, or reaching the semiconductor substrate surface in the second insulating film. After providing the opening, a step of growing a second semiconductor layer on the surface of the semiconductor substrate including the opening and including the second insulating film and the third insulating film, and performing selective anisotropic etching on the second semiconductor layer. A second insulating film is formed on the second insulating film or on the second insulating film including the opening.
a step of leaving the semiconductor layer; a step of forming a resist pattern that covers the remaining second semiconductor layer and includes the first semiconductor layer in the opening region; and a step of forming the second semiconductor layer included in the opening region using this pattern as a mask. A step of performing directional etching,
A method for manufacturing a semiconductor device, comprising the step of doping an impurity into a first semiconductor layer using the pattern as a mask.