JPH02226452A - Supervisory system for processor bus - Google Patents

Abstract

PURPOSE:To improve the efficiency of fault analysis and the clearing up of a cause by minutely preserving various information transferred through a processor bus for a prescribed period when an abnormality control signal whose continuous period is shorter than the prescribed period is generated. CONSTITUTION:A transfer information storage means 100 stores various information transferred between respective devices through the processor bus 4 for a latest prescribed period. When a signal width supervisory means 200 supervises the continuous period of a control signal which is transferred via the processor bus 4 and which is for the storage device 2, and when the control signal having the continuous period shorter than the prescribed period is detected, the means 200 stops the storage of various information by the transfer information storage means 100 after the previously decided period. Consequently, various information transferred through the processor bus can minutely be preserved for the prescribed and period when the abnormality control signal whose continuous period is shorter than the prescribed period is generated. Thus, the efficiency of fault analysis and the clearing up of the cause can considerably be improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a processor bus monitoring method in an information processing system in which a processor, a storage device, and various input/output devices are connected by a processor bus and mutually transfer information via the processor bus. The failure state caused by the control signal having a shorter duration is stored in as much detail as possible,
For the purpose of improving the efficiency of failure analysis, there is a transfer information storage means that stores various information transferred between each device via the processor bus over a recent predetermined period; monitors the duration of the control signal to the storage device, and when a control signal having a duration shorter than a predetermined period is detected, stops the storage of various information by the transfer information storage means after a predetermined period. The structure is such that a signal width monitoring means is provided.

C. Industrial Application Field] The present invention relates to an information processing system, and particularly to a processor in an information processing system in which a processor, a storage device, and various input/output devices are connected by a processor bus, and information is mutually transferred via the processor bus. Regarding bus monitoring methods.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional information processing system.

In FIG. 4, a processor 1, a storage device 2, and an input/output device 3 are connected by a processor bus 4,
Processor 1 connects to storage device 2 via processor bus 4.
, the required address a, data d (for writing),
Also, data d is written in a predetermined storage area (address a) of the storage device 2 by transferring a control signal (hereinafter referred to as a command) that controls the write or read operation.
Or read data d from a predetermined storage area.

Processor l also controls input/output device 3 to read and write data d to storage device 2 .

Note that the processor 1 and the input/output device 3 add an error detection code such as a parity check code or an error detection and correction code to the data d to be written to the storage device 2, and write the data d to the storage device 2. By performing an error check on the data d read from the storage device 2
The data d stored in the file is being verified.

On the other hand, as the speed of the processor 1 increases, the number of devices sharing the processor bus 4 also increases. If an abnormal command occurs such that the duration of the command transferred to the storage device 2 is shorter than a predetermined period, a failure may occur in which the storage contents of the storage device 2 are destroyed.

Although the occurrence of such a failure can be detected after the fact using the above-mentioned error detection code, it is impossible to analyze the failure and find out the cause of the failure.

[Problem to be solved by the invention]

As is clear from the above explanation, in conventional information processing systems, it is possible to detect after the fact that the storage contents of the storage device 2 have been destroyed using an error detection code, etc., but the duration of the command is Since it is impossible to detect the cause of a shorter period than a predetermined period, there is a problem in that it takes a long time to analyze the failure.

An object of the present invention is to save as much detail as possible a failure occurrence state caused by a control signal having a duration shorter than a predetermined period, and to improve the efficiency of failure analysis.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, l is a processor, 2 is a storage device, 3 is an input/output device, and 4 is a processor bus, which constitute an information processing system.

lOO is a transfer information storage means provided in the information processing system according to the present invention.

200 is a signal width monitoring means provided in the information processing system according to the present invention.

[Effect]

Transfer information storage means 100 stores various information transferred between devices via processor bus 4 over a recent predetermined period.

The signal width monitoring means 200 monitors the duration of the control signal to the storage device 2 transferred via the processor bus 4, and when a control signal having a duration shorter than a predetermined period is detected, After a period of time, storage of various information by the transfer information storage means 100 is stopped.

Therefore, when an abnormal control signal is generated in which the interval between serials m, #, and 11 is shorter than the predetermined period, it is possible to retain the various information transferred via the processor bus in detail over the predetermined period before and after. This makes it possible to greatly improve the efficiency of failure analysis and cause investigation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an information processing system according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a monitor storage section in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the transfer information storage means 1 in FIG.
Address generation unit 61 forming the monitor circuit 6 as 00
, a monitoring storage section 62, and a clock generation section 63, and a counting stop section 64 constituting the signal width monitoring circuit 5 and the monitor circuit 6 as the signal width monitoring means 200 in FIG.

In FIGS. 2 and 3, an address generating section 61 in the monitor circuit 6 generates a signal from "0" to rM in synchronization with a clock signal CK having a predetermined period τ supplied from a clock generating section 63.
Consisting of a counting circuit that repeatedly counts and outputs J, the count value "0" to rMJ is stored in the monitor storage unit 62 at address a.
Communicate as.

The monitor storage unit 62 is connected via the processor bus 4 to
Various information such as addresses, data, and commands transferred between the processor 1, the storage device 2, and the input/output device 3 are extracted in synchronization with the clock signal CK supplied from the clock generation section 63, and are extracted from the address generation section 61. The data is first stored in addresses a (=rOJ to "MJ>" transmitted from
In order to store data sequentially starting from the first address a (-rOJ), the monitor storage unit 62 stores the most recent predetermined period T (=τ×N
) (however, N-M+1), various information transferred via the processor bus 4 is stored.

On the other hand, the signal width monitoring circuit 5 samples the duration of the command transferred from the processor 1 and the input/output device 3 to the storage unit W2 via the processor bus 4, for example, at a cycle sufficiently shorter than the duration of the command. The system is being monitored by means of 1. When an abnormal command having a continuation period shorter than a predetermined period is detected, an interrupt signal IRQ is transmitted to the processor l, and a stop signal STP is transmitted to the monitor circuit 6.

In the monitor circuit 6, the counting stop section 64 receives the stop signal STP from the signal width monitoring circuit 5 at the time 1. From then on,
Clock supplied from the clock generator 63 (No. 8 CK
When it detects that the n-cycle clock signal CK is supplied, it transmits an address supply stop instruction ASP to the address generation section 61.

The address generation unit 61 outputs the monitor storage unit 62 at the time point [,
If the address a1 is generated for the address a1, n addresses (a+1) to (a, +n) are generated and stored in the monitor storage section until the address supply stop instruction ASP is transmitted from the signal width monitoring circuit 5. 62, and when the address supply stop instruction ASP is transmitted, the monitor storage unit 62
Immediately stops supplying address a to address a.

The monitor storage unit 62 stops operating after storing various information transferred via the processor bus 4 up to address (at+fi).

Therefore, in the monitor storage unit 62, from the time t1 when the signal width monitoring circuit 5 detects a command having a duration shorter than a predetermined period, from before (N-n) τ to after n, the processor bus Various information transferred via 4 is saved.

Note that n can be set arbitrarily between rOJ and rNJ, so if n=rQJ, the counting stop section 64 immediately sends the address stop instruction ASP upon receiving the stop signal STP from the signal width monitoring circuit 5. After transmitting the address a, the address generating section 61 immediately stops transmitting the address a, so the monitor storage section 6
2, various information on the salt before Nτ (=T) from time t is stored, and if n=rNJ is set, the counting stop section 64 receives the stop signal STP from the signal width monitoring circuit 5. transmits an address stop instruction ASP to the address generation unit 61 after a clock signal of N cycles has been supplied;
The address generation unit 61 transmits the address a1 and then transmits N addresses a up to address (al +N), and then stops transmitting the address a, so the monitor storage unit 61 stops transmitting the address a.
2, various information from time t to after Nτ (=T) will be stored.

On the other hand, the processor 1 that has received the interrupt signal IRQ extracts the storage contents of the monitor storage unit 62 from which extraction and storage of various information from the processor bus 4 has been stopped via the processor bus 4, and stores them in the processor bus 4. After storing the data in the connected external storage device 7, initial settings and restart processing of the information processing system are executed.

The diagnostician investigates the cause of the failure due to the abnormal command detected by the signal width monitoring circuit 5 by analyzing the memory contents stored in the external storage device 7.

As is clear from the above description, according to the present embodiment, the signal width monitoring circuit 5 detects a command whose duration is shorter than the predetermined period during the predetermined period T before and after the time t2 when the signal width monitoring circuit 5 detects a command whose duration is shorter than the predetermined period. Since various information transferred is saved,
The occurrence of a failure caused by such an abnormal command can be analyzed in detail, and the cause can be investigated efficiently.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and the information processing system to which the present invention is applied, for example, is not limited to what is shown in the figures, and may be modified in many other ways. However, the effects of the present invention remain the same in either case.

〔Effect of the invention〕

As described above, according to the present invention, when an abnormal control signal whose duration is shorter than a predetermined period occurs in the information processing system, various information that has been transferred via the processor bus is transferred over a predetermined period before and after. It becomes possible to have detailed information, and the efficiency of failure analysis and cause investigation can be greatly improved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an information processing system according to an embodiment of the present invention, and FIG. 3 is a diagram showing the monitor storage unit in FIG. The illustrative diagram, FIG. 4, is a diagram showing an example of a conventional information processing system. In the figure, 1 is a processor, 2 is a storage device, 3 is an input/output device, 4 is a processor bus, 5 is a signal width monitoring circuit, and 6
7 is a monitor circuit, 7 is an external storage device, 61 is an address generation section, 62 is a monitor storage section, 63 is a clock generation section, 6
4 is a counting stop section, 100 is a transfer information storage means, 200 is a signal width monitoring means, principle diagram of the present invention. 2 [ff1l: 1st, Yusou Miyami +, Eishata P 3rd
Figure is here + Shinbei'gL Kuri Kuri System Akira Cow
figure

Claims (1)

[Claims] An information processing system in which a processor (1), a storage device (2), and various input/output devices (3) are connected by a processor bus (4), and information is transferred via the processor bus (4), transfer information storage means (100) for storing various information transferred between the devices via the processor bus (4) over a recent predetermined period; monitors the duration of the control signal to the storage device (2), and if a control signal having a duration shorter than a predetermined period is detected, the transfer information storage means (100) 1. A processor bus monitoring system, comprising: a signal width monitoring means (200) for stopping storage of the various information.