JPH02222192A - Wiring pattern for printed board - Google Patents
Wiring pattern for printed boardInfo
- Publication number
- JPH02222192A JPH02222192A JP4486989A JP4486989A JPH02222192A JP H02222192 A JPH02222192 A JP H02222192A JP 4486989 A JP4486989 A JP 4486989A JP 4486989 A JP4486989 A JP 4486989A JP H02222192 A JPH02222192 A JP H02222192A
- Authority
- JP
- Japan
- Prior art keywords
- land
- soldering
- divided
- lands
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 abstract description 15
- 230000002950 deficient Effects 0.000 abstract description 6
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、面実装用のプリント基板の配線路パターンに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring path pattern for a printed circuit board for surface mounting.
面実装部品をプリント基板に実装するために従来より第
5図に示すように部品実装用ランドパターン(以下、ラ
ンドと呼ぶ)を使用し、このランド上にクリーム状の半
田を塗布し加熱することによって部品10の端子11と
該ランド12との半田付けを行うものであるが、部品の
ズレまたは浮きが発生した場合で特にそのズレまたは浮
きが部分的な場合にはそれらの欠陥を半田不良として検
出できないことが多かった。それらの事例は第6図(a
)及び第6図(b)に示す通りであり、まず、第6図(
a)は電子部品のズレによって端子a1とランドb1と
が接触しているものへ両者の半田付けは不充分である状
態を示し、この場合、−時的な電気的接触が端子a1−
ランドb1間にあるため検査工程で良品と判定されるも
後の工程か完成品の使用中に接触不良となってしまう恐
れがある。第6図(b)は電子部品の端子a2がランド
b2上で浮いている状態を示し、この場合にも第6図(
a)と同じ問題を持つものである。Conventionally, in order to mount surface mount components on a printed circuit board, a component mounting land pattern (hereinafter referred to as a land) is used as shown in Figure 5, and creamy solder is applied and heated on this land. The terminal 11 of the component 10 and the land 12 are soldered by the method, but if the component shifts or lifts, especially if the shift or lift is only partial, these defects are treated as soldering defects. It was often undetectable. Those cases are shown in Figure 6 (a
) and Fig. 6(b). First, Fig. 6(
A) shows a state in which the terminal a1 and the land b1 are in contact with each other due to misalignment of the electronic components, and the soldering between the two is insufficient.
Since it is located between the lands b1, even if it is determined to be a good product in the inspection process, there is a risk that a contact failure will occur in a later process or during use of the finished product. FIG. 6(b) shows a state in which the terminal a2 of the electronic component is floating on the land b2, and in this case also, as shown in FIG.
This has the same problem as a).
本考案は、上述のように部品のズレまたは浮きが部分的
なものであってもそれらを半田不良として確実に検出で
きるようするものである。As described above, the present invention allows parts to be reliably detected as solder defects even if they are partially displaced or lifted.
本発明では、部品の端子の一つに対して電気的に接続さ
れ少なくとも2つ以上に分割されたランドを1ランドど
してプリント基板の配線路パタンを構成することによっ
て上記の問題点を解決するものである。In the present invention, the above-mentioned problem is solved by configuring the wiring path pattern of the printed circuit board by forming a land that is electrically connected to one of the terminals of the component and divided into at least two parts. It is something to do.
本発明では、分割されたランド間の電気導通状態をチエ
ツクすることによって端子−ランド間の半田付は状態の
良否を判定するものである。In the present invention, the quality of the soldering between the terminal and the land is determined by checking the state of electrical continuity between the divided lands.
第1図は、本発明の実施例を示すものでランド1は分割
ランド1aと分割ランド1bに2分割されており同図示
のように電子部品の端子2がランド1と正常に半田例け
が為されていることは分割ランド1aと分割ランド1b
間に電気的導通状態があることをもって確認されるもの
である。第2図(a)、第2図(b)、第3図(a)、
第3図(b)は本発明の実施例を補足説明するた袷のも
ので、まず、第2図(a)及び第2図(b)は電子部品
のズレによって電子部品の端子2が一方の分割ランド1
aとのみ半田例けが為されている状態を示し、この場合
はその検査時に分割ランド1aと分割ランド1b間に電
気的導通状態がないことをもって半田付けが不良である
と判定される。また、第3図(a)及び第3図(b)電
子部品の浮きにより電子部品の端子2が一方の分割ラン
ド1aとのみ半田(−1けが為されている状態を示し、
この端子a2が分割ランドb21で浮いている状態を示
し、この場合においてもズレによる半田不良の場合と同
様に不良の判定がされろ。第4図は本発明の他の実施例
を示しランド3は分割ランド3a、分割ランド3b、分
割ランド3c、分割ランド3dとに4分割されており同
図示のように電子部品の端子4がランド3と正常に半田
(=Iけが為されているか否かは、全分割ランド3a乃
至3a間に総て電気的導通状態がある否かをもって確認
される。従って、この実施例によれば第1の実施例より
もシビャーな半田付は状態の良否の判定が出来るもので
ある。FIG. 1 shows an embodiment of the present invention, in which a land 1 is divided into two parts, a divided land 1a and a divided land 1b, and as shown in the figure, the terminal 2 of an electronic component can be connected to the land 1 normally to avoid soldering injuries. What is done is divided land 1a and divided land 1b.
This is confirmed by the presence of electrical continuity between the two. Figure 2 (a), Figure 2 (b), Figure 3 (a),
FIG. 3(b) is a supplementary explanation of the embodiment of the present invention. First, FIGS. 2(a) and 2(b) show that the terminal 2 of the electronic component is shifted to one side due to misalignment of the electronic component. division land 1
Only the symbol "a" indicates a state in which the solder is damaged, and in this case, it is determined that the soldering is defective based on the fact that there is no electrical continuity between the divided lands 1a and 1b during the inspection. In addition, FIGS. 3(a) and 3(b) show a state in which the terminal 2 of the electronic component is soldered (-1) only to one divided land 1a due to the floating of the electronic component,
This shows a state in which the terminal a2 is floating on the divided land b21, and in this case as well, a defective determination is made in the same way as in the case of a soldering defect due to misalignment. FIG. 4 shows another embodiment of the present invention, and the land 3 is divided into four parts: a divided land 3a, a divided land 3b, a divided land 3c, and a divided land 3d.As shown in the figure, the terminal 4 of the electronic component is connected to the land. 3 and whether soldering (=I) has been performed normally is confirmed by checking whether or not there is electrical continuity between all the divided lands 3a to 3a. Therefore, according to this embodiment, the first The soldering is more severe than the embodiment described above, and it is possible to judge whether the condition is good or bad.
以上のように、本発明によれば、プリント基板の配線路
パターンのラント部を互いに絶縁され2分割以上される
ものとして形成しそれら分割されたランド間の電気導通
状態をチエツクすることによって端子−ラント間の半田
イ」け状態の良否を判定するものであるから、部品のズ
レまたは浮きに起因する不完全な半田付は状態のものを
半田不良として確実に検出できるものである。As described above, according to the present invention, the runt portions of the wiring path pattern of a printed circuit board are formed into two or more parts that are insulated from each other, and the electrical continuity between the divided lands is checked. Since the soldering condition between the runts is judged to be good or bad, incomplete soldering caused by misalignment or lifting of components can be reliably detected as defective soldering.
第1図は、本発明の実施例を示す斜視図、第2図(a)
、’第2図(b)、第3図(a)、第3図(b)は本発
明の実施例を補足説明するた杓のもので第2図(a)は
平面図、第2図(b)は側面断面図、第3図(a)は平
面図、第3図(b)は側面断面図であり、第4図は本発
明の他の実施例を示す斜視図、第5図は従来例を示す斜
視図、第6図(a)及び第6図(b)は従来例を説明す
るだめの断面図である。FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2(a)
,' Fig. 2(b), Fig. 3(a), and Fig. 3(b) are supplementary explanations of the embodiments of the present invention, and Fig. 2(a) is a plan view, and Fig. 2(a) is a plan view. 3(b) is a side sectional view, FIG. 3(a) is a plan view, FIG. 3(b) is a side sectional view, FIG. 4 is a perspective view showing another embodiment of the present invention, and FIG. 6 is a perspective view showing a conventional example, and FIGS. 6(a) and 6(b) are sectional views for explaining the conventional example.
Claims (1)
てなるプリント基板の配線路パターン。(1) A wiring route pattern of a printed circuit board comprising land portions that are mutually insulated and divided into two or more parts.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4486989A JPH02222192A (en) | 1989-02-22 | 1989-02-22 | Wiring pattern for printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4486989A JPH02222192A (en) | 1989-02-22 | 1989-02-22 | Wiring pattern for printed board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02222192A true JPH02222192A (en) | 1990-09-04 |
Family
ID=12703505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4486989A Pending JPH02222192A (en) | 1989-02-22 | 1989-02-22 | Wiring pattern for printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02222192A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563345A (en) * | 1991-09-03 | 1993-03-12 | Nec Corp | Printed board |
JPH0528075U (en) * | 1991-09-20 | 1993-04-09 | 日本電気株式会社 | Printed wiring board |
-
1989
- 1989-02-22 JP JP4486989A patent/JPH02222192A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563345A (en) * | 1991-09-03 | 1993-03-12 | Nec Corp | Printed board |
JPH0528075U (en) * | 1991-09-20 | 1993-04-09 | 日本電気株式会社 | Printed wiring board |
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