JPH02222153A - Elevated source/drain transistor and its manufacture - Google Patents

Abstract

PURPOSE: To manufacture a FET which prevents intrusion of silicide on the source/drain layers into an Si substrate by using side spacers adjacent to both of field insulating layers and the source/drain layers. CONSTITUTION: The surface of an Si substrate is separated by insulating layers 44 and then covered with SiO2 thin sidewalls 54. Next, shallow pn junction layers 56 are formed by ion implantation. Next, source/drain layers raised by Si epitaxial layers 60 are formed. Successively, insulating spacers 64, 66 adjacent to the layers 60 are selectively formed. Next, the other shallow junction layers 68 thicker than the former junctions 56 and lightly doped regions 70 are formed by the second ion implantation. Next, TiSi2 layers 72, 54 are formed on the source/drain layers and the gate layer 48. In such a constitution, the probability of the TiSi2 formed on the source/drain layers intruding into the Si substrate is minimized, thereby enabling the title FET having stable operational characteristics to be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to the manufacture of one-herald transistors. More particularly, the present invention relates to a MOSFET with elevated lath/drain regions and a method of manufacturing the same.

BACKGROUND OF THE INVENTION [Prior Art and Its Problems] Recent MOS rTE -r + transistor technology utilizes elevated source/drain regions to obtain transistors with extremely shallow junctions.

This elevated source/train region creates a divine problem. A small surface typically forms at the interface where the raised source/drain region meets the insulator field oxide of the one-helang transistor structure.

Additionally, small surfaces typically form at the interface where the raised source/drain region meets the sidewall space insulator adjacent transistor gate 1. Later silicide treatment ■D3 in the culm, spike regions can form at any small surface location, and these spike regions can penetrate into the underlying semiconductor substrate and penetrate shallow junctions. be. This spike region therefore creates a short circuit for the source/drain to the silicon substrate.

In elevated source/drain transistor structures, it is important to control the diffusion of the dopants used to create the shallow 1-transistor junctions.

A raised source/drain is typically used to create an electrical connection under the thick sidewall space insulator and thereby make an electrical connection between the moat region and the channel region. Before the deposition of the area, the first
An injection step is performed. However, in the subsequent deposition step of the elevated source/drain regions,
The dope agent previously deposited in J may become further diffused, thereby altering the operating characteristics of the device.

Another problem with modern raised source/drain transistors is the ease with which the silicide contact regions are created. If the gate and lath/drain regions are not properly isolated from each other, an S-conducting circuit can form between the silicidation process and either the source or drain. Can be done. Additionally, it is difficult to later etch the silicided region to separate the gate from either the source or drain, since silicate is unintentionally created between the gate and the source/drain. .

Therefore, it does not suffer from the problems of the formation of spike regions, uncontrolled migration of dopants, and the difficulty of electrically isolating the gate from the source/drain regions.
Elevated source/drain transistors were desired.

SUMMARY OF THE INVENTION The present invention provides a new and improved source/source transistor having significantly fewer or virtually no disadvantages and problems suffered by prior art transistors having elevated moat regions.
A drain transistor processing step is obtained.

A transistor according to the invention has a gate insulator between opposing moat insulator regions at the surface of the semiconductor. A gate is created on top of this gate insulator. The initial sidewall space insulator thickness is thin enough that the dopants implanted after the creation of the elevated source/drain can move laterally within the substrate, leaving the source/drain region between 1 and 2 transistors. It is possible to electrically connect to the channel region while maintaining a shallow transistor junction. The transistor has an elevated Mo1 (source/drain) region located along the Mo1 region between the gate sidewall insulator and the field and insulator regions. Typically, the raised moat region is constructed of full silicon.

Additionally, the initial sidewall space insulator thickness is sufficient to prevent the growth of evitaxy silicon on the gate sidewalls during the creation of the raised moat region. .

In the present invention, there is also a first sidewall spacer located adjacent to the gate sidewall insulator and also located adjacent to the raised MO1 region. In general, a second sidewall spacer is created adjacent the raised moat region and the field insulator region. More specifically, the first side wall spacer and the second side wall slide according to the present invention can be formed by forming an insulator oxide 'c'.

An important feature of the present invention is to create an elevated source/train transistor that allows controlled doping of very shallow junctions after deposition of the elevated moat region.

By using a thin sidewall insulator, it is possible to create an electrical connection between the source/train region and the channel, either during or after the creation of the source/drain region. can.

Compared to prior art process steps, this feature of the present invention reduces the uncontrolled migration of previously implanted dopants during the process step of depositing the elevated source/drain regions. can be prevented.

Additionally, another important engineering advantage of the present invention is the use of sidewall spacers adjacent the gate insulator and raised source/drain regions. This spacer effectively increases the distance between the groove 1 and the source/train region. As a result, better control can be achieved in creating separate silicided regions over the gate and source/drain regions in later process steps.

Additionally, the larger slope between the gate and source/train regions may prevent short circuits that may occur in creating the silinide therebetween. Another technical advantage associated with this sidewall slippage is that the small surface underlying the spacer is no longer exposed during the silicidation process. As a result, silicide particles penetrate through the small surface and into the semiconductor substrate.
The probability of a spike region being created is small.

Another technical advantage of the present invention is the use of sidewall svanas adjacent both the field insulator regions and the raised source/drain regions. This space →
Without j, the presence of silicide spacers prevents the creation of silicide spike regions during the silicidation process. As a result, the possibility that silicide formed on the source/drain regions will penetrate into the semiconductor substrate is reduced.

[Example] The present invention will be described in detail below with reference to the accompanying drawings. This description will enable a thorough understanding of the invention, and will enable one to appreciate other advantages of the invention.

FIG. 1 is a cross-section of a raised source/drain transistor, generally indicated at 10, according to the prior art. A transistor 10 is fabricated on a semiconductor substrate 12. Field insulator region 1
4 are fabricated on the substrate 12, thereby defining a moat region 16 therebetween. Mote area 16
A gate 18 is created within. Goo 1 to 18 are separated from semiconductor substrate 12 by Goo 1 to insulator 20 . By creating the gate 18, the intermediate region 22
is determined. A lath/drain region is created within this intermediate region. The initial implant step creates a very shallow junction region 24. This junction area is
Channel area 26 and source/below Goo I~18
The drain region is electrically connected to the drain region.

A sidewall insulator 28 is created adjacent the sidewalls of gate 18. Typically, sidewall insulator 28 is comprised of oxide C and has a thickness of ioo.

~3000 angstroms. Elevated source/drain regions 3o are then created on the exposed surface of semiconductor substrate 12 within the remaining region of intermediate region 22. Typically, this raised source/drain region 30 is comprised of an epitaxial layer. The process of forming the source/drain region 30 includes a high temperature process. During this high temperature process, the dopant in the very shallow junction 24 moves further into the semiconductor substrate 12, both depthwise and laterally. This diffusion of dopant is undesirable. In creating the source/drain region 30, interstitial regions or subsurfaces 32 and 33 are created. A small surface 32 is formed at the interface between the source/drain region 30 and the field insulator region 14;
3 is formed at the interface between sidewall insulator 28 and raised source/drain region 30.

A silicide region 34 is created over the raised source/drain region 30 and a silicide region 36 is created over the gate 18. Due to the small surfaces 32 and 33 of the interface, the sirilyoid region 34 penetrates through it, thereby creating a spike region 38 and a spike region 39 (shown in dotted lines). The regions are extended into the semi-conductor substrate 12.As a result, the spike regions 1ti38, 39, and the raised source/drain regions 30
and substrate 12, thereby transistor 1
0 operating characteristics are impaired.

FIG. 2A shows a raised source/drain structure according to the present invention.
4 is a cross-sectional view of a transistor 40. FIG. transistor 4o
is fabricated by being integrated on the semiconductor substrate 42. Insulator regions 44 are created on the semiconductor substrate 42, and moat regions 46 are formed between the insulator regions 44. Goo i~48 is created on the semiconductor substrate 42. Gate 48 is separated from the semiconductor substrate by gate insulator 50. Gate 48 is typically constructed of polysilicon. Goo 1-4
8 is created so that the field insulator region 44
An intermediate region 52 is formed in the region 46 between the gate 48 and the gate 48 .

In a typical case, the field insulator area 1fi 4.4
and Goo 1 to insulator 50 are all composed of oxides.

The thickness of the gate insulator can be on the order of 50 to 250 angstroms, to prevent lateral growth of gate 48 in subsequent process steps.
An additional oxide layer of about 500 to 1000 angstroms can be created on the 8' second side.

However, under ideal conditions where Goos 1-48 do not grow laterally, there is no need to create this additional oxide layer.

Adjacent to the sidewalls of gate 48, a thin initial sidewall space insulator 54 is created. Typically, this initial thin sidewall space insulation 54 is comprised of an oxide;
And the thickness is about 200-900 onges 1-[comb. A very shallow junction region 56 is then created in the semiconductor substrate 42 in the intermediate region 52 by implantation. The junction area 1a56 is made of an N-type material (eg, arsenic, phosphorus, or antimony) or a P-type material 1. (for example,
The initial thin sidewall space insulator 54 is made by implanting either boron) into a surface compact of 5 x 1011/an3 to 1 x 1020/cm'' with fN+ concomitant doping in the junction region. In order to allow sufficient lateral movement of the agent to make an electrical connection between the intermediate region 52 and the transistor channel region 58, it is also necessary to minimize the depth of the shallow junction region [56]. , the thickness is made sufficiently small. This aspect of the invention is important, as the presence of a shallow junction region is fundamental for the advantages associated with elevated source/drain transistors. While these advantages are retained, the electrical connection from the source/drain region to the channel region can be made before or after the creation of the source/drain region 60 (see FIG. 2B). Additionally, the initial wide sidewall space insulator thickness 54 is reduced during the creation of the raised source/drain regions 60 at the gate 48.
(See Figure 2B).

Figure 2B shows the raised source/
FIG. 4 is a cross-sectional view after the processing stages of the drain 1 to the transistor 40 have been completed. Elevated source/drain regions 60 are generally created in intermediate regions 52 at the surface of semiconductor substrate 42 . The raised source/drain regions 60 are made of epitaxial silicon of 1100 nm.
It is prepared by selectively depositing a layer of thickness in the range of ~2000' Angus 1 ~ [1-mm]. Field insulator region 44 and elevated source/drain region 60
There is a small surface 62 between, while a small surface 63 is present at the interface between the raised source/drain region 60 and the initial thin sidewall space insulator 54.

Unlike the above explanation in Fig. 2, the raised source/
It should be noted that it is also possible to create the shallow junction region 56 after creating the drain region 60. The initial thin sidewall space insulator 54 thickness is made sufficiently thin that when the implant is performed after the raised source/drain regions 60 are created, the dopants migrate laterally and It is possible above to electrically connect the raised source/drain region 60 to the transistor channel region 58. Therefore, one important advantage of the present invention is that shallow junctions 56 can be created either during or after the creation of the raised source/drain regions 6o, and in either case the b transistor channel 1) flexibility in making appropriate electrical connections to region 58;

FIG. 2C shows the raised source/drain of the present invention.
2 is a cross-sectional view of a transistor 40 with additional spacers. FIG. A first sidewall spacer 64 is created adjacent the initial thin sidewall space insulator 54 and the corresponding raised source/drain region 6o. Field insulator region 44 and elevated source/
A second sidewall space '4j66 is created at the pre-existing subsurface 62 (see FIG. 2B) between the drain region 60. The spacer 64 and the spacer 66 are connected to the transistor 4
0 to a thickness of approximately 1000 to 2° OO onges and then etching the insulator layer to form the first sidewall spacer 64 and the second sidewall spacer 66. They can be created at the same time.

FIG. 2D is a cross-sectional view of the raised source/drain transistor 4o of the present invention after the second implantation step and the addition of silicon regions. After the first sidewall spanner 64 and the second sidewall spanner 66 are created, the second
An injection step is performed. This second implant step is a shallow junction 6
8 and further doping the elevated source/drain regions. Shallow junction 68 is thicker than extremely shallow junction 56 (see Figure 2A). Because the thickness of the first sidewall spacer 64 is so large, a significant portion of the implant will be held back and less implanted into the underlying region 70 within the raised source/drain region 60. Therefore, the dopant concentration in the lower region 7o will be different from the dopant in the remaining regions of the elevated source/drain region 60 by 11 degrees.

Low resistance silicon regions 72 and 74 are created over the raised source/drain regions 60 and goons 1-48, respectively. Creation of the silylide regions 72 and 74 includes:
This is done by depositing a layer of titanium over the entire structure and then reacting in a nitrogen atmosphere. The silicon in the raised source/drain regions 60 reacts with the layer of titanium, thereby creating titanium silicide (TiSi2) over the exposed silicon regions.

However, in the absence of underlying silicon, titanium will only react with a nitrogen atmosphere. To this end, titanium nitride (TAN) is fabricated on silicon-free surfaces such as field insulator regions 44 and spacers 66 and 64. As a result, when the N portion is selectively removed, low resistance silicide regions 72 and 74 remain as electrical contact areas for the 1-transistor 40.

It will be seen that the first sidewall space 64 effectively increases the distance between the raised source/drain region 60 and the contacting surface of the gate 48. The increased distance between the source/drain region 60 and the grooves 1-48 provides two important benefits: first, the first spacer 64 increases the thickness of the insulator material; The sidewalls of the gate 48 are prevented from reacting with the titanium layer during the process of creating the silicide.Second, the distance between the raised source/drain region 1yi60 and the gate 48 is large. This makes it difficult for silicide to be formed between them, thereby reducing the possibility of short circuits being formed between them.Furthermore, silicide is less likely to be formed between the gate 48 and the source/drain region 60. This makes it difficult to etch when attempting to remove this defective connection, while not disturbing the rest of the device. This potential difficulty is ameliorated by increasing the distance between the first sidewall spacer 64, which also prevents silicide from being created in the minor surface 63 (see Figure 2B). As a result, the possibility of forming a spike region 39 (see Figure 1) is effectively reduced.

The addition of the second sidewall spacer 66 prevents the creation of silicide within the small surface 62 (see Figure 2B). As a result, the likelihood of the formation of spike regions 1438 (see FIG. 1), which occur in the prior art, is effectively reduced, thereby making the device more reliable in operation. .

The present invention provides an elevated source/drain transistor that significantly overcomes the problems associated with such prior art devices. .

An initial thin sidewall space insulator is provided, which allows the raised source/drain region to be
Dopant implantation to connect the channels can optionally be performed either before or after epitaxial full silicon deposition. Additionally, the gate sidewalls are protected from silicon growth during the creation of the elevated source/drain regions. Adding the first sidewall spacer increases the thickness of the insulator between the raised source/drain region and the gate. As a result, it is prevented that the sidewall of the gate reacts with the sidewall of the gate formed on the exposed silicon region of the transistor. The possibility of creating a short circuit between the gate and the raised source/drain region is also reduced. The second sidewall spacer created at the interface between the raised source/train region and the 7-yield insulator region reduces the possibility of creating a silicide spike region that penetrates this interface, and Increase the operational reliability of the equipment. Similarly, the first sidewall spacer prevents silicide spike regions from penetrating and forming at the interface between the initial thin sidewall spacing insulator and the raised source/drain region.

Although the present invention has been disclosed in detail, it should be understood that various modifications and substitutions can be made within the scope of the claims.

Regarding the above description, the following sections are further disclosed.

(1) a semiconductor substrate; a first insulator region and a second insulator region disposed outwardly from the substrate to define a moat region therebetween; and a first insulator region and a second insulator region disposed outwardly from the moat region; , a gate having sidewalls and defining a channel region in the substrate therebelow; a thin sidewall insulator adjacent to the sidewall of the goo; a raised moat region disposed between an insulator and the first insulator region, wherein dopants injected through the raised moat region migrate laterally within the front plate; the thin sidewall insulator has a thickness of J that is capable of electrically connecting the raised moat region to the channel region and retaining a shallow junction in the substrate; , Transistor 1° (2) In paragraph 1, the thin sidewall insulator has a thickness of 900 angstroms or less,
The transistor.

3. The transistor of claim 1 further comprising a first sidewall spacer disposed adjacent the thin sidewall insulator and the raised moat region.

(4) The transistor according to item 3, wherein the first sidewall spacer is made of an insulator.

(5) The transistor according to item 1, wherein the first insulator region roughly has a second sidewall subbene located adjacent to the raised upper region.

(6) The helangister according to item 5, wherein the second side wall spacer is constituted by a piece.

(7) In paragraph 1, the raised moat region further comprises a region A'3 adjacent to the first sidewall space →j, and the dopant repulsion in the region is controlled by the moat region. Said transistor having a dopant density different from that of the remaining regions.

(8) The transistor of paragraph 1, wherein the raised moat region comprises one pit axial silicon.

(9) a semiconductor substrate; a first insulator region and a second insulator region disposed outward from the substrate to define a region 7-1 therebetween; disposed outward from the moat region; and a goo 1~ having sidewalls and defining a channel region in the underlying substrate; a sidewall insulator adjacent the sidewall of the goo 1~ disposed along the mormill region; an elevated moat region disposed between the sidewall insulator and the first insulator region; The first sidewall spacer is disposed adjacent the sidewall insulator and the raised moat region to further increase the surface distance between the moat region! transistor.

(10) In paragraph 9, the raised moat region further comprises a region adjacent to the first sidewall spacer, wherein the doped rigid layer in the region is doped with the doped material in the remaining region of the moat region. The transistor is different from the agent once.

(11) In paragraph 9, the ttf sidewall insulator has a thin sidewall insulator, and the dopant implanted through the raised moat region moves laterally within the substrate to form the raised moat region. the thin sidewall insulator has a thickness such that the thin sidewall insulator has a thickness such that the thin sidewall insulator has a thickness that is capable of electrically connecting a formed moat region to the f-t tunnel region and retaining a shallow junction within the substrate; transistor.

(12) The transistor according to item 11, wherein the thin sidewall insulator has a thickness of 900 Angus i[1-um or less.

(13) The transistor #F according to Item 9, further comprising a second sidewall smoother disposed adjacent to the first insulator region and the raised moat region.

(14) The transistor according to item 13, wherein the second sidewall spacer is made of an insulator.

15. The transistor of claim 9, wherein the raised moat region is comprised of epitaxial silicon.

(16) The transistor according to item 9, wherein the first sidewall spacer is made of an insulator.

(17) a semiconductor substrate; a first insulator region and a second insulator region disposed outwardly from the substrate to define a moat region therebetween; disposed outwardly from the mole region; and a gate having a sidewall and defining a channel region in the underlying substrate; and an IC gate disposed along the moat region and between the sidewall insulator and the first insulator region. a raised moat region; a raised moat region; a first sidewall spacer disposed adjacent to a moat region;

(18) The first helangistor according to item 17, wherein the first sidewall spacer is made of an insulator.

(19) In paragraph 17, having a thin sidewall insulator adjacent the sidewalls of the gate, and wherein dopants implanted through the raised moat region migrate laterally within the substrate. The thin sidewall insulator has a thickness such that the raised moat region can be electrically connected to the channel region and can maintain a shallow junction in the substrate. , the transistor.

(20) In the 18th wolf, the thickness of the thin insulator is 9
00 onges 1 ohm or less.

(21) In paragraph 17, a sidewall insulator adjacent to the sidewall of the goo 1 =, a second sidewall spacer disposed adjacent to the sidewall insulator and the raised moat region; The transistor further comprises:

(22) In paragraph 21, further comprising a region adjacent the first sidewall spacer in the raised moat region, wherein the dopant concentration in the region is lower than the remaining region of the upper region. 1.

(23) The i~ transistor according to item 21, wherein the second side wall is made of an insulator.

(24) Paragraph 17 of 43, wherein the raised mormill region comprises epitaxial silicon;
Helangista.

(25) a semiconductor substrate; a first insulator region and a second insulator region disposed outwardly from the substrate to define a region between them; and a first insulator region J and a second insulator region disposed outwardly from the moat region; a gate having sidewalls and defining a channel region in a substrate therebelow; a thin sidewall insulator adjacent the sidewalls of the gate; a raised moat region disposed between the body and the first insulator region; a first sidewall spacer disposed adjacent the thin sidewall insulator and the raised moat region; one insulator region and a second sidewall spacer disposed adjacent the raised moat region, wherein dopants implanted through the raised moat region migrate laterally within the substrate. and the thin sidewall insulator has a thickness such that the raised moat region can be electrically connected to the channel region and can maintain a shallow junction in the substrate.

(26) creating a first insulator region and a second insulator region disposed outwardly from the semiconductor substrate to define a moat region therebetween; , forming a gate having sidewalls and defining a channel region in the #substrate below; forming a thin sidewall insulator adjacent the sidewalls of the gate; and forming a thin sidewall insulator adjacent the sidewalls of the gate; forming a raised moat region disposed along the sidewall insulator and the first insulator region; and doping implanted through the raised moat region in the substrate. lateral movement within the substrate to electrically connect the raised moat region to the channel region and maintain a shallow bond within the substrate. creating the thin sidewall insulator.

(21) The method of claim 26, wherein the step of creating the moat region includes creating an epitaxy silicon.

28. The method of claim 26, further comprising creating a first sidewall spacer disposed adjacent the thin sidewall insulator and the raised moat region.

(29) The manufacturing method according to item 28, wherein the step of creating the first sidewall space υ- includes creating an insulator.

(30) The method of claim 26, further comprising the step of creating a second sidewall spacer disposed in v4 contact with the first insulator region and the raised moat region.

(31) The manufacturing method described in item 30, d5, wherein the step of creating the second sidewall spacer is the same as the step of creating an insulator.

(32) a3 in paragraph 28, wherein the dopant aiii in the raised moat region is adjacent to the first sidewall spacer and has a dopant concentration aiii 1 degree different from the dopant concentration in the remaining region of the moat region; The manufacturing method further comprises the step of creating one region.

(33) The method of claim 26, wherein said step of forming said thin sidewall insulator comprises the step of forming a sidewall insulation layer having a thickness of 900 mm or more. .

(34) The method of claim 26, further comprising the step of creating a joining region before the step of creating the raised moat region.

(35) The method of claim 26, further comprising the step of forming and covering a bonding area after the step of forming the raised moat area.

C36) 1 to transistor manufactured by the manufacturing method of item 26.

(37) Semiconductor j1 (first insulator region W for defining the TJ knee 1 region distributed outward from the board and between them)
i d3J: forming a second insulator region; creating a sidewall insulator adjacent to the sidewall of the goo 1~; disposed along the moat region and between the sidewall insulator and the first insulator region; creating a first sidewall spacer positioned adjacent the sidewall insulator and the raised moat area; A method for manufacturing a transistor structure in which E1 is attached to a semiconductor substrate.

(38) In paragraph 37, in the raised moat region adjacent to the first sidewall spacer and in which the dopant water droplets have a dopant concentration of 11n equal to the dopant concentration in the remaining region of the moat region. further comprising the step of creating a different region, 8;j;t[l! Manufacturing method.

(3) In paragraph 37, the step of creating the sidewall insulator comprises creating a thin sidewall insulator, and the dopant implanted through the raised moat region is in the substrate. The thin sidewall insulation has a thickness such that it can be moved laterally to electrically connect the raised moat 6J region to the channel region and maintain a shallow junction in the substrate. The above-mentioned manufacturing method, which the body has.

40. The method of claim 39, wherein said step of forming said thin sidewall insulator comprises forming said thin sidewall insulator having a thickness of 900 J Angstroms or less.

(41) In paragraph 37, a second
The manufacturing method described above generally includes the steps of creating a side wall smoother.

(42) The manufacturing method according to item 41, wherein the step of creating the second sidewall subaree further includes the step of creating an insulator.

(43) The method of claim 37, wherein the step of creating the raised moat region comprises the step of creating an epitaxial series.

(44) In paragraph 37, the step of creating the first side wall space 1y includes the step of creating an insulator.
The manufacturing method.

(45) The manufacturing method according to item 37, further comprising the step of creating a joining region after the step of creating the raised king-1 region.

(46) The manufacturing method described in item 37, further comprising the step of creating a bonding region after the step of creating and covering the raised region 1.

(47) A transistor manufactured by the manufacturing method of item 37.

(48) A first insulator region a5 disposed outward from the semiconductor top plate to define a Mo1 region therebetween;
and creating a gate located outwardly from the moat region and having sidewalls and defining a channel region in the M&therebelow; 7-1. Creating a narrowed mo[~ area] arranged along the area and between the side wall insulator and the first insulator area, and the first insulator area. and forming a first sidewall spacer disposed adjacent to the raised mormill region; and manufacturing a transistor structure associated with the semiconductor substrate, covering the semiconductor substrate.

(49) The method of claim 48, wherein the step of creating the first sidewall spacer includes creating an insulator.

(50) Clause 48, further comprising the step of forming a thin sidewall insulator adjacent to the sidewall of the gate;
and dopant implanted through the raised moat region moves laterally within the substrate to electrically connect the raised moat region to the channel region.
The thin sidewall insulator is formed to a thickness such that the thin sidewall insulator is capable of retaining shallow junctions within the substrate.

(51) The manufacturing method of Clause 48, wherein the step of creating the thin insulator includes the step of creating the thin insulator with a thickness of 900 angstroms or less.

(52) In paragraph 718, the side Q adjacent to the side wall of the goo 1~? The manufacturing method generally comprises the steps of: creating an insulator; and creating a second sidewall space disposed adjacent to the sidewall insulator and the raised moat region.

(53) The method of claim 52, wherein the step of creating the second sidewall spacer includes creating an insulator.

(54) In paragraph 48, the raised moat region is adjacent to the first sidewall spacer and the dopant therein is 1) dopant deep in the remaining region of the raised moat region. The nηJI co-manufacturing method further comprises the step of creating one region called Marado W.

(55) The method of claim 48, wherein the step of creating the raised moat region comprises the step of forming an epitaxial full silicon.

(56) The method of claim 48, further comprising the step of creating a bonding region before the step of creating the raised moat region.

(57) The method of claim 48, further comprising the step of creating and covering a bonding region after the step of creating the raised moat region.

(58) A transistor 1 to J manufactured by the manufacturing method of item 48.

(59) a seventh insulator Ki region and a second insulator disposed outwardly from the semiconductor substrate to define a moat region therebetween;
creating an insulator region; creating a gate disposed outwardly from the moat region and having sidewalls and defining a channel region in the substrate therebelow; creating a thin sidewall insulator adjacent a sidewall; and an elevated 'E' disposed along the moat region and between the sidewall insulator and the first insulator region.
-1 to create a region, and a dopant implanted through the raised moat region moves laterally into the substrate; -C electrically connects the raised moat region to the channel region; creating the thin sidewall insulator having a thickness such that the thin sidewall insulator can be attached to the substrate and retaining a shallow junction within the substrate; and adjacent the thin sidewall insulator and the raised moat region. creating a first sidewall spacer located adjacent to the first insulator region and the raised moat region; and creating a second sidewall spacer located adjacent the first insulator region and the raised moat region. 1-A method for manufacturing a transistor structure attached to the semiconductor substrate, comprising:

(60) l - raised lath/right side thin sidewall space insulator 54 adjacent to transistor gate 48;
You can get a drain, ], and a transistor. A first sidewall spacer 64 is positioned adjacent the thin sidewall spacing insulator 54 and the raised source/drain region 60 . Second
Sidewall spacers 66 are created at the interface between field insulator region 44 and raised source/drain region 60.

[Brief explanation of the drawing]

FIG. 1 shows a prior art raised source/drain
FIG. 1A is a cross-sectional view of an elevated source/drain transistor of the present invention; FIG.
Figure B is a drawing of the raised source/drain transistor of Figure 2Δ with raised source/drain regions and an initial thin sidewall spacing insulator; Figure 2C is a drawing of the raised source/drain transistor with the first sidewall spacer and a drawing of the raised source/drain transistor of FIG. 2A with a second sidewall spacing;
FIG. 2D is a drawing of the raised source/drain transistor of FIG. 2A showing the siriide contact regions and regions of different doping concentrations within the raised source/drain regions. Explanation of the number 1 42 Semiconductor substrate 44. 54 First insulator region, second insulator region 46
moat region 54 thin sidewall insulator 60 raised moat first sidewall spacer second sidewall spacer

Claims (2)

[Claims] (1) a semiconductor substrate; a first insulator region and a second insulator region disposed outwardly from the substrate to define a moat region therebetween; and a sidewall disposed outwardly from the moat region; and defining a channel region in the substrate therebelow; a thin sidewall insulator adjacent the sidewalls of the gate; and a thin sidewall insulator disposed along the moat region and defining a channel region in the substrate thereunder; a raised moat region disposed between the first insulator region and a dopant implanted through the raised moat region that moves laterally within the substrate to form the raised moat region; The thin sidewall insulator has a thickness such that the moat region can be electrically connected to the channel region and can maintain a shallow junction in the substrate. (2) creating a first insulator region and a second insulator region disposed outwardly from the semiconductor substrate to define a moat region therebetween; and a sidewall disposed outwardly from the moat region; and forming a thin sidewall insulator adjacent the sidewalls of the gate along the moat region. creating a raised moat region disposed and disposed between the sidewall insulator and the first insulator region; a dopant implanted through the raised moat region in the substrate; creating the thin sidewall insulator that can be moved laterally to electrically connect the raised moat region to the channel region and retain a shallow junction in the substrate; A method for manufacturing a transistor structure attached to the semiconductor substrate, comprising: