JP2006253300A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2006253300A
JP2006253300A JP2005065604A JP2005065604A JP2006253300A JP 2006253300 A JP2006253300 A JP 2006253300A JP 2005065604 A JP2005065604 A JP 2005065604A JP 2005065604 A JP2005065604 A JP 2005065604A JP 2006253300 A JP2006253300 A JP 2006253300A
Authority
JP
Japan
Prior art keywords
layer
formed
insulating film
source
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005065604A
Other languages
Japanese (ja)
Other versions
JP4945910B2 (en
Inventor
Atsushi Okuyama
奥山  敦
Original Assignee
Sony Corp
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, ソニー株式会社 filed Critical Sony Corp
Priority to JP2005065604A priority Critical patent/JP4945910B2/en
Publication of JP2006253300A publication Critical patent/JP2006253300A/en
Application granted granted Critical
Publication of JP4945910B2 publication Critical patent/JP4945910B2/en
Application status is Expired - Fee Related legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein an epitaxial layer is used to form an extension layer and a source drain layer and reliability is improved by preventing a joint leak between an alloy layer and a semiconductor substrate, and to provide its manufacturing method. <P>SOLUTION: An element isolation insulating film 2 partitioning an active area is formed on a semiconductor substrate 1, and a gate electrode 5 is formed on the semiconductor substrate 1 in an active area by means of a gate insulating film 4. Two extension layers 6 formed by using an epitaxial growth layer and two source drain layers 8 are stacked on the semiconductor substrate 1 on both sides of a gate electrode 5. A protection layer 9 is formed at the end on the side of the element isolation insulating film in the source drain layer 8 so as to prevent the formation of an alloy layer at the end thereof. An alloy layer 10 is formed on the source drain layer 8 exposed from the protection layer 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which an extension layer and a source / drain layer are formed by an epitaxial growth layer and a manufacturing method thereof.

  As transistor generation progresses, scaling by miniaturization is constantly performed. On the International Semiconductor Technology Roadmap (ITRS), a gate length (Lg) of 20 nm or less is expected in a transistor called hp (half pitch) 32 nm generation. For this generation of transistors, it is necessary to scale the effective thickness (EOT: Effective Oxide Thickness) of the gate insulating film and the depth (Xj) of the diffusion layer together with the gate length.

  The scaling of the effective thickness EOT of the gate insulating film is necessary for securing the driving capability (Ids), and the scaling of the depth Xj of the diffusion layer is necessary for suppressing the short channel effect (SCE). In particular, there are severe restrictions on the scaling of the diffusion layer depth Xj. In the case of forming a transistor with a gate length Lg of 20 nm or less, it is considered that the diffusion layer serving as an extension portion needs to be shallower than 5 nm.

  However, there are two main problems when trying to form this extremely shallow pn junction, that is, an ion implantation technique and an activation annealing technique have not been established at present. Even if it is assumed that the diffusion layer depth Xj of 5 nm can be realized, there arises a problem that the parasitic resistance generated increases due to the thinness.

Therefore, it is proposed that the extension part is lifted above the original silicon substrate surface, and the extension extension of the concept of lowering the resistance of the extension part while keeping the diffusion layer depth Xj below the silicon substrate shallow is proposed. (Raised Extension) structure. This technique has been proposed for a long time (see Non-Patent Document 1). In addition, a technique that defines an ideal structure such as formation of a diffusion layer and the shape of a lifting extension portion is disclosed (see Patent Document 1).
JP 2000-82813 A Nishimatsu et al., Groove Gate MOSFET, 8th Conf. On Solid State Device, pp.179-183, 1976

  When trying to realize the lift extension structure described above, one of the problems can be a junction leak generated between the silicide layer and the silicon substrate. In addition, it is expected that this problem will remarkably appear as the source / drain layers and extension layers become thinner due to miniaturization of transistors.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent junction leakage between an alloy layer and a semiconductor substrate in a semiconductor device in which an extension layer and a source / drain layer are formed by an epitaxial growth layer. An object of the present invention is to provide a semiconductor device with improved reliability and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device of the present invention is formed on a semiconductor substrate, and is formed with an element isolation insulating film partitioning an active region and a gate insulating film on the semiconductor substrate in the active region A gate electrode, two extension layers formed on the semiconductor substrate on both sides of the gate electrode and formed by an epitaxial growth layer, and two source layers formed on the two extension layers and formed by the epitaxial growth layer. A drain layer; a semiconductor-metal alloy layer formed on the source / drain layer; and an end of the source / drain layer on the element isolation insulating film side; And a protective layer for preventing formation.

  In the above-described semiconductor device of the present invention, the extension layer and the source / drain layer formed by the epitaxial growth layer are laminated on the semiconductor substrate on both sides of the gate electrode. The end portions on the element isolation insulating film side in the extension layer and the source / drain layer tend to be thinned. In the present invention, since the protective layer is formed at the end of the source / drain layer on the element isolation insulating film side, the formation of the alloy layer at the thinned end is prevented.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation insulating film that partitions an active region in a semiconductor substrate, and a step of forming a gate structure in the active region of the semiconductor substrate. And forming two extension layers by epitaxial growth on the semiconductor substrate excluding the region of the gate structure, and forming two source / drain layers by epitaxial growth on the two extension layers; A step of forming a protective layer at an end of each source / drain layer on the element isolation insulating film side, and a step of alloying an exposed surface of the source / drain layer to form an alloy layer of a semiconductor and a metal. Have.

  In the semiconductor device manufacturing method of the present invention, the extension layer and the source / drain layer are formed by epitaxial growth. The end portions on the element isolation insulating film side in the extension layer and the source / drain layer tend to be thinned. Therefore, in the present invention, after forming the source / drain layer, a protective layer is formed at the end of the source / drain layer on the element isolation insulating film side. This prevents the formation of the alloy layer on the thinned end in the subsequent alloy layer forming step.

  According to the present invention, in a semiconductor device in which an extension layer and a source / drain layer are formed by an epitaxial growth layer, it is possible to realize a semiconductor device with improved reliability by preventing junction leakage between the alloy layer and the semiconductor substrate. .

  Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. In this embodiment, an n-type MIS transistor will be described as an example with reference to the drawings. For the p-type MIS transistor, the following description is similarly applied by appropriately reversing the conductivity type.

(First embodiment)
FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment.

  For example, a semiconductor substrate 1 made of a silicon substrate is formed with an element isolation insulating film 2 made of, for example, STI (Shallow Trench Isolation) that partitions an active region. As a material for the semiconductor substrate 1, germanium (Ge), a compound of Ge and Si, or strained Si may be used in addition to silicon (Si).

  A p-type well 3 in which a channel inversion layer is formed is formed in an active region where the element isolation insulating film 2 is not formed. A gate electrode 5 is formed on the semiconductor substrate 1 via a gate insulating film 4.

  Two extension layers 6 made of a first epitaxial growth layer are formed on the semiconductor substrate 1 on both sides of the gate electrode 5. The extension layer 6 is n-type and functions as a part of the source or drain of the nMIS transistor.

  Each extension layer 6 has an inclined end face on the gate electrode 5 side. A gate insulating film 4 is formed on the inclined end face and the semiconductor substrate 1 therebetween, and a gate electrode 5 is formed thereon.

  The side surface of the gate electrode 5 is covered with a sidewall insulating film 7 formed on the extension layer 6. On the extension layer 6 not covered with the sidewall insulating film 7, an n-type source / drain layer 8 made of a second epitaxial growth layer is formed. The sidewall insulating film 7 is provided in order to ensure the distance between the gate electrode 5 and the source / drain layer 8.

  A protective layer 9 is formed at the end A of the extension layer 6 and the source / drain layer 8 on the element isolation insulating film 2 side. The protective layer 9 is made of, for example, silicon oxide or silicon nitride. In the present embodiment, the protective layer 9 is also formed on the sidewall of the sidewall insulating film 7.

  A silicide layer 10 is formed on the portion of the source / drain layer 8 exposed from the protective layer 9. The silicide layer 10 is an alloy layer of a silicon semiconductor constituting the source / drain layer 8 and a metal. The silicide layer 10 is made of, for example, cobalt silicide or nickel silicide. An alloy layer 11 is also formed on the upper surface of the gate electrode 5.

  An interlayer insulating film 12 is formed on the entire surface so as to cover the MIS transistor. Although not shown, contacts connected to the source / drain layers 8 are embedded in the interlayer insulating film 12, and wirings connected to the contacts are formed on the interlayer insulating film 12.

  The semiconductor device according to the present embodiment employs a so-called lifted extension structure in which an extension layer 6 made of an epitaxial growth layer is formed on a semiconductor substrate 1.

  In the above structure, the pn junction depth from the surface of the semiconductor substrate 1 can be reduced in a state where the thickness of the extension layer 6 is secured. Can be improved.

  In the semiconductor device described above, the extension layer 6 and the source / drain layer 8 covering the semiconductor substrate 1 are thinner than the other regions at the end A on the element isolation insulating film 2 side of the extension layer 6 and the source / drain layer 8. It tends to become. If the silicide layer 10 is formed at the end A and the silicide layer 10 reaches the semiconductor substrate 1, junction leakage occurs.

  In the present embodiment, since the protective layer 9 covering the sidewalls of the extension layer 6 and the source / drain layer 8 is formed at the end A, the formation of the silicide layer 10 at the end A is prevented. Therefore, the occurrence of junction leakage can be prevented, and a semiconductor device with improved reliability can be realized.

  Next, a method for manufacturing the semiconductor device will be described with reference to FIGS.

  First, as shown in FIG. 2A, an element isolation insulating film 2 for element isolation is formed on a semiconductor substrate 1 by using, for example, an STI technique.

  Next, as shown in FIG. 2B, a p-type impurity such as boron is ion-implanted into the semiconductor substrate 1, and after ion implantation for adjusting the threshold voltage as necessary, activation is performed. By performing annealing, the p-type well 3 is formed.

  Next, as shown in FIG. 3A, a silicon oxide film 21a having a thickness of about 0.1 to 5 nm is formed on the semiconductor substrate 1 by, eg, thermal oxidation. Subsequently, a polysilicon layer 22a having a thickness of about 100 nm to 200 nm is formed on the silicon oxide film 21a by, for example, a CVD (Chemical Vapor Deposition) method. Instead of the polysilicon layer 22a, an amorphous silicon layer or an amorphous silicon layer into which impurities are introduced may be formed.

  Next, as shown in FIG. 3B, for example, a silicon nitride film is deposited on the polysilicon layer 22a, and the silicon nitride film is processed by a lithography technique and an etching technique to form a hard mask having a pattern corresponding to the gate electrode. 23 is formed. The thickness of the hard mask 23 is selected from a range of 30 nm to 100 nm, for example.

  Next, as shown in FIG. 4A, the dummy gate 22 and the dummy gate insulating film 21 are formed by dry etching the polysilicon layer 22a and the silicon oxide film 21a using the hard mask 23 as an etching mask. Thereby, the dummy gate structure 20 including the dummy gate insulating film 21, the dummy gate 22, and the hard mask 23 is formed. The dummy gate structure 20 corresponds to the gate structure of the present invention.

  Next, as shown in FIG. 4B, after a silicon nitride film is deposited on the semiconductor substrate 1 by, for example, a CVD method so as to cover the dummy gate structure 20, anisotropic dry etching (etchback) is performed. ), The first sidewall spacer 24 is formed on the sidewall of the dummy gate structure 20. The thickness of the first sidewall spacer 24 is, for example, 1 to 10 nm.

Next, as shown in FIG. 5A, silicon in which an n-type impurity such as arsenic or phosphorus is mixed by epitaxial growth on the surface of the semiconductor substrate 1 exposed from the dummy gate structure 20 and the first sidewall spacer 24. An extension layer 6 made of a layer (first epitaxial growth layer) is formed. The material of the first epitaxial growth layer is, for example, a silicon single crystal or a mixed crystal of silicon and germanium. The impurity concentration at this time is, for example, 1 × 10 18 to 1 × 10 20 / cm 3 .

  Since this epitaxial growth is performed by a low-temperature process of 800 ° C. or less, impurities introduced during the growth hardly diffuse into the semiconductor substrate 1 (p-type well 3). A pn junction having a steep concentration gradient can be formed therebetween. Further, since the impurities are activated, it is not necessary to perform a heat treatment for activation in the subsequent steps, so that impurity diffusion into the semiconductor substrate 1 can be further suppressed. Thereby, the short channel effect of the transistor can be suppressed while the extension layer 6 having a low resistance is formed.

  An inclined end face is formed in the extension layer 6 on the dummy gate structure 20 side according to the growth conditions in the epitaxial growth. The angle (facet) formed by the inclined end surface with the substrate surface has a constant value in the range of 20 to 70 °. If this angle is too small, the parasitic resistance of the extension layer 6 increases. If the angle is too large, the parasitic capacitance between the gate electrode and the extension layer 6 increases, or the margin for overlapping the gate electrode and the inclined end surface decreases as will be described later. For this reason, this angle is preferably controlled within the above range.

  Next, as shown in FIG. 5B, the first sidewall spacer 24 made of, for example, silicon nitride is removed using heated phosphoric acid or the like.

  Next, as shown in FIG. 6A, after a silicon oxide film is deposited on the semiconductor substrate 1 by, for example, a CVD method so as to cover the dummy gate structure 20, anisotropic dry etching (etchback) is performed. ), The second sidewall spacer 25 is formed on the sidewall of the dummy gate structure 20. As the second sidewall spacer 25, a material such as a silicon oxide film having a high etching selectivity with respect to the hard mask 23 is used. The film thickness of the second sidewall spacer 25 defines a width in which the subsequent gate electrode overlaps the inclined surface of the extension layer 6, and is thus thicker than the first sidewall spacer 24. For example, the film thickness of the second sidewall spacer 25 is set in the range of 2 to 15 nm. The second sidewall spacer 25 may be formed without removing the first sidewall spacer 24. In this case, it is not always necessary to make the thickness of the second side wall spacer 25 thicker than that of the first side wall spacer 24.

  Next, as shown in FIG. 6B, after depositing, for example, a silicon nitride film on the extension layer 6 so as to cover the dummy gate structure 20, abnormal dry etching (etchback) is performed. The sidewall insulating films 7 are formed on both side surfaces of the dummy gate structure 20 via the second sidewall spacers 25. The sidewall insulating film 7 functions as an etching stopper when the second sidewall spacer 25 is etched later. For this reason, for example, a silicon nitride film is used as the material of the sidewall insulating film 7.

  Next, as shown in FIG. 7A, a source / drain composed of a silicon layer (second epitaxial growth layer) in which an n-type impurity such as arsenic or phosphorus is selectively mixed on the extension layer 6 by an epitaxial growth method. Layer 8 is formed. The material of the second epitaxial growth layer is, for example, a silicon single crystal or a mixed crystal of silicon and germanium.

  This epitaxial growth is performed by a low-temperature process of 800 ° C. or lower, similarly to the formation of the extension layer 6. For this reason, it is possible to prevent the impurities in the already formed extension layer 6 from being thermally diffused into the semiconductor substrate 1. Further, since the impurities in the source / drain layer 8 are activated, it is not necessary to perform a heat treatment for activation in the subsequent process, so that impurity diffusion into the semiconductor substrate 1 can be further suppressed. .

  Next, as shown in FIG. 7B, a protective layer 9 is formed on the source / drain layer 8 by, for example, a CVD method so as to cover the dummy gate structure 20. As the protective layer 9, for example, a silicon oxide film having an etching selectivity with respect to the hard mask 23 made of a silicon nitride film or the sidewall insulating film 7 is used.

  Next, as shown in FIG. 8A, the protective layer 9 is etched back by anisotropic dry etching to leave the protective layer 9 on the sidewalls of the extension layer 6 and the source / drain layer 8. In the method of the present embodiment, the protective layer 9 remains on the sidewall of the sidewall insulating film 7. As a result, the protective layer 9 is formed at the end A of the extension layer 6 and the source / drain layer 8 on the element isolation insulating film 2 side.

Next, as shown in FIG. 8B, the silicide layer 10 is formed in the portion of the source / drain layer 8 exposed from the protective layer 9. The silicide layer 10 is formed to lower the resistance of the source / drain layer 8, and is, for example, cobalt silicide (CoSi 2 ) or nickel silicide (NiSi 2 ). The silicide layer 10 is formed by forming a metal film made of cobalt or nickel and then heat-treating it, alloying a portion of the semiconductor material in contact with the metal film, and removing the unnecessary metal film by chemical treatment.

  Next, as shown in FIG. 9A, a silicon oxide film is deposited on the silicide layer 10 and the dummy gate structure 20 by, for example, a plasma CVD method to form an interlayer insulating film 12.

  Next, as shown in FIG. 9B, the interlayer insulating film 12 is etched back until the hard mask 23 is exposed. At this time, the upper part of the second sidewall spacer 25 made of silicon oxide is also slightly etched.

  Next, as shown in FIG. 10A, the hard mask 23 made of silicon nitride which is difficult to be etched and the upper portion of the sidewall insulating film 7 are removed by CMP. After CMP, a flat surface is formed.

  Next, as shown in FIG. 10B, the exposed dummy gate 22 is removed by etching to form a gate opening 26. More specifically, the dummy gate 22 is removed by wet etching with an alkaline solution such as a TMAH (tetramethylammonium hydroxide) aqueous solution or by dry etching.

  Next, as shown in FIG. 11A, the second sidewall spacer 25 and the dummy gate insulating film 21 in the gate opening 26 are removed by wet etching using, for example, a solution containing hydrofluoric acid. As a result, the surface of the p-type well 3 is exposed on the bottom surface of the gate opening 26. Further, the inclined end surface of the extension layer 6 is exposed at the bottom of the gate opening 26. At this time, the sidewall insulating film 7 functions as an etching stopper, and the exposed width of the inclined end surface is controlled to be constant.

Next, as shown in FIG. 11B, the gate insulating film 4 is formed on the interlayer insulating film 12 so as to cover the inner wall of the gate opening 26. Subsequently, a gate electrode layer 5 a is formed on the gate insulating film 4 so as to fill the gate opening 26. The gate insulating film 4 is a SiO 2 film formed by thermal oxidation, a SiON film formed by plasma nitriding, or a HfO 2 film formed by an ALD (Atomic Layer Deposition) method. As the gate electrode layer 5a, a metal layer containing Hf (N), Ta (N), Ti (N), W, or Ru is formed.

  Next, as shown in FIG. 12A, the excess gate electrode layer 5a and the gate insulating film 4 on the interlayer insulating film 12 are removed by, eg, CMP. As a result, the gate electrode 5 is formed in the gate opening 26 via the gate insulating film 4.

  Next, as shown in FIG. 12B, an alloy layer 11 is formed on the portion of the gate electrode 5 exposed from the interlayer insulating film 12 as necessary. The alloy layer 11 is formed by, for example, forming a metal film made of cobalt or nickel and then performing heat treatment, alloying the gate electrode material in contact with the metal film, and removing the unnecessary metal film by chemical treatment.

  In the subsequent steps, after the interlayer insulating film 12 is stacked, contacts connecting to the silicide layer 10 and the alloy layer 11 are formed, and the upper layer wiring is formed, thereby completing the semiconductor device.

  According to the method of manufacturing a semiconductor device according to the present embodiment, in the manufacture of a semiconductor device having a so-called lifted extension structure, the extension layer 6 and the source / drain layer 8 are formed after the extension layer 6 and the source / drain layer 8 are formed. A protective layer 9 is formed on the end A on the element isolation insulating film 2 side, and then a silicide layer 10 is formed on the source / drain layer 8.

  In particular, in the present embodiment, the end portion A of the extension layer 6 and the source / drain layer 8 on the element isolation insulating film 2 side, more specifically, the side wall of the extension layer 6 and the source / drain layer 8 on the element isolation insulating film 2 side. Then, the protective layer 9 is formed in a self-aligning manner by depositing and etching back the protective layer material.

  By forming the protective layer 9 at the end A where the extension layer 6 and the source / drain layer 8 tend to be thinned, junction leakage between the silicide layer 10 and the semiconductor substrate 1 at the end A is prevented. Thus, a semiconductor device with improved reliability can be manufactured.

(Second Embodiment)
FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment. In addition, the same code | symbol is attached | subjected to the component similar to 1st Embodiment, The description is abbreviate | omitted.

  As in the first embodiment, a protective layer 9 a is formed at the end portions of the extension layer 6 and the source / drain layer 8 on the element isolation insulating film 2 side. The protective layer 9a is made of, for example, silicon oxide or silicon nitride. In the present embodiment, unlike the first embodiment, a protective layer is not formed on the sidewall of the sidewall insulating film 7.

  A silicide layer 10 is formed on the portion of the source / drain layer 8 exposed from the protective layer 9a. The silicide layer 10 is an alloy layer of a silicon semiconductor constituting the source / drain layer 8 and a metal. The silicide layer 10 is made of, for example, cobalt silicide or nickel silicide.

  In the semiconductor device according to the present embodiment, the protective layer 9 a that covers the sidewalls of the extension layer 6 and the source / drain layer 8 is formed at the end A of the extension layer 6 and the source / drain layer 8. Formation of the silicide layer 10 in the portion A is prevented. For this reason, there can exist the same effect as a 1st embodiment.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. This embodiment is different from the first embodiment only in the method for forming the protective layer.

  First, in the same manner as in the first embodiment, the extension layer 6 and the source / drain layer 8 are formed through the steps from FIG. 2 to FIG.

  Next, as shown in FIG. 14A, a protective layer 9a is formed on the source / drain layer 8 so as to cover the dummy gate structure 20 by, for example, a CVD method. As the protective layer 9a, for example, a silicon oxide film having an etching selectivity with respect to the hard mask 23 made of a silicon nitride film or the sidewall insulating film 7 is used.

  Next, as shown in FIG. 14B, a mask layer 27 is formed on the protective layer 9a at the end A of the source / drain layer 8 by lithography. The mask layer 27 may be a resist mask or a hard mask.

  Next, as shown in FIG. 15A, the mask layer 27 is used as an etching mask, the protective layer 9a is etched, and then the mask layer 27 is removed so that only the side walls of the extension layer 6 and the source / drain layer 8 are removed. Then, the protective layer 9a is formed. Thereby, the protective layer 9a is formed at the end A on the side of the element isolation insulating film 2 in the sidewall insulating film 7 and the source / drain layer 8.

Next, as shown in FIG. 15B, the silicide layer 10 is formed in the portion of the source / drain layer 8 exposed from the protective layer 9a. The silicide layer 10 is formed to lower the resistance of the source / drain layer 8, and is, for example, cobalt silicide (CoSi 2 ) or nickel silicide (NiSi 2 ). The silicide layer 10 is formed by forming a metal film made of cobalt or nickel and then heat-treating it, alloying a portion of the semiconductor material in contact with the metal film, and removing the unnecessary metal film by chemical treatment.

  As the subsequent steps, as in the first embodiment, the semiconductor device is completed through the steps shown in FIGS.

  In the method of manufacturing a semiconductor device according to the present embodiment, the protective layer 9a is formed by etching using the mask layer 27 at the end A on the element isolation insulating film 2 side in the extension layer 6 and the source / drain layer 8. Later, a silicide layer 10 is formed on the source / drain layer 8.

  Therefore, as in the first embodiment, the occurrence of junction leakage between the silicide layer 10 and the semiconductor substrate 1 at the end A can be prevented, and a semiconductor device with improved reliability can be manufactured. .

(Third embodiment)
FIG. 16 is a cross-sectional view of the semiconductor device according to the present embodiment. In addition, the same code | symbol is attached | subjected to the component similar to 1st Embodiment, The description is abbreviate | omitted.

  In the present embodiment, a protective layer 9 b is formed at the end A of the extension layer 6 and the source / drain layer 8 on the element isolation insulating film 2 side. In the present embodiment, the protective layer 9 b is constituted by a region in which the end portions A of the extension layer 6 and the source / drain layer 8 are insulated.

  A silicide layer 10 is formed on the exposed surface of the source / drain layer 8 other than the region where the protective layer 9b is formed. The silicide layer 10 is an alloy layer of a silicon semiconductor constituting the source / drain layer 8 and a metal. The silicide layer 10 is made of, for example, cobalt silicide or nickel silicide.

  In the semiconductor device according to the present embodiment, the protective layer 9b in which the extension layer 6 and the source / drain layer 8 are insulated is formed at the end A of the extension layer 6 and the source / drain layer 8. Formation of the silicide layer 10 in the portion A is prevented. For this reason, there can exist the same effect as a 1st embodiment.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. This embodiment is different from the first embodiment only in the method for forming the protective layer.

  First, in the same manner as in the first embodiment, the extension layer 6 and the source / drain layer 8 are formed through the steps from FIG. 2 to FIG.

  Next, as shown in FIG. 17A, a mask layer 28 that covers the regions other than the end portion A of the extension layer 6 and the source / drain layer 8 and exposes the end portion A is formed by lithography. The mask layer 28 may be either a resist mask or a hard mask.

  Next, as shown in FIG. 17B, the portions of the source / drain layer 8 and the extension layer 6 exposed from the mask layer 28 are oxidized or nitrided to form a protective layer 9b made of silicon oxide or silicon nitride. To do. Note that treatment other than oxidation or nitridation may be used as long as silicon as an epitaxial growth layer can be insulated. Thereafter, as shown in FIG. 18A, the mask layer 28 is removed.

Next, as shown in FIG. 18B, a silicide layer 10 is formed in a portion of the source / drain layer 8 other than the formation region of the protective layer 9b. The silicide layer 10 is formed to lower the resistance of the source / drain layer 8, and is, for example, cobalt silicide (CoSi 2 ) or nickel silicide (NiSi 2 ). The silicide layer 10 is formed by forming a metal film made of cobalt or nickel and then heat-treating it, alloying a portion of the semiconductor material in contact with the metal film, and removing the unnecessary metal film by chemical treatment.

  As the subsequent steps, as in the first embodiment, the semiconductor device is completed through the steps shown in FIGS.

  In the manufacturing method of the semiconductor device according to the above-described embodiment, the end layer A on the element isolation insulating film 2 side in the extension layer 6 and the source / drain layer 8 is protected by a selective insulating process using the mask layer 28. After forming the layer 9 b, the silicide layer 10 is formed on the source / drain layer 8.

  Therefore, as in the first embodiment, the occurrence of junction leakage between the silicide layer 10 and the semiconductor substrate 1 at the end A can be prevented, and a semiconductor device with improved reliability can be manufactured. .

The present invention is not limited to the description of the above embodiment.
Various changes can be made to the steps before and after the formation of the protective layers 9, 9a, 9b. For example, in this embodiment, since a metal gate is employed, the dummy gate structure 20 is formed as a gate structure and then removed. However, when a polysilicon gate is employed, the dummy gate insulating film 21 and the dummy gate are used. 22 can be used as it is as a gate insulating film and a gate electrode. Further, when a metal gate is adopted as the gate electrode 5, the alloy layer 11 is not necessary.

In the present embodiment, the example in which the overlap amount between the inclined end surface of the extension layer 6 and the gate electrode 5 is controlled using the first sidewall spacer 24 and the second sidewall spacer 25 has been described. These layers may be omitted.
In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing which shows an example of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 3rd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 3rd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... P-type well, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Extension layer, 7 ... Side wall insulating film, 8 ... Source-drain layer, 9, 9a, 9b ... protective layer, 10 ... silicide layer, 11 ... alloy layer, 12 ... interlayer insulating film, 20 ... dummy gate structure, 21 ... dummy gate insulating film, 21a ... silicon oxide film, 22 ... dummy gate, 22a ... Polysilicon layer, 23 ... hard mask, 24 ... first sidewall spacer, 25 ... second sidewall spacer, 26 ... gate opening, 27 ... mask layer, 28 ... mask layer

Claims (5)

  1. An element isolation insulating film formed on a semiconductor substrate and defining an active region;
    A gate electrode formed on the semiconductor substrate in the active region via a gate insulating film;
    Two extension layers stacked on the semiconductor substrate on both sides of the gate electrode and formed by an epitaxial growth layer;
    Two source / drain layers stacked on the two extension layers and formed by an epitaxial growth layer;
    An alloy layer of a semiconductor and a metal formed on the source / drain layer;
    And a protective layer that is formed at an end portion of the source / drain layer on the element isolation insulating film side and prevents the formation of the alloy layer at the end portion.
  2. A sidewall insulating film covering the side surface of the gate electrode is formed on the extension layer,
    The semiconductor device according to claim 1, wherein the protective layer is formed of a material different from that of the sidewall insulating film.
  3. Forming an element isolation insulating film for partitioning an active region on a semiconductor substrate;
    Forming a gate structure in an active region of the semiconductor substrate;
    Forming two extension layers by epitaxial growth on the semiconductor substrate excluding the region of the gate structure;
    Forming two source / drain layers by epitaxial growth on the two extension layers;
    Forming a protective layer at an end of each source / drain layer on the element isolation insulating film side;
    Alloying exposed surfaces of the source / drain layers to form an alloy layer of a semiconductor and a metal.
  4. After the step of forming the extension layer and before the step of forming the source / drain layer, the method further includes a step of forming a sidewall insulating film on the sidewall of the gate structure,
    The method for manufacturing a semiconductor device according to claim 3, wherein in the step of forming the protective layer, a protective layer made of a material different from that of the sidewall insulating film is formed.
  5. The gate structure is a dummy gate structure;
    After the step of forming the alloy layer,
    Forming an interlayer insulating film exposing an upper surface of the gate structure;
    Removing the gate structure to form a gate opening exposing the semiconductor substrate;
    Forming a gate insulating film on the semiconductor substrate in the gate opening;
    The method of manufacturing a semiconductor device according to claim 3, further comprising: forming a gate electrode that fills the gate opening.
JP2005065604A 2005-03-09 2005-03-09 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4945910B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005065604A JP4945910B2 (en) 2005-03-09 2005-03-09 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005065604A JP4945910B2 (en) 2005-03-09 2005-03-09 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2006253300A true JP2006253300A (en) 2006-09-21
JP4945910B2 JP4945910B2 (en) 2012-06-06

Family

ID=37093478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005065604A Expired - Fee Related JP4945910B2 (en) 2005-03-09 2005-03-09 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4945910B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009308A (en) * 2009-06-23 2011-01-13 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
EP3080844A4 (en) * 2013-12-12 2017-07-12 Texas Instruments Incorporated Forming silicide and contact at embedded epitaxial facet

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02222153A (en) * 1988-12-22 1990-09-04 Texas Instr Inc <Ti> Raised source-drain-transistor and its manufacturing method
JPH0786579A (en) * 1993-09-14 1995-03-31 Toshiba Corp Semiconductor device
JPH10135453A (en) * 1996-10-28 1998-05-22 Sharp Corp Semiconductor device and its manufacture
JPH10214967A (en) * 1997-01-30 1998-08-11 Nec Corp Manufacture of semiconductor device
JPH11354784A (en) * 1998-06-08 1999-12-24 Sony Corp Manufacture of mis field effect transistor
JP2000216386A (en) * 1999-01-25 2000-08-04 Internatl Business Mach Corp <Ibm> Fabrication of semiconductor device having junction
JP2000223703A (en) * 1999-01-29 2000-08-11 Toshiba Corp Semiconductor device and its manufacture

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02222153A (en) * 1988-12-22 1990-09-04 Texas Instr Inc <Ti> Raised source-drain-transistor and its manufacturing method
JPH0786579A (en) * 1993-09-14 1995-03-31 Toshiba Corp Semiconductor device
JPH10135453A (en) * 1996-10-28 1998-05-22 Sharp Corp Semiconductor device and its manufacture
JPH10214967A (en) * 1997-01-30 1998-08-11 Nec Corp Manufacture of semiconductor device
JPH11354784A (en) * 1998-06-08 1999-12-24 Sony Corp Manufacture of mis field effect transistor
JP2000216386A (en) * 1999-01-25 2000-08-04 Internatl Business Mach Corp <Ibm> Fabrication of semiconductor device having junction
JP2000223703A (en) * 1999-01-29 2000-08-11 Toshiba Corp Semiconductor device and its manufacture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009308A (en) * 2009-06-23 2011-01-13 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
EP3080844A4 (en) * 2013-12-12 2017-07-12 Texas Instruments Incorporated Forming silicide and contact at embedded epitaxial facet
US9812452B2 (en) 2013-12-12 2017-11-07 Texas Instruments Incorporated Method to form silicide and contact at embedded epitaxial facet
US10008499B2 (en) 2013-12-12 2018-06-26 Texas Instruments Incorporated Method to form silicide and contact at embedded epitaxial facet

Also Published As

Publication number Publication date
JP4945910B2 (en) 2012-06-06

Similar Documents

Publication Publication Date Title
JP4493536B2 (en) Semiconductor device and manufacturing method thereof
US7714394B2 (en) CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
US7303965B2 (en) MIS transistor and method for producing same
JP4773182B2 (en) Manufacturing method of semiconductor device
US6642581B2 (en) Semiconductor device comprising buried channel region
KR101637718B1 (en) Fin structure of semiconductor device
US6992358B2 (en) Semiconductor device and method for manufacturing the same
JP2007207837A (en) Semiconductor device, and method of manufacturing same
JP2005252268A (en) Manufacturing method of semiconductor device having burried oxide film, and semiconductor device having the burried oxide film
US8030708B2 (en) Insulated gate field-effect transistor
JP2005209782A (en) Semiconductor device
US7719043B2 (en) Semiconductor device with fin-type field effect transistor and manufacturing method thereof.
JP3998893B2 (en) Method for forming T-type element isolation film
CN100481505C (en) Semiconductor device and method for manufacturing the same
US7622770B2 (en) Semiconductor device having a trench gate and method of fabricating the same
TWI383490B (en) Method of manufacturing semiconductor device
JP5326274B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2007520891A (en) Method for forming a semiconductor device with local SOI
JP2007134674A (en) Semiconductor device and its manufacturing method
US20070108514A1 (en) Semiconductor device and method of fabricating the same
JP2009010111A (en) Semiconductor device and method for manufacturing semiconductor device
JP2005072577A (en) High integration semiconductor device provided with silicide film capable of assuring contact margin, and manufacturing method therefor
US7652328B2 (en) Semiconductor device and method of manufacturing the same
KR100844933B1 (en) Transistor in semiconductor device and method for manufacturing the same
US6017801A (en) Method for fabricating field effect transistor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070831

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090319

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110517

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110707

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111115

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111227

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120207

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120220

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150316

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150316

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees