JPH0221927U - - Google Patents
Info
- Publication number
- JPH0221927U JPH0221927U JP10067188U JP10067188U JPH0221927U JP H0221927 U JPH0221927 U JP H0221927U JP 10067188 U JP10067188 U JP 10067188U JP 10067188 U JP10067188 U JP 10067188U JP H0221927 U JPH0221927 U JP H0221927U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- clock pulse
- inverter
- base
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案によるクロツクパルス整形回路
の実施例を示す回路図、第２図は第１図の動作を
説明するための波形図、第３図は従来のクロツク
パルス整形回路の回路図である。
１……クロツクパルス入力端子、２，３……ト
ランジスタ、４……エミツタ抵抗、５……基準電
圧、６……コレクタ抵抗、７……レベルシフト用
トランジスタ、８……エミツタ抵抗、９……クロ
ツクパルス出力端子、１０……電源入力端子、１
１……反転器、１２……演算増幅器、１３……帰
還抵抗器、１４……コンデンサ、１５，１６……
抵抗器、１７……バイパスコンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of a clock pulse shaping circuit according to the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram of a conventional clock pulse shaping circuit. 1...Clock pulse input terminal, 2, 3...Transistor, 4...Emitter resistance, 5...Reference voltage, 6...Collector resistance, 7...Level shift transistor, 8...Emitter resistance, 9...Clock pulse Output terminal, 10...Power input terminal, 1
1... Inverter, 12... Operational amplifier, 13... Feedback resistor, 14... Capacitor, 15, 16...
Resistor, 17...Bypass capacitor.
Claims (1)
ツクパルスを入力し、第２トランジスタのベース
に基準電圧を入力することにより、前記クロツク
パルスのレベルを識別し、前記第２トランジスタ
のコレクタに第３トランジスタのベースを接続す
ることにより前記第３トランジスタのエミツタよ
り前記識別されたクロツクパルスを同相にレベル
シフトしてデユーテイ比５０％のクロツクパルス
整形波形を得るクロツクパルス整形回路において
、前記第３トランジスタのエミツタ出力を反転す
る反転器と、前記反転器出力の平均値を求め、こ
の平均値と第２基準電圧との誤差を検出し、この
誤差に対応の出力を前記第２トランジスタに加え
られる基準電圧として前記第２トランジスタのベ
ースに与える演算増幅器とを設け、前記反転器出
力よりデユーテイ比５０％の整形クロツクパルス
を得ることを特徴とするクロツクパルス整形回路
。 By inputting a clock pulse to the base of the first transistor of the differential amplifier and inputting a reference voltage to the base of the second transistor, the level of the clock pulse is identified, and the base of the third transistor is input to the collector of the second transistor. an inverter for inverting the emitter output of the third transistor in a clock pulse shaping circuit which level-shifts the identified clock pulse from the emitter of the third transistor to the same phase to obtain a clock pulse shaping waveform with a duty ratio of 50%; Then, an average value of the output of the inverter is determined, an error between this average value and a second reference voltage is detected, and an output corresponding to this error is used as a reference voltage to be applied to the second transistor at the base of the second transistor. 1. A clock pulse shaping circuit, comprising: an operational amplifier for supplying a signal to the inverter, and obtaining a shaped clock pulse with a duty ratio of 50% from the output of the inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10067188U JPH0221927U (en) | 1988-07-29 | 1988-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10067188U JPH0221927U (en) | 1988-07-29 | 1988-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221927U true JPH0221927U (en) | 1990-02-14 |
Family
ID=31328956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10067188U Pending JPH0221927U (en) | 1988-07-29 | 1988-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221927U (en) |
-
1988
- 1988-07-29 JP JP10067188U patent/JPH0221927U/ja active Pending
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