JPH0221613B2 - - Google Patents
Info
- Publication number
- JPH0221613B2 JPH0221613B2 JP57172103A JP17210382A JPH0221613B2 JP H0221613 B2 JPH0221613 B2 JP H0221613B2 JP 57172103 A JP57172103 A JP 57172103A JP 17210382 A JP17210382 A JP 17210382A JP H0221613 B2 JPH0221613 B2 JP H0221613B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- instruction
- address
- status word
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003672 processing method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 1
- 238000010977 unit operation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Devices For Executing Special Programs (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17210382A JPS5971550A (ja) | 1982-09-30 | 1982-09-30 | 命令処理方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17210382A JPS5971550A (ja) | 1982-09-30 | 1982-09-30 | 命令処理方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5971550A JPS5971550A (ja) | 1984-04-23 |
JPH0221613B2 true JPH0221613B2 (zh) | 1990-05-15 |
Family
ID=15935597
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17210382A Granted JPS5971550A (ja) | 1982-09-30 | 1982-09-30 | 命令処理方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5971550A (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2637770B2 (ja) * | 1988-05-25 | 1997-08-06 | 日本電気株式会社 | マイクロコンピュータ |
JP2715967B2 (ja) * | 1995-03-15 | 1998-02-18 | 日本電気株式会社 | マイクロコンピュータ |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621237A (en) * | 1979-07-30 | 1981-02-27 | Fujitsu Ltd | Information processor |
JPS56124952A (en) * | 1980-02-20 | 1981-09-30 | Fujitsu Ltd | Information processing equipment |
-
1982
- 1982-09-30 JP JP17210382A patent/JPS5971550A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621237A (en) * | 1979-07-30 | 1981-02-27 | Fujitsu Ltd | Information processor |
JPS56124952A (en) * | 1980-02-20 | 1981-09-30 | Fujitsu Ltd | Information processing equipment |
Also Published As
Publication number | Publication date |
---|---|
JPS5971550A (ja) | 1984-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI407366B (zh) | 具有微代碼之微處理器、在微處理器中儲存資料的方法、以及使用於計算裝置之電腦程式產品 | |
JPS6122331B2 (zh) | ||
JPH0430053B2 (zh) | ||
JPH03129433A (ja) | 並列処理装置および並列処理方法 | |
JPH04329435A (ja) | 異なるアーキテクチヤのインストラクシヨンを処理するコンピユータ及びその結果の通信方法 | |
JPS61290570A (ja) | ベクトル処理方法 | |
JPH0326414B2 (zh) | ||
JPH0766365B2 (ja) | コ・プロセツサ制御方式 | |
US5442769A (en) | Processor having general registers with subdivisions addressable in instructions by register number and subdivision type | |
JPH0380336A (ja) | 二重オペレーティングシステム計算機の動作強化装置のmバイト命令ワードcpuの動作強化装置及びレジスタ指向型アーキテクチュアcpuの動作強化装置 | |
US5446865A (en) | Processor adapted for sharing memory with more than one type of processor | |
EP1039376B1 (en) | Sub-instruction emulation in a VLIW processor | |
JP6882320B2 (ja) | ベクトル命令の処理 | |
JPH0221613B2 (zh) | ||
US5327537A (en) | Apparatus for controlling instruction execution in a pipelined processor | |
JPH0192843A (ja) | データ処理装置 | |
JPH0512751B2 (zh) | ||
US5278959A (en) | Processor usable as a bus master or a bus slave | |
JP3520372B2 (ja) | メモリ制御ユニット並びに入出力制御ユニットの動作におけるクリティカル・パスの削除 | |
JP2798275B2 (ja) | 仮想記憶アドレス空間アクセス制御方式 | |
JP3490191B2 (ja) | 計算機 | |
JPH0754468B2 (ja) | 仮想計算機システム | |
JP2883488B2 (ja) | 命令処理装置 | |
Groote et al. | An elementary processor | |
JPS61267135A (ja) | デ−タ処理装置 |