JPH02214311A - Oscillating circuit for microcomputer - Google Patents

Oscillating circuit for microcomputer

Info

Publication number
JPH02214311A
JPH02214311A JP3542689A JP3542689A JPH02214311A JP H02214311 A JPH02214311 A JP H02214311A JP 3542689 A JP3542689 A JP 3542689A JP 3542689 A JP3542689 A JP 3542689A JP H02214311 A JPH02214311 A JP H02214311A
Authority
JP
Japan
Prior art keywords
logic circuit
circuit
oscillation
logic
microcomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3542689A
Other languages
Japanese (ja)
Inventor
Hiroshi Hayaoka
洋 早岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3542689A priority Critical patent/JPH02214311A/en
Publication of JPH02214311A publication Critical patent/JPH02214311A/en
Pending legal-status Critical Current

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  • Oscillators With Electromechanical Resonators (AREA)

Abstract

PURPOSE:To reduce a signal leaked to the outside of a microcomputer and to reduce spurious radiation by providing a logic circuit with a high gain and a logic circuit with a low gain and applying switching control at application of power and after the stable oscillation. CONSTITUTION:The title circuit consists of a feedback amplifier comprising a crystal oscillator 1, a 1st logic circuit 4 made up of an inverter with a high gain and a 2nd logic circuit 5 made up of an inverter with a low gain, and of a phase detection control circuit 8 applying switching control to the 2nd logic circuit 5 in response to the phase of an oscillated signal 8. Then the oscillator 1, a feedback resistor 2 and a capacitor 3 are mounted externally to a CPU 10 and the logic circuits 4, 5 and the phase detection control circuit 6 are built in the inside of a CPU 10. The logic circuits 4, 5 are used at application of power to oscillate the oscillator 1 and the oscillation of the logic circuit 4 with high gain is stopped by the control circuit 6 after the stabilized oscillation and the oscillated element 1 is oscillated with the logic circuit 5 with a low gain only. As a result, the signal leaked to the outside of the CPU 10 is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマイクロコンピュータを利用した各種コンピュ
ータ機器のクロックパルス発生器として用いられる発振
回路に関し、特にその発振回路から不要輻射として外部
に漏れる信号を少なくしたマイクロコンピュータの発振
回路に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an oscillation circuit used as a clock pulse generator for various computer equipment using a microcomputer, and in particular to a method for eliminating signals leaking to the outside as unnecessary radiation from the oscillation circuit. This relates to a reduced oscillation circuit for a microcomputer.

〔従来の技術〕[Conventional technology]

従来、マイクロコンピュータにおいてクロックパルス発
布器として用いられている発振回路の一例を第3図に示
して説明する。この発振回路は、第3図に示すように、
水晶の発振子1と1、帰還抵抗2と、コンデンサ3及び
帰還増幅器としてのインバータなどのロジック回路11
から成り、そのロジック回路11をマイクロコンピュー
タ(以下、cpUともいう)10内に内蔵せしめる。そ
して、CPUl0に電源が供給されると、ロジック回路
11にも電源が供給され、帰還抵抗2とコンデンサ3を
介して発振子1が振動を開始することにより、その固有
振動数で発振を行なうものと々っている。
An example of an oscillation circuit conventionally used as a clock pulse generator in a microcomputer will be described with reference to FIG. This oscillation circuit, as shown in Figure 3,
A logic circuit 11 including crystal oscillators 1 and 1, a feedback resistor 2, a capacitor 3, and an inverter as a feedback amplifier.
The logic circuit 11 is built into a microcomputer (hereinafter also referred to as CPU) 10. When power is supplied to the CPU10, power is also supplied to the logic circuit 11, and the oscillator 1 starts oscillating via the feedback resistor 2 and capacitor 3, thereby oscillating at its natural frequency. It's so hot.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、このような従来の回路は、既に決められた利得
のロジック回路11で発振子lを発振させるようになっ
ているので、CPUl0の外部に漏れる信号を少なくす
ることができないという問題点があった。
However, in such a conventional circuit, since the oscillator 1 is caused to oscillate by the logic circuit 11 with a predetermined gain, there is a problem in that it is not possible to reduce the signal leaking to the outside of the CPU 10. Ta.

本発明はかかる問題点を解決するためになされたもので
、発振回路から外部に漏れる信号を少なくして不要輻射
の軽減を図ったマイクロコンピュータの発振回路を提供
することを目的とする。
The present invention has been made to solve these problems, and an object of the present invention is to provide an oscillation circuit for a microcomputer that reduces unnecessary radiation by reducing signals leaking from the oscillation circuit to the outside.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的を達成するため、本発明に係るマイクロコン
ピュータの発振回路は、帰還増幅器を利得の高い第1ロ
ジツク回路と利得の低い第2ロジツク回路から構成して
、これら第1ロジツク回路。
In order to achieve the above object, the oscillation circuit for a microcomputer according to the present invention includes a feedback amplifier consisting of a first logic circuit with a high gain and a second logic circuit with a low gain.

第2ロジツク回路を電源投入時と発振安定後とで切換え
制御するようにしたものである。
The second logic circuit is switched and controlled between when the power is turned on and after the oscillation is stabilized.

〔作用〕[Effect]

したがって、本発明においては、電源投入時に高利得で
発振を行ない、発振安定後は低利得で発振を行なうこと
により、定常時におけるマイクロコンピュータの外部に
漏れる信号を少なくすることが可能となる。
Therefore, in the present invention, by performing oscillation with a high gain when the power is turned on, and performing oscillation with a low gain after the oscillation stabilizes, it is possible to reduce signals leaking to the outside of the microcomputer during normal operation.

〔実施例〕 以下、本発明を図面に示す実施例に基づいて詳細に説明
する。
[Example] Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

第1図は本発明による発振回路の一実施例を示すブロッ
ク構成図である。この実施例の発振回路は、水晶の発振
子1と、利得の高いインバータなどの第1ロジツク回路
4及び利得の低いインバータなどの第2ロジツク回路5
から成る帰還増幅器と、これら第1ロジツク回路4.第
2ロジツク回路5を発振信号8の位相に応じて切換え制
御するための位相検出制御回路6から構成されている。
FIG. 1 is a block diagram showing an embodiment of an oscillation circuit according to the present invention. The oscillation circuit of this embodiment includes a crystal oscillator 1, a first logic circuit 4 such as a high gain inverter, and a second logic circuit 5 such as a low gain inverter.
a feedback amplifier consisting of these first logic circuits 4. It is comprised of a phase detection control circuit 6 for switching and controlling the second logic circuit 5 in accordance with the phase of the oscillation signal 8.

ただし、この例では、発振子1.帰還抵抗2.コンデン
サ3はcp[Jloに外付けされ、第1ロジツク回路4
.第2ロジツク回路52位相検出制御回路6はCPUl
0内部に内蔵されている。なお、第1図において9は位
相検出制御回路6から送出される各ロジック回路4,5
を制御するための制御信号を示し、また、図中同一符号
は同一または相当部分を示している。
However, in this example, oscillator 1. Feedback resistance 2. The capacitor 3 is externally connected to cp[Jlo, and is connected to the first logic circuit 4.
.. The second logic circuit 52 phase detection control circuit 6 is connected to the CPU1
Built-in internally. In FIG. 1, reference numeral 9 indicates each logic circuit 4, 5 sent from the phase detection control circuit 6.
The same reference numerals in the drawings indicate the same or corresponding parts.

このように構成された発振回路によると、利得の高い第
1ロジツク回路4と利得の低い第2ロジツク回路5及び
それらを制御する位相検出制御回路6を用いることによ
り、例えば、電源投入時に両者のロジック回路4,5を
使用して発振子1を発振させ、その発振安定後に制御回
路6により利得の高い第1ロジツク回路4の発振を止め
、利得の低い第2ロジツク回路5のみで発振子1を発振
させることができる。その結果、CPUl0の外部へ漏
れる信号を少なくすることが可能となる。
According to the oscillation circuit configured in this way, by using the first logic circuit 4 with a high gain, the second logic circuit 5 with a low gain, and the phase detection control circuit 6 that controls them, for example, when the power is turned on, both The oscillator 1 is made to oscillate using the logic circuits 4 and 5, and after the oscillation stabilizes, the control circuit 6 stops the oscillation of the first logic circuit 4 with a high gain, and the oscillator 1 is made to oscillate using only the second logic circuit 5 with a low gain. can be made to oscillate. As a result, it is possible to reduce the amount of signals leaking to the outside of the CPU10.

第2図は本発明の別の実施例を示すもので、第1図との
異なる点は、利得の高い第1ロジツク回路4としてゲー
ト素子7を外付けしたものを用い、このゲート素子7を
位相検出制御回路6の制御信号9によシ制御するように
したことである。この実施例においても、第1図と同様
に、電源投入時に両者のロジック回路4,5を用いて発
振子1を発振させ、発振安定後にゲート素子7をオフ制
御せしめて利得の高い第1ロジツク回路4の発振を止め
ることによシ、利得の低い第2ロジツク回路5のみで発
振子1を発振させることができる。
FIG. 2 shows another embodiment of the present invention, and the difference from FIG. 1 is that a gate element 7 is externally attached as the first logic circuit 4 with a high gain; The control is performed using the control signal 9 of the phase detection control circuit 6. In this embodiment as well, as in FIG. 1, when the power is turned on, both logic circuits 4 and 5 are used to cause the oscillator 1 to oscillate, and after the oscillation is stabilized, the gate element 7 is turned off and the first logic circuit with a high gain is activated. By stopping the oscillation of the circuit 4, the oscillator 1 can be caused to oscillate only by the second logic circuit 5 having a low gain.

なお、本発明は上述の実施例にのみ限定されるものでは
なく、特許請求の範囲に記載された範囲内において種々
変更し得るものであることは言うまでもない。
It goes without saying that the present invention is not limited to the above-described embodiments, but can be modified in various ways within the scope of the claims.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、マイクロコンピュータの
発振回路において利得の高いロジック回路と利得の低い
ロジック回路を設け、それらを電源投入時と発振安定後
とで切換え制御することKよシ、マイクロコンピュータ
の外部へ漏れる信号を少なくでき、不要輻射の軽減が図
れるという効果がある。
As explained above, the present invention provides a high-gain logic circuit and a low-gain logic circuit in the oscillation circuit of a microcomputer, and switches and controls them when the power is turned on and after the oscillation is stabilized. This has the effect of reducing the amount of signals leaking to the outside and reducing unnecessary radiation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
本発明の別の実施例を示すブロック図、第3図は従来の
マイクロコンピュータの発振回路の一例を示すブロック
図である。 1・・・・発振子、2・・・・帰還抵抗、3・・・・コ
ンデンサ、4費・・や第1ロジツク回路、5・・・・第
2ロジツク回路、6・・・・位相検出回路、7・・・・
ゲート素子、1o・・−・マイクロコンピュータ(CP
U)。
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional microcomputer oscillation circuit. . 1...Resonator, 2...Feedback resistor, 3...Capacitor, 4...First logic circuit, 5...Second logic circuit, 6...Phase detection Circuit, 7...
Gate element, 1o --- Microcomputer (CP
U).

Claims (1)

【特許請求の範囲】[Claims] 発振子と、その帰還増幅器として用いてなるインバータ
などのロジック回路から構成されるマイクロコンピュー
タの発振回路において、前記ロジック回路は利得の高い
第1ロジツク回路と利得の低い第2ロジツク回路から成
り、これら第1ロジツク回路、第2ロジツク回路を電源
投入時と発振安定後とで切換え制御する制御回路を具備
することを特徴とするマイクロコンピュータの発振回路
In a microcomputer oscillation circuit that is composed of an oscillator and a logic circuit such as an inverter used as its feedback amplifier, the logic circuit is composed of a first logic circuit with a high gain and a second logic circuit with a low gain. An oscillation circuit for a microcomputer, comprising a control circuit that switches and controls the first logic circuit and the second logic circuit when power is turned on and after oscillation has stabilized.
JP3542689A 1989-02-15 1989-02-15 Oscillating circuit for microcomputer Pending JPH02214311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3542689A JPH02214311A (en) 1989-02-15 1989-02-15 Oscillating circuit for microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3542689A JPH02214311A (en) 1989-02-15 1989-02-15 Oscillating circuit for microcomputer

Publications (1)

Publication Number Publication Date
JPH02214311A true JPH02214311A (en) 1990-08-27

Family

ID=12441538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3542689A Pending JPH02214311A (en) 1989-02-15 1989-02-15 Oscillating circuit for microcomputer

Country Status (1)

Country Link
JP (1) JPH02214311A (en)

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