JPH022136A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a shallow pn junction without consuming a semiconductor substrate by covering a window for forming a source and drain area which are formed at an insulation film on a semiconductor substrate with a silicon film, making it to react with a metal film to forming silicide, and diffusing impurities within a silicon film onto a substrate for forming a source and drain areas. CONSTITUTION:After forming a gate insulation film 3, a polycrystal silicon film gate electrode 4, a n<-> type source area 6, a drain area 7, and a dioxide silicon film gate electrode side wall film 5, a polycrystal silicon film 8 is formed. As ion is embedded, etching is performed, and only the silicon film 8 is left at the source and drain areas 6 and 7. Then, a titanium film 12 is formed, heat treating is performed, and than the non-reacted titanium film 12 is removed and heat treating is performed again. It allows a source electrode 13 consisting of titanium/silicide, a drain electrode 14, and a gate electrode 15 to be formed. At this time, impurities at the n<-> type source are 6 and the drain area 7 are activated, As is diffused from the silicon film 8, and a n<+> type source area 9 and a drain area 10 are formed.

Description

[Detailed Description of the Invention] [1 Already Required] Regarding a method suitable for manufacturing a semiconductor device using salicide, a structure is adopted in which a silicon semiconductor substrate is not consumed to generate silicide, and a means for impurity diffusion is devised. then pn
The aim is to prevent the bonding depth X from becoming large.
forming a window for forming a source region and a window for forming a drain region in an insulating film on a semiconductor substrate, and then forming an impurity-containing silicon film to cover the window for forming a source region and the window for forming a drain region. a step of forming a metal film that can be silicided on the entire surface, and then siliciding the metal film and the impurity-containing silicon film and diffusing impurities from the impurity-containing silicon film into the semiconductor substrate. The method includes a step of performing heat treatment to form a source region and a drain region.

[Industrial application field]

The present invention is based on salicide (se I fa I ign
The present invention relates to a method suitable for manufacturing a semiconductor device that employs ED 5ILIDE: 5ALICIDE).

The miniaturization of semiconductor devices is progressing rapidly, and along with this, the resistance of the contact portion, that is, the contact resistance and the diffusion layer resistance, is being reduced, the formation of shallow impurity diffusion regions, and the self- The effective use of alignment methods has become an important issue, and there is a need for technology that can deal with such issues.

[Conventional technology]

Mis (metal 1nsulat) in recent years.

In field effect semiconductor devices, in order to deal with the problems mentioned above, electrodes are formed using a self-alignment method using silicide of high melting point metals such as titanium (Ti) and cobalt (CO). A so-called salicide structure is adopted, and ion implantation using low acceleration energy is performed.

8 to 12 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining the prior art, and the following description will be made with reference to these figures.

See Figure 8 (11) For example, by applying a selective thermal oxidation method using a silicon nitride (Sf3N4) film as an oxidation-resistant mask, p
Silicon dioxide (SiO2
) is formed. Note that, although there actually exists a channel cut region under the field insulating film 2, it is omitted for the sake of simplicity.

(2) The silicon nitride film used as an oxidation-resistant mask and the like are removed to expose the element formation region of the silicon semiconductor substrate 1.

(3) By applying the thermal oxidation method, the thickness can be reduced to, for example, 15
A gate insulating film 3 made of silicon dioxide with a thickness of about 0 [people] is formed.

(4) Chemical vapor deposition
.

A polycrystalline silicon film having a thickness of, for example, about 3000 (people) is formed by applying a CVD (CVD) method.

(5) By applying normal photolithography technology, the polycrystalline silicon film formed in step (4) is patterned to form the gate electrode 4.

(6) By applying the ion implantation method, As ions are implanted to form the n-type source region 6 and the n-type drain region 7.

The conditions for this ion implantation are, for example, the following: Dose 'ft: I X I 013 (cm-'')
Acceleration energy: 60 [KeV].

Incidentally, the n-type source region 6 and the n-type drain region 7 cannot actually operate unless heat treatment is performed to activate the implanted ions, but this heat treatment is performed at an appropriate time during the process. Since the process is carried out at a specific time or is carried out concurrently with other processing, a specific explanation will not be provided, and the explanation will be based on the assumption that the region is formed at the stage of ion implantation. Furthermore, if the conductivity type of the silicon semiconductor substrate 1 is n type, it goes without saying that the source region 6 and drain region 7 are of p'' type.

Further, at this stage, patterning of the gate insulation M3 may be performed using the gate electrode 4 as a mask.

(By applying the 71CVD method, the thickness of
00 (person) silicon dioxide film is formed.

(8) Reactive ion etching using CF4+CHF3 as etching gas
By applying the etching: RIE) method,
The silicon dioxide film formed in step (7) is anisotropically etched to expose the surface of the silicon semiconductor substrate 1.

As a result, the silicon dioxide film is removed except for the sidewall film 5 of the gate electrode 4.

(9) By applying the ion implantation method, As ions are implanted to form the n+ type source h■ region 9 and the n+
A molded drain region 10 is formed.

The conditions for this ion implantation are, for example, the following: Dose amount: 4×10 15 (cm-”) Acceleration energy Q (KeV).

With this, the so-called LDD (lightly doped
This means that a drain) structure has been constructed.

See Figure 1O00) For example, by applying sputtering method,
Titanium (Ti) with a thickness of, for example, about 500 [people]
A film 12 is formed.

See Figure 11 0υ RTA (rapid thermal an
By applying the neal method, heat treatment is performed to cause the titanium film 12 to react with the silicon semiconductor substrate 1 and the gate electrode 4 made of polycrystalline silicon.

With this, the source electrode 1 made of titanium silicide
3, a drain electrode 14, and a gate electrode 15 are formed.

See Figure 12 (b) For example, hydrogen peroxide (H202): aqueous ammonia (NH40H): water (H2O) = 1: 1
: The titanium film 12 that was not converted into titanium silicide in the step 0υ is removed by immersion in an etchant consisting of 1.

After this, by applying conventional techniques, for example, phosphosilicate glass (phosphosilicate glass)
Passivation film made of glass (PSG) or aluminum 1. (Complete by forming electrodes, wiring, etc. made of all resin.

[Problem to be solved by the invention]

In the MIS field effect semiconductor device manufactured as described above, although low contact resistance and low diffusion layer resistance are achieved, part of the surface of the silicon semiconductor substrate is consumed to generate silicide, which is the electrode. The electrode and drain electrode are formed in a state that they penetrate into the silicon semiconductor substrate, and accordingly, the depth of the pn junction
becomes large.

In this case, even if a shallow pn junction is generated by ion implantation with low acceleration energy, the effort will be completely wasted.

The present invention adopts a configuration in which the silicon semiconductor substrate is not wasted to generate silicide, and also devises impurity diffusion means to prevent the depth X of the pn junction from becoming large.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, an insulating film (
For example, a step of forming a source region forming window and a drain region forming window in the field insulating film 2, etc.;
An impurity-containing silicon film (for example, a polycrystalline silicon film 8) covering the source region forming window and the drain region forming window
), then a step of forming a metal film (for example, the titanium film 12) that can be silicided on the entire surface, and then siliciding the metal film and the impurity-containing silicon film and forming the impurity-containing silicon film. The method includes a step of diffusing impurities into the semiconductor substrate and performing heat treatment to form a source region (for example, an n++ source region 9) and a drain region (for example, an n+ type drain region 10).

[Effect]

By adopting the above method, almost no semiconductor substrate is consumed when silicide is generated, and impurities contained in the silicon 1lfi are removed during the heat treatment when silicide is formed between the metal film and the silicon film. Since the source and drain regions are formed by diffusion into the semiconductor substrate, a shallow pn junction can be formed, and it goes without saying that low contact resistance and low diffusion resistance due to salicide can be obtained. performance and reliability will be improved.

〔Example〕

1 to 7 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. Note that the same symbols as those used in FIGS. 8 to 12 represent the same parts or have the same meanings.

Refer to FIG. 1. (1) Until the state shown in the figure is achieved, all steps fil to (8) according to the prior art explained with reference to FIG. 8 are the same.

See Figure 2 (by applying the 21CVD method, the thickness, for example, 20
Approximately 0 [people] to 5000 (people), preferably 10
00 (person) polycrystalline silicon film 8 is formed.

(3) By applying an ion implantation method, As ions are implanted into the polycrystalline silicon film 8 at a dose of, for example, about I x 1015 to 1016 (Cm-'') and an acceleration energy of, for example, 70 (KeV).

(4) By applying a spin coating method, a photoresist film 11 having a thickness of, for example, 2 [μm] is formed.

See Figure 3 (5) RI using etching gas as CF and +02
By applying the E method, photoresist 1-film 11
Etching back is performed to expose a portion of polycrystalline silicon film 8.

See Figure 4 (6) R using CCl4+02 as etching gas
By applying the IE method, the photoresist film 11
Using this as a mask, the polycrystalline silicon film 8 is etched to remove the portions above the n-type source region 6 and n-type drain region 7, leaving only those on the n-type source region 6 and n-type drain region 7.

At this time, the gate electrode 4 made of polycrystalline silicon is also slightly etched. Moreover, the polycrystalline silicon film 8 is
For example, an n-type source region 6 and an n''' type drain region 7
Alternatively, a silicon film selectively grown epitaxially or a polycrystalline silicon film selectively grown can be used instead.

Refer to FIG. 5. (7) By applying the magnetron sputtering deposition method, a titanium film 12 having a thickness of, for example, about 500 [people] is formed.

It is preferable that the thickness of the titanium film 12 be about 2 times that of the polycrystalline silicon film 8, and it goes without saying that titanium can be replaced with other materials such as Cohar 1-(Co). .

See Figure 6 (8) Rapid thermal annealing using, for example, a tungsten lamp as a heat source.
By applying the rmal anneal (RTA) method, the temperature can be adjusted to 600 ("C) to 650 ("C), for example.
A source electrode 13 made of titanium silicide (TiSiX) is formed by performing heat treatment for silicide of the titanium film 12, the polycrystalline silicon film 8, and the polycrystalline silicon gate electrode 4 with a heating time of, for example, 60 seconds. A drain electrode 14 and a gate electrode 15 are formed.

By this heat treatment, the impurities constituting the n'' type source region 6 and the n- type drain region 7 are activated, and As is diffused from the polycrystalline silicon film 8 to form the n+ type source region 9.
and an n+ type drain region lO.

Note that TiSix generated in this step satisfies 0<x<2.

See Figure 7 (9) Add the etchant to H2O2 + NH in the same manner as above.
By applying a wet etching method of 40II and H20, the excess titanium film 12 that has not been silicided is removed.

00) By applying the RTA method again, the temperature is set to, for example, 700 ("C) to 900 [°C], and the heating time is set to, for example, 3
Heat treatment is performed for 0 [seconds] to complete silicidation. In this way, the silicide produced in step (8) is 'l' i S iχ, but becomes high-quality TiSi2.

Due to this step and the heat treatment performed in step (8),
Activation of impurities forming the n- type source region 6 and n- type drain region 7 and formation of the n + type source region 9 and n + type drain region 10 are completed. The depth of the n"" type source region 6 and n- type drain region 7 thus completed is approximately 2000 (people), and the depth of the n+
The depth of the + source region 9 and the n + -type drain region 10 is about 1000 mm, which is shallower than in the case of conventional technology. This is largely due to the fact that it hardly consumes the substrate 1 and relies on impurity diffusion from the n++ source region 9, the n+ type drain region 10, and the polycrystalline silicon film 8.

αυ Thereafter, a pancipation film made of PSG, electrodes and wiring made of Al, etc., are formed and completed using ordinary techniques.

In the above embodiment, the conductivity type of each part is set with the silicon semiconductor substrate 1 being p-type, but it goes without saying that everything including the silicon semiconductor substrate 1 may be set to the opposite conductivity type. .

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to the present invention, a source region forming window and a drain region forming window formed in an insulating film on a semiconductor substrate are covered with a silicon film, and the silicon film and the metal film are bonded together. The silicon film is reacted to form a silicide, and impurities contained in the silicon film are diffused into the semiconductor substrate to form a source region and a drain region.

By adopting the above structure, almost no semiconductor substrate is consumed when generating silicide, and moreover, impurities are diffused from the silicon film during heat treatment during silicide formation to form source and drain regions. As a result, a shallow pn junction can be formed, and low contact resistance and low diffusion resistance due to the use of salicide can be obtained, and the performance and reliability of the semiconductor device are improved.

[Brief explanation of the drawing]

1 to 7 are cross-sectional side views of main parts of a semiconductor device at important process points for explaining one embodiment of the present invention, and FIGS. 8 to 12 are process diagrams for explaining a conventional example. 2A and 2B each represent a cutaway side view of a main part of a semiconductor device at a certain location. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a field insulating film, 3 is a gate insulating film, 4 is a gate electrode made of polycrystalline silicon, 5 is a sidewall film, 6 is an n-type source region, and 7 is a n-type drain region, 8 polycrystalline silicon film, 9
is an n++ source region, 10 is an n+ type drain region, 1
1 is a photoresist film, 12 is a titanium layer 11 for producing silicide, 13 is a source electrode made of titanium silicide, 14 is a drain electrode made of titanium silicide, and 15 is a gate electrode. Figure 1 Patent Applicant: Fujitsu Co., Ltd. Representative Patent Attorney Akio Aitani Attorney Patent Attorney Hiroshi Watanabe - Figure 2 Figure 3 Figure 7 Figure 8 Figure 5 et al. 9 et al. 10

Claims (1)

[Claims] A step of forming a source region forming window and a drain region forming window in an insulating film on a semiconductor substrate, and then forming an impurity-containing silicon that covers the source region forming window and the drain region forming window. a step of forming a film, a step of forming a metal film that can be silicided over the entire surface, and a step of siliciding the metal film and the impurity-containing silicon film and transferring impurities from the impurity-containing silicon film to the semiconductor substrate. 1. A method of manufacturing a semiconductor device, comprising the step of performing heat treatment to form a source region and a drain region.