JPH02205065A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02205065A JPH02205065A JP2423289A JP2423289A JPH02205065A JP H02205065 A JPH02205065 A JP H02205065A JP 2423289 A JP2423289 A JP 2423289A JP 2423289 A JP2423289 A JP 2423289A JP H02205065 A JPH02205065 A JP H02205065A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- metal wiring
- integrated circuit
- polysilicon resistor
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 239000003960 organic solvent Substances 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 238000007669 thermal treatment Methods 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 14
- 229910045601 alloy Inorganic materials 0.000 description 7
- 239000000956 alloy Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 229910001229 Pot metal Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、シリコン基板上に配設された抵抗値のばらつ
きが小さい、ポリシリコン抵抗体を有する半導体集積回
路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device having a polysilicon resistor disposed on a silicon substrate and having a small variation in resistance value.
従来の技術
近年、高速化する半導体集積回路装置にあっては、寄生
容量が小さいポリシリコン抵抗がよく使用される。2. Description of the Related Art In recent years, polysilicon resistors with small parasitic capacitance are often used in semiconductor integrated circuit devices that are becoming faster.
以下に従来の半導体集積回路装置について説明する。第
２図は、従来の半導体集積回路装置の断面構造図を示す
ものである。第２図において、１はシリコン基板、２は
第１絶縁膜、３はポリシリコン抵抗体、４は第２絶縁膜
、５は第１金属配線、６は第３絶縁膜、８は第２金属配
線、９は接続部、１０は合金層である。A conventional semiconductor integrated circuit device will be explained below. FIG. 2 shows a cross-sectional structural diagram of a conventional semiconductor integrated circuit device. In FIG. 2, 1 is a silicon substrate, 2 is a first insulating film, 3 is a polysilicon resistor, 4 is a second insulating film, 5 is a first metal wiring, 6 is a third insulating film, and 8 is a second metal 9 is a wiring, 9 is a connection portion, and 10 is an alloy layer.
以上のように構成された半導体集積回路において、ポリ
シリコン抵抗体３の接続部９では、第１金属配線５がポ
リシリコン抵抗体３と直接接続されている。In the semiconductor integrated circuit configured as described above, the first metal wiring 5 is directly connected to the polysilicon resistor 3 at the connecting portion 9 of the polysilicon resistor 3 .
発明が解決しようとする課題
しかしながら、上記の従来の構成では、第１金属配線５
を集積回路内部接続配線としているため、第２金属配線
５と下地とのオーミック接触を得るための約４００℃で
１５分程度の熱処理および第３絶縁膜をスピンオンガラ
スを含む複層膜で構成する場合、４５０〜５００℃で３
０分程度の平坦化熱処理、さらに、保護膜形成後に、プ
ラズマドライエツチングのプラズマ照射ダメージを除去
する４００〜４５０℃で１５分程度の熱処理がすべて、
第１金属配線５とポリシリコン抵抗体３との接続部９に
加わり、このため第１金属配線５の中の金属粒子が過剰
に拡散、合金化し、第１金属配線５とポリシリコン抵抗
体３との接続部９での合金層１０が、接続部９の端部か
ら横方向へ１．５〜２μｍ程度しみ出してしまい、ポリ
シリコン抵抗体３の長さによっては、その抵抗値のばら
つきが３０％〜５０％にも達したり、ショートしてしま
うという欠点を有していた。Problems to be Solved by the Invention However, in the above conventional configuration, the first metal wiring 5
Since this is used as an internal connection wiring of an integrated circuit, heat treatment is performed at approximately 400° C. for approximately 15 minutes to obtain ohmic contact between the second metal wiring 5 and the underlying layer, and the third insulating film is composed of a multilayer film containing spin-on glass. 3 at 450-500℃
Flattening heat treatment for about 0 minutes, and after forming the protective film, heat treatment for about 15 minutes at 400 to 450°C to remove plasma irradiation damage from plasma dry etching.
The metal particles in the first metal wiring 5 are excessively diffused and alloyed, and the first metal wiring 5 and the polysilicon resistor 3 are connected to each other. The alloy layer 10 at the connection part 9 with the polysilicon resistor 9 seeps out laterally by about 1.5 to 2 μm from the end of the connection part 9, and depending on the length of the polysilicon resistor 3, the resistance value may vary. It had the disadvantage that it could reach 30% to 50% or short circuit.
本発明は、上記従来の課題を解決するもので、ポリシリ
コン抵抗体の抵抗値を再現性よく得られる半導体集積回
路装置を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a semiconductor integrated circuit device in which the resistance value of a polysilicon resistor can be obtained with good reproducibility.
課題を解決するための手段
この目的を達成するために本発明の半導体集積回路装置
は、第１金属配線上に被着した第３絶縁膜上に配設する
第２金属配線が、ポリシリコン抵抗体の表面に直接接続
した構成を有し、第２金属配線をポリシリコン抵抗体の
集積回路内部接続配線としている。Means for Solving the Problems In order to achieve this object, the semiconductor integrated circuit device of the present invention provides a semiconductor integrated circuit device in which the second metal wiring disposed on the third insulating film deposited on the first metal wiring is a polysilicon resistor. It has a structure in which it is directly connected to the surface of the body, and the second metal wiring is used as the internal connection wiring of the integrated circuit of the polysilicon resistor.
作用
この構成によって、接続部ではポリシリコン抵抗体の表
面と第２金属配線が直接接触する。このため第２金属配
線とポリシリコン抵抗体との接続部では、第１金属配線
のオーミック接触用の熱処理および第３絶縁膜の平坦化
熱処理を受けないので、過剰な合金層をおさえ、従って
接続部からの合金層のしみ出しを制御でき、ポリシリコ
ン抵抗体の抵抗値のばらつきを低減することができ、抵
抗値の再現性のよい半導体集積回路装置を得ることがで
きる。Effect: With this configuration, the surface of the polysilicon resistor and the second metal wiring are in direct contact at the connection portion. Therefore, at the connection between the second metal wiring and the polysilicon resistor, the first metal wiring is not subjected to ohmic contact heat treatment and the third insulating film is not subjected to flattening heat treatment, so the excess alloy layer is suppressed and the connection is made. It is possible to control the seepage of the alloy layer from the portion, reduce variations in the resistance value of the polysilicon resistor, and obtain a semiconductor integrated circuit device with good resistance value reproducibility.
実施例
以下本発明の一実施例について図面を参照しながら説明
する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図は、本発明の一実施例における半導体集積回路装
置の断面構造図を示すものである。第１図において、シ
リコン基板１上に第１絶縁膜２、例えばシリコン酸化膜
を０．５μｍの厚さで形成した後、Ｐ型にドープしたポ
リシリコン抵抗体３を形成する。その後、第２絶縁膜４
を、例えばシリコン酸化膜を０．１μｍの厚さで構成し
た後、第１金属配線５として、Ｓｉを１％含むアルミニ
ウムを厚み１μｍ形成する。その後、下地とのオーミッ
ク接触を得る熱処理として、例えば３８０℃１５分の熱
処理を施した後、第３絶縁膜６として、例えばシリコン
酸化膜をプラズマＣＶＤ法により約０．５μｍ形成した
上部に、Ｓｉを含んだ有機溶剤を塗布し、スピンオンガ
ラスを形成する。そめ後、４００〜５００℃で３０分程
度の平坦化熱処理を施し、開講部７を開口し、第２金属
配線８を形成し、保護膜形成後にプラズマドライエツチ
ングのプラズマ照射ダメージを除去する４００〜４５０
℃で１５分程度の熱処理を施す。FIG. 1 shows a cross-sectional structural diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, a first insulating film 2, for example a silicon oxide film, is formed to a thickness of 0.5 μm on a silicon substrate 1, and then a P-type doped polysilicon resistor 3 is formed. After that, the second insulating film 4
For example, after forming a silicon oxide film with a thickness of 0.1 .mu.m, aluminum containing 1% Si is formed to a thickness of 1 .mu.m as the first metal wiring 5. Thereafter, heat treatment is performed at 380° C. for 15 minutes to obtain ohmic contact with the base, and then, as the third insulating film 6, a silicon oxide film is formed to a thickness of about 0.5 μm by plasma CVD. A spin-on glass is formed by applying an organic solvent containing . After cooling, a flattening heat treatment is performed at 400 to 500° C. for about 30 minutes to open the opening part 7, form the second metal wiring 8, and after forming the protective film, remove the plasma irradiation damage caused by plasma dry etching. 450
Heat treatment is performed at ℃ for about 15 minutes.
以上のように構成された半導体集積回路において、ポリ
シリコン抵抗体の接続部９には、第１金属配線５は形成
されず、第２金属配線８のみが直接接続される。このた
め第２金属配線８とポリシリコン抵抗体３との接続部９
では第１釜属配線の下地とのオーミック接触を得るため
の熱処理および第３絶縁膜の平坦化熱処理を受けないの
で、金属粒子の過剰な拡散が制御され、合金層のしみ出
＼１
しが０，３μｍ１１度以下と従来の１７５以下に低減さ
れる。これにともない、ポリシリコシ抵抗−のばらつき
も１０％程度まで低減可能ヤあ乞。′なお、ポリシリＬ
：１′：／抵抗体と第２金属配線間の合釜化熱処禅は、
保護膜形成後の４００〜４５０℃１５分の熱処理で、充
分小さく、安定したコンタクト抵抗が得られそいる。ま
た、コシ多りト数はポリシリコン抵抗体１個；巳つき、
等価回路にＭでいくつあってもよいことは明白である。In the semiconductor integrated circuit configured as described above, the first metal wiring 5 is not formed at the connection portion 9 of the polysilicon resistor, and only the second metal wiring 8 is directly connected. Therefore, the connecting portion 9 between the second metal wiring 8 and the polysilicon resistor 3
Since the heat treatment for obtaining ohmic contact with the base of the first pot metal wiring and the flattening heat treatment for the third insulating film are not performed, excessive diffusion of metal particles is controlled and the seepage of the alloy layer is prevented. It is reduced to 0.3 μm and 11 degrees or less, which is 175 or less than the conventional value. Along with this, the variation in polysilicon resistance can be reduced to about 10%. 'In addition, polysili L
:1':/The heat treatment process between the resistor and the second metal wiring is as follows:
A sufficiently small and stable contact resistance can be obtained by heat treatment at 400 to 450° C. for 15 minutes after forming the protective film. In addition, the number of stiffness is 1 polysilicon resistor;
It is obvious that there may be any number of M in the equivalent circuit.
発明の効果
以上のように、本発明によれば、第１金属配線上に被着
した第３絶縁膜上に配設する第２金属配線が、ポリシリ
コン抵抗体の表面に直接接続した構成により、第２金属
配線とポリシリコン抵抗体との接触部では第１金属配線
のオーミック接触用の熱処理および第３絶縁膜の平坦化
熱処理を受けないので、過剰な合金層をおさえ、従って
接続部からの合金層のしみ出しを制御でき、ポリシリコ
ン抵抗体の抵抗値のばらつきを低減でき、抵抗値の再現
性のよい優れた半導体集積回路装置を実現できる。Effects of the Invention As described above, according to the present invention, the second metal wiring disposed on the third insulating film deposited on the first metal wiring is directly connected to the surface of the polysilicon resistor. Since the contact area between the second metal wiring and the polysilicon resistor is not subjected to the heat treatment for ohmic contact of the first metal wiring and the flattening heat treatment of the third insulating film, the excess alloy layer is suppressed and the contact area is removed from the connection area. The seepage of the alloy layer can be controlled, the variation in the resistance value of the polysilicon resistor can be reduced, and an excellent semiconductor integrated circuit device with good resistance value reproducibility can be realized.
第１図は、本発明の一実施例半導体集積回路装置の断面
構造図、第２図は、従来の半導体集積回路装置の断面構
造図である。
２・・・・・・第１絶縁膜、３・・・・・・ポリシリコ
ン抵抗体４・・・・・・第２絶縁膜、５・・・・・・第
１金属配線、６・・・・・・第３絶縁膜、７・・・・・
・開口部、８・・・・・・第２金属配線。FIG. 1 is a cross-sectional structural diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional structural diagram of a conventional semiconductor integrated circuit device. 2...First insulating film, 3...Polysilicon resistor 4...Second insulating film, 5...First metal wiring, 6... ...Third insulating film, 7...
- Opening, 8...Second metal wiring.
Claims (1)
第１絶縁膜および前記ポリシリコン抵抗体を覆って被着
された第２絶縁膜と、前記第２絶縁膜上に配設された第
１金属配線と、前記第１金属配線および前記第２絶縁膜
を覆って被着された第３絶縁膜と、前記ポリシリコン抵
抗体の直上の前記第３絶縁膜上に配設された第２金属配
線とを有し、前記第２金属配線が、前記第２絶縁膜およ
び前記第３絶縁膜を貫通する開講部を介して、前記ポリ
シリコン抵抗体の表面に接続されてなる半導体集積回路
装置。a polysilicon resistor disposed on a first insulating film; a second insulating film deposited to cover the first insulating film and the polysilicon resistor; and a polysilicon resistor disposed on the second insulating film. a first metal wiring, a third insulating film deposited to cover the first metal wiring and the second insulating film, and a third insulating film disposed directly above the polysilicon resistor. a second metal wiring, and the second metal wiring is connected to the surface of the polysilicon resistor through an opening that penetrates the second insulating film and the third insulating film. circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2423289A JPH02205065A (en) | 1989-02-02 | 1989-02-02 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2423289A JPH02205065A (en) | 1989-02-02 | 1989-02-02 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02205065A true JPH02205065A (en) | 1990-08-14 |
Family
ID=12132512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2423289A Pending JPH02205065A (en) | 1989-02-02 | 1989-02-02 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02205065A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6703666B1 (en) * | 1999-07-14 | 2004-03-09 | Agere Systems Inc. | Thin film resistor device and a method of manufacture therefor |
-
1989
- 1989-02-02 JP JP2423289A patent/JPH02205065A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6703666B1 (en) * | 1999-07-14 | 2004-03-09 | Agere Systems Inc. | Thin film resistor device and a method of manufacture therefor |
| US7276767B2 (en) | 1999-07-14 | 2007-10-02 | Agere Systems Inc. | Thin film resistor device and a method of manufacture therefor |
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