JPH10223842A - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the electrode resistance and suppress the dispersion, by providing a silicon nitride film on an insulation film, an Si film having specified resistance on the silicon nitride film, and electrodes electrically connected to the Si film. SOLUTION: On a base film 12 Si films 13, 14 are provided which are doped with impurities at a high and slightly low concn., respectively. On the surfaces of the films 13, 14 an oxide film 15 is provided and second layer Si oxide film 16 is provided to form side walls and cover the Si films 13, 14. Contact holes of lower layer electrodes 13, openings for forming a dielectric layer 17, and contact holes of electrodes 18, 19 of a resistance are formed. At the dielectric layer-forming region a silicon nitride film 17 and Si film 20 are provided and electrodes 21, 22, 18, 19 are provided. This reduces the resistance value dispersion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same, and more particularly to a method using a silicon film having excellent characteristics as a substitute for a polysilicon film used as a resistor or an electrode.

[0002]

2. Description of the Related Art Generally, an IC generates a voltage for detecting a current, and has a built-in resistor for generating the voltage. On the other hand, as a resistor, there are a diffusion resistor using a diffusion region and a polysilicon resistor using polysilicon. However, with the recent high integration, the following merits have been obtained, and therefore, a polysilicon resistor has been attracting attention.

[0003] The first advantage is shrinkage. Diffusion resistors must be formed in islands surrounded by isolation regions, but polysilicon resistors are not required. In addition, the polysilicon resistor can be arranged at an arbitrary position on the insulating layer and can be formed in an empty space, so that the IC can be shrunk accordingly. A second advantage is suppression of parasitic effects. Although the formation of the P + type isolation region causes a parasitic capacitance at the PN junction, this parasitic capacitance does not occur in the polysilicon resistor because the isolation region is not used, and the influence of the parasitic capacitance on the circuit is eliminated.

[0004] For these reasons, there are many devices using a polysilicon resistor. As an example, FIG.
Fig. 6 shows the structure. Reference numeral 1 denotes an N-type epitaxial layer laminated on a P-type semiconductor substrate, and a P-type diffusion region 2
Is formed, and a poly-Si film 5 is formed via an insulating film 3. Here, reference numeral 3 denotes a Si oxide film. Further, an aluminum electrode 7 is provided as a passivation via an interlayer insulating resin layer 6.

Here, a diffusion resistor having a positive temperature coefficient and poly-Si having a negative temperature characteristic are connected in parallel to realize a resistor having a small temperature coefficient. However, when temperature compensation is not considered, the diffusion resistance is not formed below the poly-Si resistor, but is formed on a space or on the insulating films 3 and 4 or in a LOCOS oxide film in MOS or Bi-CMOS. Is placed on top.

The film is formed at a temperature at which polysilicon is formed when silane gas adheres to the insulating film 3 by utilizing LPCVD, that is, at about 620 ° C. When this polysilicon surface is observed with an electron microscope, grains can be observed,
There is a difference, but the diameter is about 500
Å. On the other hand, there is a type in which a capacitor is formed on a LOCOS oxide film or the insulating film of FIG. First, a polysilicon film to be used as an electrode is formed on these insulating films, a silicon nitride film as a dielectric material is provided thereon, a polysilicon film is provided thereon as an upper layer electrode, and an Al electrode is further provided. Are provided, and are configured as capacitors. This structure is similar to the capacitor of FIG. 1 except that there is no silicon nitride film 12 disposed on the LOCOS oxide film.

[0007]

In the case where the former polysilicon is used as a resistor, there has been a problem that the number of steps is increased or the variation is increased as compared with a diffusion resistor. In other words, a board on which a number of wafers on which a plurality of ICs to be formed are formed is mounted is placed in a polysilicon layer deposition chamber (L
PCVD, etc.), and the film is formed. It was found that the variation of the polysilicon resistor between wafers, the variation of the polysilicon resistor in the wafer, and the variation of the polysilicon resistor in the IC were large. . As a result, a large number of ICs deviating from the allowable range of the resistance value are generated, and the yield is reduced.

In the latter case where polysilicon is used as the capacitor electrode, the resistance of the capacitor varies due to the above-described variation in polysilicon, which eventually causes the characteristics of the capacitor to vary. In addition, a polysilicon film is coated on the silicon nitride film to protect the dielectric layer. In this technique (Japanese Patent Application Laid-Open No. 62-163356), it seems that the protection of the Si nitride film is completely covered by the polysilicon, but after the formation of the Si nitride film, the film is etched to control the thickness. This weak point in the structure is positively removed (the intermediate product of the Si nitride film is easily removed with hydrofluoric acid), and a large pinhole is formed. Or the pinholes are too small and oxidation does not proceed. In addition, the weak spots are scattered. Therefore, there has been a problem that the conductive material formed in the upper layer (here, the poly-Si layer) and the lower electrode are short-circuited or the film quality is deteriorated.

Further, instead of poly-Si, an Si oxide film is
There is also a process of forming a film on a nitride film by CVD and removing the Si oxide film when opening contact holes for the emitter, base and collector of the TR. That is, the Si nitride film is Si
Although it is protected by an oxide film, it is necessary to completely remove this oxide film because the capacitance value of the capacitor decreases,
Some over-etching is needed. Eventually, the Si nitride film is exposed to an etching gas or an etchant, so that the weak spot is positively etched, which causes a problem of deteriorating characteristics such as withstand voltage.

That is, it has been found that the characteristics are not improved because the unreacted Si becomes an insulating layer by etching or thermal oxidation, and the characteristics are rather deteriorated. In addition, by the heat treatment, a part of Si-ON becomes SiO2,
In addition, there is a problem that weak spots increase due to the partial formation of an intermediate product of the Si nitride film and pinholes are formed by the etching process.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems. First, a silicon nitride film provided on an insulating film and an amorphous silicon film provided on the silicon nitride film are provided. The problem is solved by having a silicon film having a predetermined resistance value obtained by heat treatment and a pair of electrodes electrically connected to the silicon film.

As will be described later, as shown in FIG. 5 and FIG. 6 in which the deposition temperature of the silicon film is plotted on the horizontal axis, if amorphous silicon is applied at a low temperature and then annealed and used, the sheet resistance value is low and there is no variation. Things have been realized. In addition, it was found that the use of a silicon nitride film as a base of the silicon film further improved the performance. As shown in FIG. 7, when the line width is about 10 to 50 μm, the resistance is high (High R) and the base is a silicon oxide film (top graph) and the base is a silicon nitride film (second graph from the top). In the graph), the variation of 8% is reduced to 5%. In the case of low resistance (Low R), 5% is 2% or less.

Second, a silicon nitride film provided on the insulating film, a silicon film provided on the silicon nitride film and serving as a lower electrode of a capacitor obtained by heat-treating the amorphous silicon film, and a silicon film The problem is solved by having a silicon nitride film which is provided as a dielectric layer of the capacitor provided above and an upper electrode of the capacitor electrically connected to the silicon nitride film.

The first means is applied to an electrode of a capacitor. A silicon film obtained by heat-treating amorphous silicon lowers the resistance value of the electrode, suppresses variations, and further improves these characteristics by using a base. it can. The third means utilizes the silicon film as a protective film of a dielectric material. The film formation temperature of this silicon film is 100 degrees lower than the film formation temperature of the polysilicon film. It is possible to suppress the deterioration of the dielectric material at the time. Further, since the silicon film can be formed with a low resistance value, the function as an electrode can be improved, and the characteristics of the capacitor can be improved.

A fourth means is a method for manufacturing a silicon film. The method includes forming a silicon layer on a silicon nitride film formed on an insulating layer at an amorphous formation temperature, and introducing impurities into the silicon layer. The impurity is diffused by heat treatment while substantially maintaining the surface roughness of the silicon layer, and the diffused silicon layer is used as a resistor, so that the resistance value of the silicon film can be reduced. Is a silicon nitride film, so that variations can be further suppressed.

A fifth means is one in which the fourth means is applied to a capacitor, wherein a silicon layer is formed on a silicon nitride film formed on an insulating layer at an amorphous formation temperature, and impurities are introduced into the silicon layer. Then, a heat treatment is performed while substantially maintaining the surface roughness of the silicon layer to diffuse the impurities, and the diffused silicon layer is used as a lower electrode of the capacitor to solve the problem.

A sixth means is to utilize this silicon layer to protect a silicon nitride film which is a dielectric of a capacitor. Since the silicon layer is formed at a lower temperature than polysilicon, the silicon nitride film has a corresponding defect. Can be prevented. In all of the above means, first, a silicon layer is formed on an insulating film at an amorphous formation temperature.

In FIG. 6, the abscissa indicates the temperature at which the (amorphous silicon layer) is formed, and after heat treatment, the ordinate indicates the variation in the sheet resistance Rs of the film. Things. In other words, there is a large difference between a low temperature at which amorphous silicon is formed and a high temperature at which polysilicon is directly applied.
Almost 3 for direct deposition of polysilicon (620 degrees)
% Or more, but three kinds of film thicknesses (2000Å, 3000
{4000}), which is substantially 1%.

When the surface roughness is observed with an electron microscope,
With the direct deposition of polysilicon, the grain size can be observed at about 500 °, and since etching is performed in this state, the grain boundary is positively etched. However, even when the amorphous silicon film is first applied and heat-treated, no grain or grain boundary is observed at all even when observed with an electron microscope. Therefore, in the etching at the time of patterning, there is no element (etching the grain boundary) that makes the pattern uneven, so that etching can be performed on a flat surface and variation can be suppressed. Moreover, as shown in FIG. 5, it has been found that the method of forming a film at a low temperature, that is, forming an amorphous silicon film and then introducing an impurity and annealing the film also lowers the sheet resistance. In other words, the characteristics can be improved whether utilized as a resistor or a capacitor. Further, as shown in FIG. 7, when a silicon nitride film is used as a base, the characteristics can be further improved.

[0020]

Embodiments of the present invention will be described below. 2 to 4 show the conversion state of the film, the left side shows the conventional method, which is directly annealed from polysilicon, and the right side shows the amorphous silicon (hereinafter referred to as a) of the present invention. −Si) to after the heat treatment.

The experimental flow at this time is as follows. A: A silicon oxide film of about 1000 ° is grown on a silicon substrate. B: 540 degree, 580 degree, 6 mounted on LPCVD equipment
At 100 degrees and 620 degrees, 100% silane gas (S
iH4). The film thickness at this time is 2
000, 3000, and 4000.

C: BF 2 is ion-implanted over the entire surface. 60
eV, 3 × 10 15 However, in order to further reduce the sheet resistance described later, a−S
It is necessary to increase the film thickness of i, increase the electrode width, or increase the impurity concentration. D: Annealing for 1 hour in a nitrogen atmosphere at 900 degrees.

E: Measurement of sheet resistance RS. 2 shows the steps up to B, FIG. 3 shows a state in which the step C is completed, FIG. 4 shows a state in which the step D is completed, and FIG. 5 (sheet resistance Rs) and FIG. (Variation in resistance). The horizontal axis in FIGS. 5 and 6 indicates the film forming temperature in the step B. Further, FIG. 7 shows a pattern obtained by patterning the film of FIG. 4 to form a resistor, and measuring the variation in the resistance value of the resistor. The number of measurements is 160. The triangular points indicate that the base is a silicon oxide film, the upper line is high resistance (2 KΩ indicated by High R), the lower line is low resistance (200 KΩ indicated by Low R), and the rhombic points are The underlying layer is a silicon nitride film, and the upper line is the high resistance,
The lower line is the low resistance.

Looking at the measurement results, the lower the film forming temperature,
It was found that the sheet resistance was low and the variation was small.
Further, it was also found that when the film was formed in the step B, at about 520 degrees to 580 degrees (hereinafter referred to as a low-temperature region), the film was made of amorphous silicon. Further, a region exceeding 590 degrees to 610 degrees (hereinafter referred to as a high-temperature region) has a greatly changed surface state and is made of polysilicon. About 580
It is considered that a region between about degrees and 600 degrees (hereinafter referred to as an intermediate region) is a transition region between polysilicon and amorphous silicon.

The surface condition of the silicon film is as follows:
As can be seen from the electron microscope (magnification: 50,000), as shown on the right side of FIG. 2, unevenness on the surface is hardly observed, and a-Si1 is formed. On the other hand, in the high temperature region, a polysilicon film 3 of 500 ° (diameter) can be observed as a slightly large grain 2 as shown on the left of FIG. A grain boundary 4 exists between the grains 2.

Next, in the ion implantation in the step C, the ion implantation shown in FIG.
As indicated by the mark, boron fluoride (BF2 +) 5 has been ion-implanted, and it is considered that the impurity distribution states of the right a-Si film and the left polysilicon film are substantially the same. Here, if boron ions are implanted, they penetrate through the a-Si film or the polysilicon film, and therefore, boron fluoride having a large size to enter the vicinity of the surface is employed. In addition, As and S
Since b ions do not enter deeply like boron fluoride, they can be employed.

Further, the annealing step in the step D is about 800 to 1000 degrees, preferably about 900 degrees.
The result here was a different phenomenon than expected. Although the grain size of the polysilicon film 3 on the left side of FIG. 4 is slightly different due to the heat treatment, the grain is formed by an electron microscope (5000).
(0x magnification). However, aS on the right side of FIG.
i was a flat film because it was not possible to determine whether there was any grain even when observed with an electron microscope (magnification of 50,000 times). Since the heat treatment has been applied, it is difficult to imagine that the polysilicon film remains as a-Si. That is, the polysilicon film is generated in the order of two digits or one digit, and the part that is substantially observed is a single crystal. It can be determined that the film is from a film having a large grain. In addition, no grain boundary can be observed. In the former case, it is considered that the grain boundary is very narrow and small ones are finely dispersed, and in the latter case, the grain is large and almost all of the resistor is 1%.
It can be determined that there is no real grain boundary in one grain.

In general, the film after annealing is 5 ° C. in a high temperature region.
Grains of about 00 ° exist and the surface is rough, but the surface is much flatter in the low temperature region than in the high temperature region. In other words, when the polysilicon film in the high temperature region is etched, the grain boundary has a higher etching speed, so that the surface looks uneven when observed with an electron microscope. Further, the surface of the a-Si film in the low temperature region is almost flat. This is because if the polycrystalline state is finer than the polysilicon film in the high-temperature region, even if the grains are selectively etched, it looks substantially flat, and one or two grains having a large grain form a resistor. Then, since the grain boundary is almost non-existent in comparison with polysilicon, even if it is etched, it is possible to form a flat, well-shaped and beautiful pattern. Here, the etching is anisotropic dry etching.

That is, the feature of the present invention is that an a-Si film is formed on a wafer provided in an LPCVD apparatus by flowing a silane gas in a low temperature region, and impurities are diffused while heat treatment is performed on the a-Si film. It is to be used as a body and as an electrode of a capacitor. As described above, this film has a small variation in sheet resistance and is a flat film whose surface state is substantially indistinguishable from a-Si. High etching process. Therefore, the variation of the resistance value of the resistor is remarkably reduced due to the two points that the variation of the sheet resistance is small and that the shape can be accurately etched. Further, as shown in FIG. 5, the value of the sheet resistance in the low temperature region can be reduced, and it can be used as a material closer to the electrode.

If a silicon nitride film is adopted as the dielectric layer and an amorphous silicon layer is formed immediately in a non-oxidizing atmosphere after the formation of the silicon nitride film, the surface of the silicon nitride film is not exposed to various atmospheres. In addition, since the temperature can be lowered by about 100 degrees without the application of a high temperature, a high-quality film free of defects and oxide films can be maintained to the end.

Furthermore, after forming an amorphous silicon layer on the insulating layer, introducing impurities into the amorphous silicon layer, the impurities are diffused by heat treatment while substantially maintaining the surface roughness, and the silicon layer is formed as a capacitor. When used as a lower layer electrode, as described above, amorphous silicon can lower the sheet resistance value compared to polysilicon, so that the resistance value can be further reduced even if the step of introducing impurities into the base and the emitter is also used. In addition, since the surface has good roughness, the quality of the silicon nitride film formed thereon can be improved. Moreover, if polysilicon is placed on this high quality film, the film quality of polysilicon can be further improved.

As shown in FIG. 7, the variation greatly varies depending on the base, and the use of a silicon nitride film as the base can suppress the variation in the resistance value. When the line width of FIG. 7 is in the range of about 10 to 50 μm, the high resistance is
The variation of 8% is reduced to 5%. In the case of low resistance, 5% is 2% or less. Since the silicon nitride film itself has a dense and flat surface, it is considered that the silicon film thereon can be satisfactorily applied.

FIG. 1 shows a semiconductor integrated circuit in which a silicon nitride film is used as a base and a silicon layer is formed thereon for use as a lower electrode of a resistor or a capacitor for the reasons described above. An insulating film 11 is formed on the semiconductor layer 10. This insulating film is a silicon oxide film,
A thick oxide film used in BIP and a LOCOS oxide film used in MOS and Bi-CMOS. A silicon nitride film 12 is provided as a base film on a part of the insulating film. Here, the silicon nitride film may be a continuous film in which a resistor and a capacitor are mounted together, or may be separated separately. However, since the silicon nitride film gives distortion due to the difference in the coefficient of thermal expansion, it is preferable that the thickness and the area be as small as possible. Therefore, if the thickness of the silicon nitride film exceeds 1000 °, it is better to separate the silicon nitride films with the minimum area where they can be mounted. In addition, the thickness is 20
If the angle is about 0 to 600 °, distortion may be small and continuous.

The silicon films 13 and 14 are provided on the base film 12 by the above-described method. The silicon film 13 is heavily doped with impurities to be used as a lower electrode. In addition, the silicon film 14 is slightly doped to achieve a predetermined resistance value. An oxide film 15 is provided on the surfaces of the silicon films 13 and 14, a sidewall is also formed, and a second relatively thick silicon oxide film 16 is provided so as to cover the silicon films 13 and 14. A contact hole of the lower electrode 13, an opening serving as a region for forming the dielectric layer 17, and contact holes of the electrodes 18 and 19 of the resistor are formed. The silicon nitride film 17 and the silicon film 2 are formed in the region where the dielectric layer is formed.
0 is provided. Further, the electrodes 21, 22, 18, 19
Is provided. Here, the silicon film 20 is also formed by the method described above, but may be a polysilicon film.

Next, a method of manufacturing a semiconductor integrated circuit will be described. 8 to 15 are N-type MOs from the left.
S, NPN transistors, capacitors and resistors are shown as being formed. First, a P-type semiconductor substrate 70 is doped with impurities of a predetermined P + -type buried layer 71, an N + -type buried layer 72, and a P + -type lower isolation region 73, on which an N-type epitaxial layer 74 is formed. It is laminated. These impurities are diffused above the epitaxial layer 74 by the heat treatment during the lamination or separately. Further oxidizing the epitaxial layer 74,
Thousands of silicon oxide films 75 are grown. This film 75
Is used as a mask for subsequent ion implantation. In the silicon oxide film 75, a portion corresponding to the planned P + type well 76 of the N-type MOS and the planned upper isolation region 77 is formed. Boron ion is formed in the opening at a concentration required for the well 76. Has been injected. Further, the resist 78 is opened so that a portion corresponding to the isolation region 77 is opened.
And boron is ion-implanted into the isolation region 77 again. (See FIG. 8) Subsequently, thermal diffusion is performed so that the lower isolation region 73 and the upper isolation region 77 overlap each other, and the oxide film 75 is removed. The following is the formation of a LOCOS oxide film, and thus an oxide film 79 of about 500 ° is generated. Further, a silicon nitride film 81, which is an anti-oxidation film, is attached to a portion excluding a region where the planned LOCOS oxide film 80 is to be formed. (Refer to FIG. 9) Subsequently, LOCOS oxidation is performed. LOCOS oxide film 80 having a thickness of about 7000 to 10,000 degrees is generated by thermal oxidation at about 1000 degrees. After this, the oxide film 79
Is removed, and a thin oxide film (gate insulating film 82) is again formed at about 500 °.

Subsequently, an underlying silicon nitride film 8 is formed on the entire surface.
3 is deposited at about 400 DEG and is preferably patterned so as to remain only in the area where the capacitors and resistors are applied.
Subsequently, a film for the resistor is formed. Here, this resistor film is also formed of a-Si. The wafer formed up to the above process is mounted on a wafer board and mounted on an LPCVD apparatus. A gas for forming a-Si (100% silane gas in this case, but not limited thereto) is flowed from this apparatus, and a film forming temperature of 520 to 580 degrees, preferably about 540 to 560 degrees is formed. A-Si8 at film temperature
4 is formed on the entire surface of the wafer. This wafer contains the C
BF2 is introduced by ion implantation and N2
After being annealed in an atmosphere at about 900 degrees, it is patterned into a shape as a resistor. (Refer to FIG. 10) As described above, unlike conventional polysilicon, the sheet resistance is low, and the surface roughness of the film is so small that no grain can be recognized. It has the feature that it can be patterned in a shape and the variation of the resistance value can be remarkably suppressed. In addition, the film characteristics are further improved because the underlayer is a silicon nitride film.

Subsequently, after slightly oxidizing and further growing the gate insulating film 82, a silicon film for a gate electrode is formed on the entire surface by LPCVD so that a-Si is formed.
Impurities are added to a-Si using OCl3, and further diffused by heat treatment. After that, the gate, the gate line and the capacitor are patterned into the shape of the lower electrode 85,
Oxidation forms oxide film 86. (See FIG. 11) Subsequently, P ions are ion-implanted using a mask made of a photoresist with the source-drain portions of the NMOS exposed.
In order to attach the sidewall 88 of the gate 87, 150
An oxide film of about 0 ° is formed on the entire surface and etched back to form a sidewall 88. A low concentration source 89 and drain 90 are formed by the following heat treatment. (Figure 1
Subsequently, a photoresist is attached so that the base region 91 of the NPN transistor is exposed, and boron ions as impurities of the base 91 are implanted. Further, a photoresist 92 exposing the source / drain region of the NMOS, the emitter and the collector contact of the transistor is covered, and As
Is ion-implanted. Subsequently, boron is ion-implanted using a resist in which a region corresponding to the base contact of the transistor is opened through a heat treatment as a mask, and after removing the resist, BPS is applied to the entire surface.
A G film 93 is formed. By this time, high concentration source 9
4, a drain 95, an emitter region 96, a base contact region 97, and a collector contact region 98 are formed by thermal diffusion. Then, the film 93 corresponding to the dielectric formation region of the capacitor is etched, and a silicon nitride film 99 and an a-Si film 100 are formed thereon. After that, the contact is opened. (See FIG. 14) Finally, as shown in FIG. 15, an electrode is formed in this contact hole. Actually, a passivation film or the like is laminated thereon to complete the IC chip, but the description is omitted.

The lower electrode 85 and the upper electrode 10 of the capacitor
In the case of No. 0, as described above, a-Si is formed on the entire surface in the low temperature region, and then, after doping with impurities, annealing is performed while also performing diffusion while maintaining the surface roughness of a-Si. As shown in FIG. 5, since the sheet resistance can be reduced, the function as an electrode can be further enhanced.
Further, the concentration is increased by using a step of introducing an impurity into the gate electrode and a step of introducing an impurity into the diffusion region, but the impurity concentration is predetermined. Therefore, even at this predetermined concentration, the sheet resistance can be lower than that of the conventional polysilicon film, and the function as an electrode can be enhanced. The capacitor is
Q is measured as a characteristic. The Q is a resistance generated in the capacitor, and the value of the Q is reduced. However, the characteristic of the Q can be enhanced by the reduction in the resistance.

Further, since the film quality of the lower electrode 85 is flat, the film quality of the silicon nitride film 99 formed thereon can be improved. As a result, a
-The film quality of Si98 can be further improved. In addition, it is further improved by the influence of the base. Here, FIG. 10, FIG.
In step 1, the silicon nitride film 83 and the silicon film 8
4,85 are continuously formed by LPCVD, and a gate electrode,
Gate line and electrode group of lower layer electrode 85 and resistor 84
May be performed separately to control the impurity concentration.

[0040]

As is clear from the above description, the first
In addition, when a silicon film provided on this silicon nitride film and obtained by heat-treating an amorphous silicon film is used as a resistor, variations in sheet resistance and variations in resistance value of the resistor are suppressed, and the yield is improved. Can be.

Second, by utilizing the silicon film provided on the silicon nitride film and obtained by heat-treating the amorphous silicon film as the lower electrode of the capacitor, the resistance value of the electrode is further reduced and the variation is suppressed. be able to. In addition, these characteristics can be further improved by the base, and the yield of the capacitor can be improved.

Third, if the silicon film is used as a protective film for the dielectric material, the film forming temperature of the silicon film is low, so that the deterioration of the dielectric material during the film formation can be suppressed. Also, since the silicon film can be formed with a low resistance value,
The function as an electrode can be improved, and the characteristics of the capacitor can be improved. Fourth, a method of manufacturing a silicon film is to form a silicon layer on a silicon nitride film formed on an insulating layer at an amorphous formation temperature, and to introduce impurities into the silicon layer. When the impurity is diffused by performing a heat treatment while maintaining the temperature substantially, and the diffused silicon layer is used as a resistor, the resistance value of the silicon film can be reduced. Further, since the underlying layer is a silicon nitride film, Further, variation can be suppressed.

Fifth, the fourth means is applied to a capacitor, and a silicon layer is formed on a silicon nitride film formed on an insulating layer at an amorphous formation temperature and impurities are introduced into the silicon layer. If the impurity is diffused by heat treatment while substantially maintaining the surface roughness of the silicon layer, and the diffused silicon layer is used as a lower electrode of the capacitor, the characteristics of the capacitor can be improved.

Sixth, the silicon layer is used to protect a silicon nitride film which is a dielectric of a capacitor. Since the silicon layer is formed at a lower temperature than polysilicon, it is possible to prevent the silicon nitride film from being induced by defects. In addition, the characteristics of the dielectric film of the capacitor can be maintained without deteriorating.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor integrated circuit of the present invention.

FIG. 2 is a diagram illustrating a state where a-Si of the present invention and a conventional poly-Si film are attached.

FIG. 3 is a diagram illustrating a state when ions are implanted into two types of films in FIG. 2;

FIG. 4 is a diagram illustrating a state when the two types of films of FIG. 3 are annealed.

FIG. 5 is a diagram illustrating the sheet resistance of the present invention and a conventional resistive film.

FIG. 6 is a diagram illustrating a variation in sheet resistance in FIG. 5;

FIG. 7 is a diagram in which a base is divided into a silicon oxide film and a silicon nitride film, and variations in resistance values of resistors are examined.

FIG. 8 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 9 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 10 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 11 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 12 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 13 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 14 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 15 is a cross-sectional view of a semiconductor integrated circuit illustrating a manufacturing method of the present invention.

FIG. 16 is a cross-sectional view illustrating a conventional resistor.

Claims (6)

[Claims] 1. An insulating film formed on a surface of a semiconductor layer, a silicon nitride film provided on the insulating film, and a predetermined resistor provided on the silicon nitride film and obtained by heat-treating an amorphous silicon film. A semiconductor film having at least a silicon film having a value and a pair of electrodes electrically connected to the silicon film. 2. An insulating film formed on a surface of a semiconductor layer, a silicon nitride film provided on the insulating film, and a lower layer of a capacitor provided on the silicon nitride film and obtained by heat-treating an amorphous silicon film. A silicon film serving as an electrode, a silicon nitride film serving as a dielectric layer of the capacitor provided on the silicon film, and an upper electrode of the capacitor electrically connected to the silicon nitride film serving as the dielectric layer;
A semiconductor integrated circuit having an electrode electrically connected to the silicon film. 3. The semiconductor integrated circuit according to claim 2, wherein a silicon film obtained by heat-treating an amorphous silicon film is provided between the silicon nitride film serving as the dielectric layer and the upper electrode. 4. A method for forming a silicon layer at an amorphous formation temperature on a silicon nitride film formed on an insulating layer of a semiconductor integrated circuit, introducing impurities into the silicon layer, and then substantially reducing the surface roughness of the silicon layer. A method for manufacturing a semiconductor integrated circuit, characterized in that the impurity is diffused by heat treatment while maintaining the impurity, and the diffused silicon layer is used as a resistor. 5. A method for forming a silicon layer at an amorphous formation temperature on a silicon nitride film formed on an insulating layer of a semiconductor integrated circuit, introducing impurities into the silicon layer, and subsequently reducing the surface roughness of the silicon layer. A method for manufacturing a semiconductor integrated circuit, characterized in that the impurity is diffused by heat treatment while maintaining the same, and the diffused silicon layer is used as a lower electrode of the capacitor. 6. The method according to claim 5, wherein the dielectric layer of the capacitor is a silicon nitride film, and the amorphous silicon layer is formed immediately after the formation of the silicon nitride film in a non-oxidizing atmosphere.