JPS5912010B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5912010B2
JPS5912010B2 JP50035064A JP3506475A JPS5912010B2 JP S5912010 B2 JPS5912010 B2 JP S5912010B2 JP 50035064 A JP50035064 A JP 50035064A JP 3506475 A JP3506475 A JP 3506475A JP S5912010 B2 JPS5912010 B2 JP S5912010B2
Authority
JP
Japan
Prior art keywords
metal
contact
manufacturing
wiring
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50035064A
Other languages
Japanese (ja)
Other versions
JPS51110265A (en
Inventor
和利 上林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP50035064A priority Critical patent/JPS5912010B2/en
Publication of JPS51110265A publication Critical patent/JPS51110265A/en
Publication of JPS5912010B2 publication Critical patent/JPS5912010B2/en
Expired legal-status Critical Current

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  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係り、特にその配線の
形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming wiring therefor.

従来の半導体装置における電極配線の形成方法において
は、能動素子や受動素子の端子部に対応して酸化シリコ
ンのような絶縁膜に電極コンタクト用窓を設けたのちに
、チタンや白金等のコンタクト用金属をシリコン基板全
面に被着してから、熱処理を行つて素子のコンタクト部
に金属シリサイドを形成し、続いて金属シリサイドに変
化していない余分のコンタクト用金属をエッチングして
除去する必要があつた。
In the conventional method for forming electrode wiring in semiconductor devices, electrode contact windows are formed in an insulating film such as silicon oxide to correspond to the terminals of active elements and passive elements, and then contact windows made of titanium or platinum are formed. After metal is deposited on the entire surface of the silicon substrate, it is necessary to perform heat treatment to form metal silicide in the contact area of the element, and then to remove the excess contact metal that has not changed to metal silicide by etching. Ta.

次に配線用金属を被着してから選択的にエッチングして
電極配線を形成する。5 このような従来技術において
は、余分のコンタクト用金属のエッチングという困難な
工程が必要であるばかりでなく、この工程における汚染
による性能劣化や歩留りの低下が大きな問題となつてい
る。
Next, metal for wiring is deposited and selectively etched to form electrode wiring. 5. Such conventional techniques not only require the difficult process of etching excess contact metal, but also pose major problems such as performance deterioration and yield reduction due to contamination in this process.

10本発明はこのような欠点を改善した、新規な電極配
線の形成方法による半導体装置の製造方法を提供するこ
とを目的とする。
10 An object of the present invention is to provide a method for manufacturing a semiconductor device using a novel method for forming electrode wiring, which improves the above-mentioned drawbacks.

本発明の特徴は、半導体基板上に開口を有する絶縁膜を
設ける工程と、この絶縁膜上及び開口内15に第1の金
属を被着する工程と、この開口の部分に金属シリサイド
を形成する工程と、しかる後に第1の金属上に第2の金
属を被着する工程と、第1の金属をこの第2の金属に拡
散吸収させた後にこれをエッチングして所望の配線パタ
ーンにする20工程とを含む半導体装置の製造方法にあ
る。
The features of the present invention include the steps of providing an insulating film having an opening on a semiconductor substrate, depositing a first metal on the insulating film and in the opening 15, and forming metal silicide in the opening. step, followed by a step of depositing a second metal on the first metal, and etching the first metal into a desired wiring pattern after diffusing and absorbing the first metal into the second metal. A method of manufacturing a semiconductor device includes steps.

例えば、電極コンタクト用窓の設けられた絶縁膜を被着
した単結晶シリコン基板の一主面上全面に第1の金属と
してコンタクト用金属を被着して、この電極コンタクト
窓部に金属シリサイドを形成し、25更に第2の金属と
して配線用金属を被着して絶縁膜上のコンタクト用金属
をこの配線用金属内に拡散吸収させた後に所望形状の電
極配線を形成する半導体装置の製造方法である。本発明
によれば、第1の金属によつて基板の開30口部に金属
シリサイド膜が形成されるので、第2の金属が基板と合
金化する、いわゆるアロイスパイクを防止できる。
For example, a contact metal is deposited as the first metal on the entire main surface of a single crystal silicon substrate on which an insulating film provided with an electrode contact window is deposited, and metal silicide is applied to the electrode contact window. 25. A method for manufacturing a semiconductor device, which further comprises depositing a wiring metal as a second metal, diffusing and absorbing the contact metal on the insulating film into the wiring metal, and then forming an electrode wiring in a desired shape. It is. According to the present invention, since a metal silicide film is formed by the first metal at the opening 30 of the substrate, so-called alloy spikes in which the second metal becomes alloyed with the substrate can be prevented.

そして、第1の金属を第2の金属に拡散吸収してからエ
ッチングによるパターンニングを行なうので、第1の金
属にエッチング35の困難な金属を用いることができる
。さらに、第1、第2の金属を一度にエッチングするこ
とができるので、製造プロセスが簡略になり、エツチン
グによる汚染が減少して半導体装置の歩留りが向上する
。次に図面に従つて本発明を詳細に説明する。
Since patterning by etching is performed after the first metal is diffused and absorbed into the second metal, a metal that is difficult to etch 35 can be used as the first metal. Furthermore, since the first and second metals can be etched at once, the manufacturing process is simplified, contamination due to etching is reduced, and the yield of semiconductor devices is improved. Next, the present invention will be explained in detail with reference to the drawings.

図a−eは本発明の一実施例の半導体装置の製造方法を
示す工程図である。図aに示すように、単結晶シリコン
基板1の表面にコンタクト用窓3を有する絶縁膜2を形
成し、つづいてチタン、白金、コバルト、金、銀、銅、
クロム、モリブデン等のコンタクト用金属を蒸着して5
0〜200Aの金属膜4を形成する。
Figures a to e are process diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIG.
Contact metals such as chromium and molybdenum are vapor-deposited 5
A metal film 4 of 0 to 200 A is formed.

コンタクト用金属は上記の金属のうちいずれの金属を用
いてもよく、あるいはこれらの金属群から選ばれた二種
類以上の金属を組合せて用いてもよい。次に350〜6
50℃の温度で熱処理をすると、図bに示すようにコン
タクト窓の部分に金属シリサイド5が形成される。続い
てアルミニウムのような配線用金属層6を1〜3μmの
厚さに被着する(図c)。
The contact metal may be any of the metals listed above, or a combination of two or more metals selected from these metal groups. Next 350-6
When heat treatment is performed at a temperature of 50° C., metal silicide 5 is formed in the contact window portion as shown in FIG. b. A wiring metal layer 6, such as aluminum, is then applied to a thickness of 1 to 3 .mu.m (FIG. c).

次に、200〜600℃の温度で1〜10分間熱処理し
て、金属シリサイドに変化していないコ ニンタクト用
金属膜4を配線用金属層6に拡散吸収させる(図d)。
Next, heat treatment is performed at a temperature of 200 to 600° C. for 1 to 10 minutes to diffuse and absorb the contact metal film 4, which has not changed into metal silicide, into the wiring metal layer 6 (FIG. d).

最後に選択的エツチングをして、所望の形状の電極配線
パターンとする(図e)。
Finally, selective etching is performed to obtain the desired shape of the electrode wiring pattern (Figure e).

金属シリサイドを形成するための熱処理と、配 二線用
金属層6にコンタクト用金属を拡散吸収するための熱処
理とを単一の熱処理ですませることも考えられるが、そ
の場合には配線用金属層6によつてアロイスパイクが出
来る前に金属シリサイドが形成される必要があり、した
がつてコンタクト用金属膜4の膜厚及び熱処理の温度、
時間等を十分に管理する必要があるので好ましくはない
It is conceivable that the heat treatment for forming metal silicide and the heat treatment for diffusing and absorbing the contact metal into the wiring metal layer 6 can be performed in a single heat treatment. 6, it is necessary to form metal silicide before the alloy spike is formed. Therefore, the thickness of the contact metal film 4 and the temperature of the heat treatment,
This is not preferable because it requires sufficient time management.

以上の説明によつて明らかなように、本発明の半導体装
置の製造方法によればエツチングの困難なコンタクト用
金属を、配線用金属に拡散吸収させてから電極配線パタ
ーンを形成するためのエツチングをするので、エツチン
グ工程が容易かつ簡略となるのみならず、コンタクト用
金属膜の被着、金属シリサイド化のための熱処理、配線
用金属の被着および該配線用金属に金属シリサイドに変
化していないコンタクト用金属を拡散吸収させる工程と
を蒸着装置内で行うことができ、汚染による性能劣化や
歩留りの低下という問題は大幅に改善される。なお、配
線用金属は少量のコンタクト用金属を吸収しているわけ
であるが、そのために電気抵抗が増大する現象は認めら
れない。
As is clear from the above description, according to the method for manufacturing a semiconductor device of the present invention, contact metal, which is difficult to etch, is diffused and absorbed into wiring metal, and then etching is performed to form an electrode wiring pattern. This not only simplifies and simplifies the etching process, but also ensures that the contact metal film is not deposited, the heat treatment is performed to convert the metal into a metal silicide, the wiring metal is deposited, and the wiring metal does not change into metal silicide. The process of diffusing and absorbing the contact metal can be performed within the vapor deposition apparatus, and the problems of performance deterioration and yield reduction due to contamination can be significantly improved. Note that although the wiring metal absorbs a small amount of the contact metal, no phenomenon in which the electrical resistance increases due to this is observed.

【図面の簡単な説明】[Brief explanation of the drawing]

図a−eは各々本発明の一実施例の半導体装置の製造方
法を示す工程順断面図、である。 なお図において、1・・・単結晶シリコン基板、2・・
・絶縁膜、3・・・コンタクト用窓、4・・・コンタク
ト用金属膜、5・・・金属シリサイド、6・・・配線用
金属層、である。
Figures a to e are cross-sectional views in the order of steps, each showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 1... single crystal silicon substrate, 2...
- Insulating film, 3... window for contact, 4... metal film for contact, 5... metal silicide, 6... metal layer for wiring.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板上に開口を有する絶縁膜を設ける工程と
、該絶縁膜上及び該開口内に第1の金属を被着する工程
と、該開口の部分の前記半導体基板に金属シリサイドを
形成する工程と、しかる後に前記第1の金属上に第2の
金属を被着する工程と、前記第1の金属を前記第2の金
属に拡散吸収させた後にエッチングによつて所望形状の
電極配線を形成する工程とを含むことを特徴とする半導
体装置の製造方法。
1. A step of providing an insulating film having an opening on a semiconductor substrate, a step of depositing a first metal on the insulating film and in the opening, and a step of forming metal silicide on the semiconductor substrate in the area of the opening. Then, a step of depositing a second metal on the first metal, and forming an electrode wiring in a desired shape by etching after diffusing and absorbing the first metal into the second metal. A method for manufacturing a semiconductor device, comprising the steps of:
JP50035064A 1975-03-24 1975-03-24 Manufacturing method of semiconductor device Expired JPS5912010B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50035064A JPS5912010B2 (en) 1975-03-24 1975-03-24 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50035064A JPS5912010B2 (en) 1975-03-24 1975-03-24 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS51110265A JPS51110265A (en) 1976-09-29
JPS5912010B2 true JPS5912010B2 (en) 1984-03-19

Family

ID=12431580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50035064A Expired JPS5912010B2 (en) 1975-03-24 1975-03-24 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5912010B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057704B2 (en) * 1979-05-25 1985-12-16 日本電気株式会社 Manufacturing method of semiconductor device
JPS60206022A (en) * 1984-03-30 1985-10-17 Fujitsu Ltd Generation of high melting point metal silicide

Also Published As

Publication number Publication date
JPS51110265A (en) 1976-09-29

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