JPH02203623A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To attain an analog digital converter having a highly accurate converting characteristic even at high clock speed by so constituting the converter that outputs of comparators connected in parallel are given to a 4-input AND, in which they are ANDed and giving the resulting signal to an encoder thereby correcting an error output of the comparator. CONSTITUTION:The title converter consists of (2<n>-1) comparators C1-C7 connected in parallel, (2<n>-1) AND gates AND1-AND7 and an encoder 2 and a noninverting output of (i-1)th and i-th comparators and an inverting output of (i+1)-th and (i+2)th comparators are inputted to the i-th AND gate. Since an analog input level is decided when the logic output arrangement of the four comparators C1-C7 adjacent to each other is 0011, and when only one output error of the comparators C1-C7 takes place at a location deviated by + or -2 quantization unit with respect to the analog input level, completely correct conversion result is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an analog-to-digital converter, which is the most important among signal processing circuits.

BACKGROUND OF THE INVENTION In recent years, signal processing technology has improved dramatically due to significant advances in semiconductor integration technology. Among them, the analog-to-digital converter is one of the most important signal processing circuits.

An example of the conventional analog-to-digital converter mentioned above will be described below with reference to the drawings.

FIG. 3 shows the configuration of a conventional 3-bit analog-to-digital converter. In FIG. 3, 01 to C7 are comparators, the input terminals are connected to the analog input terminal 1 of ■, and the input terminals of e are the reference voltage terminals V
rsfl-Vref7, and its outputs are two human-powered AND gates A N D + ~ AND7, respectively.
connected to. Here, the n-th two-person logical AND gate A
ND0 takes the AND of the positive phase output of the comparator Cn and the negative phase output of the comparator Cn+1. However, the seventh comparator receives only the positive phase output of the comparator C7.

2 is an encoder with 7 AND gates AND+ ~AN
D? Encode the output of . bO-bl and b2 are 3-bit digital outputs.

The operation of the analog-to-digital converter configured as described above will be explained below.

First, analog input voltages applied to terminal 1 are simultaneously compared by seven comparators Ct-C7. The outputs of comparators C1 to C7 are the two-person AND+=AND7
As a result, only one of the seven AND outputs becomes 1", and the analog input level is determined. The encoder 2 converts the determined analog input level into b(1), such as a binary code. , bl, b2.

Problems to be Solved by the Invention However, in the above configuration, the 8 types of output states of the 7 comparators are directly mapped to 23 binary codes, so even one comparator may cause an error output due to noise etc. If it is output, the conversion output will be visible if it is output at all. When the clock speed is several hundred MHz or higher,
There is a problem in that error outputs are often generated due to noise generated by the comparator itself, uneven AC characteristics of the comparator, etc., and correct conversion output cannot be obtained.

In view of the above problems, the present invention provides an analog-to-digital converter that can provide a correct binary conversion output up to one error output even if the comparator generates an error output due to noise or the like.

Means for Solving the Problems In order to solve the above problems, the analog-to-digital converter of the present invention consists of (2n-1) comparators, (2n-1) AND gates, and encoders connected in parallel. The positive-phase outputs of the (i-1)-th and i-th comparators and the (i+1)-th
It has a configuration in which the opposite phase outputs of the th and (i+2)th comparators are input.

Effect of the Invention With the above-described configuration, the present invention determines the analog input level at the location where the logical output array of four adjacent comparators is 0011, so that the output error of the comparator is less than ±2 quantization units with respect to the analog input level. If only one occurs in an out-of-place position, a completely correct conversion result will be obtained.

Embodiment Hereinafter, an analog-to-digital converter according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a 3-bit analog-to-digital converter in an embodiment of the present invention. In Figure 1, c and -C7 are comparators, ■ is an analog input terminal, and V rel~V
re47 is the reference voltage terminal, 2 is the encoder, bo-b=
is a digital output terminal, and the above structure is the same as that shown in FIG. AND+ to AND7 are AND gates, among which ANDt to ANDs are AND gates, AND takes the AND of the positive phase outputs of the comparator C1 and the comparator C1-1 and the negative phase outputs of the comparator CH+1 and the comparator CH+2. That is, A N D1= Ci ” C1-1'C++l'
C1+ but i=2 to 5, and for other AND gates, AND, =C, -C2・C3+ ANDe=Cs・C6・C7T AND? =C8・C7.

The operation of the analog-to-digital converter configured as above will be explained below.

First, FIG. 2 shows the conversion result when an error occurs in one comparator when comparators C1 to C5 have 1 output and 04 to C7 have 0 output for a certain analog input voltage. Out of the seven types of errors that occur, it is possible to correct up to three types of errors, and you can see how you can perform correct conversion. The other four types are modes in which error correction is not possible in principle, or two types of correction are possible, and correct conversion cannot be performed.

Conventional analog-to-digital converters do not perform correct conversion for all error modes. The above effects are 4
It has been shown that by performing a manual logical product, it is possible to correct a comparator error when it occurs at a location farther away than ±2ffi conversion units with respect to the analog input.

In the analog-to-digital converter of the present invention, 23x (2'-
1)=56 ways for one error state of a comparator,
It can be confirmed by performing a logic check as shown in FIG. 2 that all 30 errors can be converted correctly.

As described above, according to this embodiment, after the comparator,
By providing a four-man power AND gate to determine the level of the analog input voltage, an analog-to-digital converter capable of error correction for a single comparator error can be realized.

Note that although a 3-bit analog-to-digital converter is shown in the embodiment, in the case of 3 or more bits, the comparator C
This can be realized by increasing the number of AND gates 1 to C7 and AND gates AND+ to AND7.

Effects of the Invention As described above, the present invention has a configuration in which the outputs of the comparators connected in parallel are logically multiplied by four people and then inputted to the encoder, thereby correcting the error output of the comparator, and achieving high precision even at high clock speeds. It is possible to realize an analog-to-digital converter having the following conversion characteristics.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention, Fig. 2 is a diagram explaining the operation of the embodiment of the present invention, and Fig. 3 is a block diagram of a conventional analog-to-digital converter. be. 1... Analog input terminal, 2... Encoder, c, c 7-°-゛- comparator, V
rsfl −Vref7°゛°°°゛Reference voltage, AND
I-AND?・・・・・・AND gate, bo-b2・
...Digital output. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (1)

[Claims] It consists of n comparators that share an analog input, n AND gates that receive the output of the comparators, and an encoder that converts it into a digital code. An analog-to-digital converter, characterized in that the positive phase outputs of the ith and ith comparators and the negative phase outputs of the (i+1)th and (i+2)th comparators are input.