KR20000004486A - Analog-digital converter - Google Patents

Abstract

PURPOSE: An analog-digital converter is provided to improve the reliability of converting and economical efficiency. CONSTITUTION: The analog-digital converter comprises: a plurality of resistors(31) serially connected each other so as to generate a plurality of threshold voltages between Vfs and VSS; a first comparing portion(32) for outputting a first digital code by simultaneously comparing the each threshold voltage and an input analog voltage; an upper bit processing portion(36) for determining upper bits by receiving an output of the first comparing portion; a second comparing portion(33) for outputting a second digital code by comparing the input analog voltage and an external VD/A; a SAR portion(34) including the upper bit processing portion, and for outputting a final digital code including the determined upper bits after storing the second digital code; and D/A converting portion(35) for outputting the VD/A by receiving a digital code stored in the SAR portion.

Description

Analog / digital converter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to analog-to-digital (A / D) converters, and more particularly to an A / D converter that improves the reliability and economics of conversion.

1 is a block diagram showing a conventional SAR type A / D converter, Figure 2 is a block diagram showing a conventional flash type A / D converter.

A conventional SAR (Successive Approximation Register) type A / D converter has a first comparator 11, a SAR unit 12, a D / A converter 13, and a clock unit 21 as shown in FIG. It consists of.

Here, the SAR unit 12 receives the digital code of the first comparison unit 11 and the clock of the clock unit 21 as a sequential comparison register, stores the digital code, and stores the final digital code to the outside. Output.

The D / A converter 13 receives the digital code of the SAR unit 12 and decodes the digital code to output V _{D / A} to the first comparator 11.

The first comparator 11 has the V _{D / A} connected to a negative terminal and an analog voltage Va, an analog input signal, connected to a positive terminal to be compared with the V _{D / A.} Op Amp (Operational Amplifier) is configured to compare the V _{D / A} and Va and output a digital code.

Referring to the operation of the conventional SAR type A / D converter as described above is as follows.

First, the digital code of the SAR unit 12 is 100 ... 000 (N pieces), and this value is converted into the first V _{D / A which} is an analog voltage by using the D / A converter 13.

Subsequently, when the first V _{D / A} and Va are compared by the first comparator 11, a high or low value is obtained.

In other words, when the first V _{D / A} is large compared to the Va is high, on the contrary, when the first V _{D / A} is small compared to the Va is low.

If the output of the first comparator 11 is high, the most significant bit of the SAR unit 12 is stored as 0, and if it is low, the most significant bit of the SAR unit 12 is stored as 1.

In this case, when the output of the first comparator 11 is low, the value of the digital code of the SAR unit 12 is 100.000, and if the output of the first comparator 11 is high, the SAR The value of the digital code of the part 12 is 000 ... 000.

The next bits then repeat the same operation to determine a value of zero or one.

Determining the value of the least significant bit (LSB) determines the digital value for the analog input signal.

In another conventional flash type A / D converter, as shown in FIG. 2, a resistance string 14 having 2 ⁿ resistors connected in series between Vfs (fs: full scale) and VSS in converting an analog input signal into n-bit digital is shown. And a second comparator 15, and a coder (priority encoder) 16 first.

Here, the second comparator 15 has Vfs, which is an analog input signal connected to both terminals, and a threshold voltage between the resistors of the resistance string 14 at equal intervals as a comparison voltage to be compared with Va at the negative terminal. It is composed of 2 ⁿ -1 Op Amp connected to compare Vfs and Va and output a digital code.

The operation of the flash-type A / D converter of another conventional example as described above is as follows.

When the Va is simultaneously applied to a plurality of Op Amps of the second comparator 15, the Op Amp to which Vfs higher than Va is connected outputs a low output, that is, 0 to the priority encoder 16, and Vfs lower than Va. Op Amp connected to outputs a high output, that is, 1 to the priority encoder 16.

The priority encoder 16 then combines the outputs of the second comparator 15 to determine the final digital output.

However, the conventional A / D converter has a problem of lowering the conversion reliability and economics as follows.

First, since the SAR-type A / D converter determines one n-bit value every one clock period, the n-bit conversion time is n × clock period, which requires a lot of time.

Second, the flash type A / D converter requires 2 ⁿ -1 converters for n-bit conversion, resulting in a larger chip size, a complexity of priority encoders for 2 ⁿ -1 signal processing for n-bit conversion, and a high precision of SAR. It is worse than type A / D converter.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and consists of a resistor string and a first comparator of a flash type A / D converter and a second comparator, a SAR part and a D / A converter of a SAR type A / D converter. The object is to provide an A / D converter that improves the reliability and economics of the conversion.

1 is a block diagram showing a conventional SAR type A / D converter

Figure 2 is a block diagram showing another conventional flash type A / D converter

3 is a block diagram illustrating an A / D converter according to an embodiment of the present invention.

4 is a block diagram illustrating a SAR unit of an A / D converter according to an embodiment of the present invention.

5 is a circuit diagram for determining a most significant bit and a next higher bit of an A / D converter according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

31: resistance row 32: first comparison unit

33: second comparison unit 34: SAR unit

35: D / A converter 36: upper n / 2 bit processor

37: lower n / 2-bit processor 39: clock unit

41: first inverter 42: second inverter

43: first transfer gate 44: second transfer gate

The A / D converter according to the present invention outputs a first digital code by simultaneously comparing a resistance string consisting of a plurality of series resistors, a plurality of series resistors, and each of the threshold voltages and an input analog voltage to generate a plurality of threshold voltages between Vfs and VSS. A first comparator, an upper bit processor configured to receive outputs of the first comparator, and determine higher bits, a second comparator configured to compare the input analog voltage with an external V _{D / A} and output a second digital code; A SAR unit which includes a bit processing unit and stores the second digital code and outputs a final digital code including the determined upper bits to the outside; and _{D which} receives the digital code stored in the SAR unit and outputs the V _{D / A.} It comprises a / A converter unit.

Referring to the preferred embodiment of the A / D converter according to the present invention as described above in detail with reference to the accompanying drawings as follows.

3 is a block diagram illustrating an A / D converter according to an embodiment of the present invention, FIG. 4 is a block diagram showing a SAR unit of an A / D converter according to an embodiment of the present invention, and FIG. 5 is an embodiment of the present invention. Is a circuit diagram for determining the most significant bit and the next higher bit of the A / D converter.

In the A / D converter according to the embodiment of the present invention, as shown in FIG. 3, the resistor string 31, the first comparator 32, and the SAR of the flash-type A / D converter when converting an analog input signal into n-bit digital. A second comparator 33, a SAR unit 34, a D / A converter 35, and a clock unit 39 of the type A / D converter.

Here, the resistor string 31 is composed of 2 ^{n / 2} resistors connected in series between Vfs and VSS to divide Vfs into 2 ^{n / 2} -1 threshold voltages, and the first comparator 32 to both terminals analog input signal is an analog voltage (Va) is connected and the second to the negative terminal is the threshold voltage of Vfs between resistance that is the resistance heating (31) of the same spacing is connected to the comparison voltage compared to the Va ^{n / 2} - It consists of one Op Amp and compares Vfs and Va and outputs a digital code.

The SAR unit 34 is a sequential comparison register. The SAR unit 34 includes an upper n / 2-bit processor 36 and a lower n / 2-bit processor 37 as shown in FIG. 4. The digital codes of 32 and 33 and the clock of the clock unit 39 are inputted to store the digital codes and output the final digital codes to the outside.

The D / A converter 35 receives the digital code of the SAR unit 34 and decodes the digital code to output V _{D / A} to the second comparator 33.

The second comparison part 33 is the V _{D / A} are connected to the negative terminal and is composed of one of Op Amp is the V _{D / A} as the comparison voltage of Va to compare connected to both terminals the V _{D / A} and Va Compare and print the digital code.

Referring to the operation of the A / D converter according to an embodiment of the present invention configured as described above are as follows.

Of the analog signal by one clock, first through the n / 2-bit flash type A / D converter, the first comparison part 32 input during conversion to an analog input signal n bit digital, A / D converter 2 ^{n / 2 n / 2} -1 logic signals compared at ² -1 Op Amp are input to the SAR unit 34.

In addition, the SAR unit 34 combines the 2 ^{n / 2} -1 logic signals input from the flash type A / D converter into n / 2 bits in the upper n / 2 bit processing unit 36, and the combined n The / 2 bit is set to the upper n / 2 bits in the SAR unit 34.

The combination of the most significant bit (MSB) and the next higher bit in the upper n / 2 bit processor 36 is the first comparator 32 through two first inverters 41, as shown in FIG. Is determined by the output of W 2 ^{n / 2-1} -1, and the next higher bit is opposite to the output W 2 ^{n / 2-1} -1 of the first comparator 32 by the second inverter 42, respectively. Output W (2 ^{n / 2-1} ) of the first comparator 32 depending on whether the first and second transfer gates 43 and 44 that are input in the state are turned on. -2 ^{n / 2-2} ) or W (2 ^{n / 2-1} +2 ^{n / 2-2} ).

Subsequently, in the state where the upper n / 2 bits are determined, the lower most significant bit is set to 1 and the remaining bits are set to 0 in the lower n / 2 bit processor 37 to determine n-bit digital code values.

The digital code determined by the lower n / 2-bit processor 37 is inputted to the D / A converter 35 and outputs V _{D / A} corresponding to the value to output Va and the second comparator 33. ) To determine the n / 2-1th bit value.

Subsequently, the above n / 2-bit processing unit 37 repeats the above process n / 2 times, thereby determining a digital value of n bits for the analog input signal.

The A / D converter of the present invention is composed of a resistor string and a first comparator of a flash type A / D converter and a second comparator, a SAR part, and a D / A converter of a SAR type A / D converter to convert an analog input signal to n. When converting to bit digital, the upper n / 2 bits use flash type A / D converters and the lower n / 2 bits use SAR type A / D converters, which reduces the time required for SAR type A / D converters. In the A / D converter, less converters are required than in the prior art, thereby reducing the size of the chip and improving the accuracy of the conversion, thereby improving the reliability and economic efficiency of the conversion.

Claims (3)

A resistor string comprising a plurality of series resistors such that a plurality of threshold voltages are generated between Vfs and VSS; A first comparator for simultaneously comparing the respective threshold voltages and the input analog voltages and outputting a first digital code; An upper bit processor configured to receive outputs of the first comparator and determine upper bits; _A second comparing unit comparing the input analog voltage with an external V _{D / A} and outputting a second digital code; A SAR unit including the upper bit processing unit and storing the second digital code and outputting a final digital code including the determined upper bit to the outside; And a D / A converter for receiving the digital code stored in the SAR and outputting the V _{D / A.} The method of claim 1, The SAR unit comprises an upper bit processing unit and a lower bit processing unit. The method of claim 1, The upper bit processing unit includes two first inverters for determining the most significant bit and first and second transfer gates receiving the most significant bit in opposite states by a second inverter to determine the next higher bit. A / D converter, characterized in that.