JPS6448522A - All parallel a/d converter - Google Patents

Abstract

PURPOSE:To prevent generation of a coding mistake of an A/D converter due to external noise by providing a logic gate processing each output of plural comparators to the pre-stage of an encoder. CONSTITUTION:When two or more outputs of three consecutive comparators (N-1, N, N+1) of a comparator group 10 go to logic level '1', a logic gate group 20A outputs logic level '1'. The logic output of [2-3] sets of the logic gate group 20A and the output being the output (in total [2-1] set) of a first comparator 1 of the comparator 10 and a final comparator 2-1 are fed to a '001' conversion circuit 20B, and an encoder 20 is provided to code the result of the circuit 20B into n-bit digital signal with less code error. Thus, even when there is a difference from a delay time or noise in each comparator of the comparator group in parallel operation of 2-1 sets of comparators, the total parallel A/D converter with n-bit is realized, where the probability of production of coding mistake in the output is small.