JPH02203595A - Multilayered wiring board - Google Patents

Multilayered wiring board

Info

Publication number
JPH02203595A
JPH02203595A JP1020706A JP2070689A JPH02203595A JP H02203595 A JPH02203595 A JP H02203595A JP 1020706 A JP1020706 A JP 1020706A JP 2070689 A JP2070689 A JP 2070689A JP H02203595 A JPH02203595 A JP H02203595A
Authority
JP
Japan
Prior art keywords
power supply
section
wiring board
supply layers
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1020706A
Other languages
Japanese (ja)
Inventor
Bunichi Tagami
田上 文一
Bunichi Fujita
文一 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1020706A priority Critical patent/JPH02203595A/en
Publication of JPH02203595A publication Critical patent/JPH02203595A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To reduce noise from a multilayered printed board by making distances between an element and power supply layers shorter so as to reduce inductance components and, at the same time, forming an insulating layer of a thin film section so as to reduce conductor intervals between the pairs of power supply layers. CONSTITUTION:A multilayered wiring board 10 composed of a thin film section 11 and thick film section 12 is formed against an integrated circuit element 1. Power supply layers 111 and 112 are arranged in the section 11 adjacent to the main surface side of the section 11 and power supply layers 121 and 122 are provided in the section 12. In addition, through holes for power supply 20 and signals 30 are provided. In order to reduce inductance components by making the distances between the element 1 and power supply layers shorter, the power supply layer pairs 111 and 112 and 121 and 122 are formed adjacent to an element 1 mounting surface by means of the section 11 and, at the same time, an insulating layer is formed of the section 11. Therefore, conductor intervals between the power supply layer pairs can be reduced extensively and the coupling between the power supply layers can be strengthened, resulting in an increase in electrostatic capacity. Thus noise can be reduced from the multilayered printed board.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路素子などの電子部品を実装する多層
配線基板に関し、特に高速素子を実装するに好適な多層
配線基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring board on which electronic components such as integrated circuit elements are mounted, and particularly to a multilayer wiring board suitable for mounting high-speed elements.

〔従来の技術〕[Conventional technology]

従来の多層配線基板は、特開昭58−111396号公
報に記載のように、グリーンシート積層法によるセラミ
ック多層配線基板において、特定の導体層間の絶縁体層
を印刷法により形成し該導体層間厚をグリーンシート積
層部に比べて薄くし導体眉間の静電容量の増大を図った
ものが挙げられる。
A conventional multilayer wiring board is a ceramic multilayer wiring board using a green sheet lamination method, as described in JP-A-58-111396, in which an insulator layer between specific conductor layers is formed by a printing method, and the thickness between the conductor layers is adjusted. One example is one in which the conductor is made thinner than the green sheet laminated part to increase the capacitance between the conductor's eyebrows.

上記発明は、多層配線基板に実装した集積回路素子の動
作により生じる電源電位の変動を抑えるべくなされたも
のである。
The above invention was made in order to suppress fluctuations in power supply potential caused by the operation of integrated circuit elements mounted on a multilayer wiring board.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術においては、集積回路素子から該導体層対
に至る経路の長さ及び導体層対を形成す+電源層につい
て十分に配慮されておらず、特に高速素子を搭載する場
合には問題があった。
In the above-mentioned conventional technology, sufficient consideration is not given to the length of the path from the integrated circuit element to the conductor layer pair and the power supply layer forming the conductor layer pair, which poses a problem especially when high-speed elements are mounted. there were.

すなおち、素子が高速動作を行うため信号の切替り時間
が短くなり高周波成分を多量に含むようになってきたた
め、素子から電源層に至る経路のインダクタンス成分が
無視できなくなり、電源層間に十分な静電容量を確保し
ても有効に鋤かない状況が生じてしまった。また、変動
電流が閉回路を形成する各電源が別々に離れて配置され
ると変動電流により誘導されるノイズが該電源層に隣接
する導体層に悪影響を及ぼし装置の誤動作を生じさせる
問題があった。
In other words, as devices operate at high speeds, the switching time of signals becomes shorter and they begin to contain large amounts of high-frequency components.As a result, the inductance component of the path from the device to the power layer can no longer be ignored, and sufficient space between the power layers is required. A situation has arisen in which plowing cannot be done effectively even if the capacitance is secured. Furthermore, if the power supplies whose fluctuating currents form a closed circuit are placed separately and separately, the noise induced by the fluctuating currents may adversely affect the conductor layer adjacent to the power supply layer, causing equipment malfunction. Ta.

本発明の目的は上記問題点に鑑み、上記インダクタンス
の低減及び誘導ノイズの低減をすることにある。
SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to reduce the inductance and induced noise.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、従来交流特性まで含めた考
慮が十分にされていなかった電源層配置に着目し変動電
流のソース及びシフトとなる電源対をなす導体層対を隣
接させかつ集積回路素子を搭載する主表面近傍に配置し
たものである。
In order to achieve the above objective, we focused on the power supply layer arrangement, which had not been sufficiently considered in the past, including AC characteristics, and placed the conductor layer pairs that form the power source pair, which serves as the source and shift of the fluctuating current, adjacent to each other, and integrated circuit elements. It is placed near the main surface on which it is mounted.

〔作用〕[Effect]

素子動作により生じる変動電流は、素子と電源層間を接
続するスルーホールなどに流れ、このときスルーホール
部のインダクタンスにより素子と電源層間の電位差が生
じる。とくに素子の切替速度が速くなると電位差が顕著
になり無視できなくなる。本発明のごとく、当該電源層
を素子を搭載する主表面近傍に配置することで、スルー
ホール部のインダクタンスが低減でき高速素子の変動電
流により生じる電位差も十分小さくできる。
A fluctuating current generated by element operation flows through a through hole or the like that connects the element and the power supply layer, and at this time, a potential difference occurs between the element and the power supply layer due to the inductance of the through hole portion. In particular, as the switching speed of the elements increases, the potential difference becomes significant and cannot be ignored. By arranging the power supply layer near the main surface on which the element is mounted as in the present invention, the inductance of the through-hole portion can be reduced and the potential difference caused by the fluctuating current of the high-speed element can be sufficiently reduced.

また、変動電流のソースとシンクとなる電源には逆方向
で同量の電流変化が生じるため、これらの電源を対にし
て隣接し電気的結合を強−めることで変動電流により生
じる電位変動が時間的及び場所的共に局所的に収束する
ため、これら電源層に隣接する導体へ誘導するノイズ及
びこれら電源層内で遠方に伝わるノイズを小さくするこ
とができる。
In addition, since the same amount of current changes in opposite directions in the power supplies that are the source and sink of the fluctuating current, the potential fluctuations caused by the fluctuating current can be suppressed by pairing these power supplies and placing them adjacent to each other to strengthen electrical coupling. Since the noise is locally converged in both time and space, it is possible to reduce noise induced into conductors adjacent to these power supply layers and noise transmitted over long distances within these power supply layers.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図により説明する。1は
集積回路素子、10は多層配線基板であり11は薄膜部
12は厚膜部を示す。111と112は薄膜部の主表面
側に隣接して配置した電源層、121と122は厚膜部
に設けた電源層である。20は電源用スルーホール、3
0は信号用スルーホール、40は外部接続用のパッドを
示す。
An embodiment of the present invention will be described below with reference to FIG. 1 is an integrated circuit element, 10 is a multilayer wiring board, and 11 is a thin film portion 12 is a thick film portion. Reference numerals 111 and 112 indicate power supply layers disposed adjacent to the main surface side of the thin film portion, and reference numerals 121 and 122 indicate power supply layers provided in the thick film portion. 20 is a power supply through hole, 3
0 indicates a signal through hole, and 40 indicates a pad for external connection.

本実施例では、薄膜により電g層対を作成し素子搭載面
に隣接して配置してあり、素子と電源層間の距離を短く
しインダクタンス成分の減少を図ると共に、薄膜により
絶縁層を形成したことで、電源層対間の導体間隔を非常
に/hさくすることが可能となり、電源層間の結合を強
固にし静電容量の増大が図れる。
In this example, a pair of electric g layers are made of a thin film and placed adjacent to the element mounting surface, thereby shortening the distance between the element and the power layer to reduce the inductance component, and forming an insulating layer with the thin film. This makes it possible to make the conductor spacing between the pair of power supply layers extremely small, thereby making it possible to strengthen the coupling between the power supply layers and increase the capacitance.

第2図は、ECL回路の基本的な回路を示したものであ
る。回路素子としてECLを使用した場合には、論理動
作により変動電流が生じるエミッタフォロワ一部の電源
対を前述の電源対にすることがよい。
FIG. 2 shows the basic circuit of the ECL circuit. When an ECL is used as a circuit element, it is preferable to use the above-mentioned power supply pair as a part of the power supply pair of the emitter follower in which a fluctuating current is generated due to a logic operation.

本実施例では、シングルチップのキャリアを示したが、
マルチチップモジュール用の多層配線基板に適用きるこ
とは明らかである。
In this example, a single-chip carrier was shown, but
It is clear that the invention can be applied to multilayer wiring boards for multichip modules.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、集積回路素子と電源層間のインダクタ
ンスを低減できるので、スルーホール部に生じる電位差
を小さくできノイズ低減に効果がある。また、変動電流
により生じる互いに逆方向のノイズを局在的に打消し合
うことができるのでノイズの低減に効果がある。
According to the present invention, since the inductance between the integrated circuit element and the power supply layer can be reduced, the potential difference generated in the through-hole portion can be reduced, which is effective in reducing noise. In addition, noise in opposite directions caused by fluctuating currents can be locally canceled out, which is effective in reducing noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図、第2図はECL素
子の基本回路図である。 1・・・集積回路素子、10・・・多層配線基板、11
・・・薄膜部、     12・・・厚膜部。 111、 112. 121. 122・・・電源層、
20、30・・・スルーホール、 40・・・パッド。
FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a basic circuit diagram of an ECL element. DESCRIPTION OF SYMBOLS 1... Integrated circuit element, 10... Multilayer wiring board, 11
... Thin film part, 12... Thick film part. 111, 112. 121. 122...power layer,
20, 30...through hole, 40...pad.

Claims (1)

【特許請求の範囲】[Claims] 1.複数の導体層を絶縁体層を介在させて積層し一体化
して成る多層配線基板において、特定の導体層を隣接し
て積層し、該導体層対を多層配線基板の集積回路素子を
搭載する主表面近傍に配置したことを特徴とする多層配
線基板。
1. In a multilayer wiring board formed by laminating and integrating a plurality of conductor layers with insulating layers interposed therebetween, specific conductor layers are laminated adjacently, and the conductor layer pair is used as the main body on which the integrated circuit element of the multilayer wiring board is mounted. A multilayer wiring board characterized by being arranged near the surface.
JP1020706A 1989-02-01 1989-02-01 Multilayered wiring board Pending JPH02203595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1020706A JPH02203595A (en) 1989-02-01 1989-02-01 Multilayered wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1020706A JPH02203595A (en) 1989-02-01 1989-02-01 Multilayered wiring board

Publications (1)

Publication Number Publication Date
JPH02203595A true JPH02203595A (en) 1990-08-13

Family

ID=12034589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1020706A Pending JPH02203595A (en) 1989-02-01 1989-02-01 Multilayered wiring board

Country Status (1)

Country Link
JP (1) JPH02203595A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515324B2 (en) 2000-09-08 2003-02-04 Nec Corporation Capacitor, capacitor mounting structure, method for manufacturing same, semiconductor device, and method for manufacturing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6515324B2 (en) 2000-09-08 2003-02-04 Nec Corporation Capacitor, capacitor mounting structure, method for manufacturing same, semiconductor device, and method for manufacturing same

Similar Documents

Publication Publication Date Title
JP2738590B2 (en) Capacitor laminate for printed wiring boards
EP0379686B1 (en) Printed circuit board
KR101522786B1 (en) Multilayered substrate and method of manufacturing the same
JPH065847A (en) Semiconductor power module
JP2004235629A (en) High-speed performance printed circuit board and manufacturing method therefor
US6618266B2 (en) Method for high-density, low-via-count, decoupling capacitor placement
JPH07135376A (en) Composite printed-circuit board and its manufacture
JPH1197810A (en) Circuit board
JP3252635B2 (en) Multilayer electronic components
JPH02203595A (en) Multilayered wiring board
JPS61131498A (en) Wiring structure of termination circuit
JPH0786754A (en) Laminated hybrid integrated circuit component
JPS63170988A (en) Hybrid integrated circuit
US20040211954A1 (en) Compositive laminate substrate with inorganic substrate and organic substrate
JPH06244305A (en) Multi-chip module
JP3591894B2 (en) Multilayer printed circuit board
JPH05167265A (en) High speed signal printed wiring board
JP2000151306A (en) Semiconductor device
JPH0638300U (en) Switching power supply circuit board
JP2006261213A (en) Electronic circuit
KR100275376B1 (en) Multylayer printed circuit board
JPH0576783B2 (en)
JPS60233881A (en) Printed circuit board
JPS62119964A (en) Composite circuit device
JP2000031608A (en) Printed wiring board