JPH02203567A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPH02203567A
JPH02203567A JP2079589A JP2079589A JPH02203567A JP H02203567 A JPH02203567 A JP H02203567A JP 2079589 A JP2079589 A JP 2079589A JP 2079589 A JP2079589 A JP 2079589A JP H02203567 A JPH02203567 A JP H02203567A
Authority
JP
Japan
Prior art keywords
semiconductor layer
electrode
thin film
film transistor
laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2079589A
Other languages
Japanese (ja)
Inventor
Yuko Hiura
樋浦 祐子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2079589A priority Critical patent/JPH02203567A/en
Publication of JPH02203567A publication Critical patent/JPH02203567A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To manufacture in a short time a semiconductor device by laser CVD by a method wherein a semiconductor layer is arranged between a source electrode and a drain electrode, and the semiconductor layer comes into contact with each electrode, only through the side wall part. CONSTITUTION:Firstly, a chromium film is patterned on a glass substrate 6, thereby forming a drain electrode 1 and a source electrode 2. Patterning is performed by plasma CVD method. A semiconductor layer 4 is formed in the gap between the electrodes 1 and 2, in the manner in which the length in the gap direction becomes equal to the gap width. After a gate insulating film 5 is formed, a gate electrode 3 is formed thereon and a thin film pattern is obtained. The semiconductor layer 4 comes into contact with the electrodes 1 and 2 only through the side wall part, so that direct laser irradiation on the electrode surface is unnecessitated, and highly intense laser light irradiation is enabled. As a result, a thin film can be formed in a short time by laser CVD.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は薄膜トランジスタに関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistors.

[従来の技術およびその課題] 製作工程が逆スタガ型薄膜トランジスタより少なくてす
む類スタガ型薄膜トランジスタの製作においては、ドレ
イン、ソース各金属電極を形成した後、ドレイン、ソー
ス電極の一部を覆う形状で両電極間に半導体層を形成し
ていた。このような構造の半導体層を直接パターン化し
たレーザ光を照射して形成する方法が著者らにより19
88年第49回応用物理学会講演予稿集、534頁に報
告されている。このレーザCVDでは、レジストプロセ
スを要さないので他の方法に較べ製作工程を大幅に短縮
できる特徴がある。
[Prior art and its problems] In manufacturing a staggered thin film transistor, which requires fewer manufacturing steps than an inverted staggered thin film transistor, after forming drain and source metal electrodes, a metal electrode is formed that partially covers the drain and source electrodes. A semiconductor layer was formed between both electrodes. The authors have proposed a method to form a semiconductor layer with such a structure by directly irradiating patterned laser light.
It was reported in the Proceedings of the 49th Japan Society of Applied Physics Conference in 1988, page 534. Laser CVD does not require a resist process, so it has the feature that the manufacturing process can be significantly shortened compared to other methods.

しかしながら従来の類スタガ型薄膜トランジスタ構造の
半導体層を形成するレーザCVDの場合、照射光の強度
を十分に下げないと電極金属が半導体層の中に拡散し、
トランジスタの電気特性を劣化させるという難点があっ
た。そのため従来のレーザCVDによる半導体層形成で
は、照射光強度を下げて行う結果、所望の膜厚を得るた
めに長い時間がかかり、レーザCVDによる工程短縮の
長所は十分に生かされていなかった。
However, in the case of laser CVD for forming a semiconductor layer of a conventional staggered thin film transistor structure, if the intensity of the irradiation light is not sufficiently lowered, the electrode metal will diffuse into the semiconductor layer.
This had the disadvantage of degrading the electrical characteristics of the transistor. For this reason, in conventional laser CVD semiconductor layer formation, the intensity of the irradiated light is lowered, and as a result, it takes a long time to obtain the desired film thickness, and the advantage of shortening the process by laser CVD has not been fully utilized.

本発明は以上述べたような従来の問題点を解決するため
になされたもので、レーザCVDによる半導体層の形成
を短時間で行うことのできる薄膜トランジスタを提供す
ることを目的とする。
The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a thin film transistor in which a semiconductor layer can be formed in a short time by laser CVD.

[課題を解決するための手段] 本発明は、ソース電極およびドレイン電極間に半導体層
が形成され、該半導体層上にゲート絶縁膜およびゲート
電極が順次形成された薄膜トランジスタにおいて、ソー
ス電極およびドレイン電極と半導体層との接触は、各電
極の側壁部でのみなされていることを特徴とする薄膜ト
ランジスタである。
[Means for Solving the Problems] The present invention provides a thin film transistor in which a semiconductor layer is formed between a source electrode and a drain electrode, and a gate insulating film and a gate electrode are sequentially formed on the semiconductor layer. The thin film transistor is characterized in that contact with the semiconductor layer is made only at the side wall portion of each electrode.

[作用] レーザCVDは、レーザ光照射部にのみ局所的に原料ガ
スの分解反応を促進し、成膜を生じさせる技術であり、
薄膜トランジスタマトリックスの半導体層の形成に適用
すれば、従来必要としたレジストプロセスを省くことが
でき、大いに工程および製作に要する時間を短縮できる
[Operation] Laser CVD is a technology that locally promotes the decomposition reaction of the source gas only in the laser beam irradiation area to form a film.
If applied to the formation of a semiconductor layer of a thin film transistor matrix, the resist process required in the past can be omitted, and the time required for process and manufacturing can be greatly reduced.

しかし、ドレイン、ソース電極と半導体層とのコンタク
トを電極表面と側面との両方でとる構造の従来型の類ス
タガ簿膜トランジスタを作成するためには、電極表面に
も直接レーザ光を照射しなければならない。そのため十
分に大きな成膜速度が得られるようなレーザ光強度のも
とでは金属の半導体層への拡散が生じ、薄膜トランジス
タの性能劣化を招く。これを防ぐために従来はレーザ光
強度を十分に下げ、低い成膜速度で半導体層を形成して
いた。このため従来型構造では、工程数は減少できるも
のの、製作に要する時間は短縮できず、レーザCVDの
メリットが十分に活かされない。
However, in order to create a conventional type staggered film transistor with a structure in which contacts between the drain and source electrodes and the semiconductor layer are made on both the electrode surface and the side surfaces, the electrode surface must also be directly irradiated with laser light. Must be. Therefore, under a laser beam intensity that allows a sufficiently high film deposition rate, diffusion of metal into the semiconductor layer occurs, leading to deterioration in the performance of the thin film transistor. In order to prevent this, conventionally the intensity of the laser beam was sufficiently lowered and the semiconductor layer was formed at a low deposition rate. For this reason, in the conventional structure, although the number of steps can be reduced, the time required for manufacturing cannot be shortened, and the advantages of laser CVD cannot be fully utilized.

本発明では、電極側面のみが半導体層と接触する構造と
なっているので、レーザCVDにて作製する際には、電
極間空隙にのみレーザ光を照射すればよく、電極上には
照射する必要がない。従って、高い強度のレーザ光を照
射しても電極材料が半導体層へ溶は出すことはないので
、短い時間で作製することができる。このため、薄膜ト
ランジスタの性能を劣化させることなく、製造工程の短
縮を図ることができる。
In the present invention, only the side surfaces of the electrodes are in contact with the semiconductor layer, so when fabricating by laser CVD, it is only necessary to irradiate the inter-electrode gap with laser light, and it is not necessary to irradiate the electrodes. There is no. Therefore, even if high-intensity laser light is irradiated, the electrode material will not dissolve into the semiconductor layer, so it can be manufactured in a short time. Therefore, the manufacturing process can be shortened without deteriorating the performance of the thin film transistor.

半導体層と金属との接触抵抗は、同じ金属膜厚。The contact resistance between the semiconductor layer and metal is the same metal film thickness.

半導体膜厚では従来構造より大きいが、金属膜厚。The semiconductor film thickness is larger than the conventional structure, but the metal film thickness is greater.

半導体膜厚を若干厚くすることによって、従来並み、の
低い接触抵抗に抑えられる。この際、増大する成膜に要
する時間を考慮しても、従来構造よりはるかに短い時間
で薄膜トランジスタを作成できる。
By slightly increasing the thickness of the semiconductor film, the contact resistance can be kept as low as in the conventional case. At this time, even when taking into account the increased time required for film formation, a thin film transistor can be created in a much shorter time than with conventional structures.

[実施例] 以下、本発明の実施例について図面を参照して詳細に説
明する。
[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明による薄膜トランジスタの部分断面図で
ある。
FIG. 1 is a partial cross-sectional view of a thin film transistor according to the present invention.

図中、1はドレイン電極、2はソース電極、3はゲート
電極、4は半導体層、5はゲート絶縁膜、6はガラス基
板、12はオーミック層である。
In the figure, 1 is a drain electrode, 2 is a source electrode, 3 is a gate electrode, 4 is a semiconductor layer, 5 is a gate insulating film, 6 is a glass substrate, and 12 is an ohmic layer.

各電極1,2の材料としてはクロム、ゲート絶縁膜5の
材料としてはSiN、半導体層4としては非晶質シリコ
ンを用いた。またオーミックコンタクトを良好にするた
めにドレイン、ソース電極表面はn型不純物を注入した
シリコン薄膜よりなるオーミック層12で覆った。
Chromium was used as the material for each of the electrodes 1 and 2, SiN was used as the material for the gate insulating film 5, and amorphous silicon was used for the semiconductor layer 4. Further, in order to improve ohmic contact, the surfaces of the drain and source electrodes were covered with an ohmic layer 12 made of a silicon thin film into which n-type impurities were implanted.

次に、上記薄膜トランジスタの製造方法について説明す
る。
Next, a method for manufacturing the above thin film transistor will be described.

まず、第1図に示すガラス基板6上にクロム膜をスパッ
タリング法により成膜し、パターニングを行うことによ
り、ドレイン電極1、ソース電極2を形成する。次に、
オーミック層12としてのリンドープシリコン膜をプラ
ズマCVDにより形成し、パターニングする。
First, a chromium film is formed by sputtering on a glass substrate 6 shown in FIG. 1, and patterned to form a drain electrode 1 and a source electrode 2. next,
A phosphorus-doped silicon film as the ohmic layer 12 is formed by plasma CVD and patterned.

続いて第2図に示した成膜装置を用い、半導体層4を次
のようにして形成する。ガラス基板6をCVDチャンバ
11に固定し、ArFレーザ7からの出射光をマスク8
、レンズ9、合成石英窓10を通してソース電極2とド
レイン電極1の間の空隙に、空隙方向の長さが空隙幅と
等しくなるビームパターンで照射する。その結果、CV
Dチャンバ11内に導入されたジシランガスがArFレ
ーザで光化学分解され、半導体層4としてのa−3i:
H膜のパターン薄膜が形成される。
Subsequently, using the film forming apparatus shown in FIG. 2, the semiconductor layer 4 is formed in the following manner. The glass substrate 6 is fixed to the CVD chamber 11, and the light emitted from the ArF laser 7 is passed through the mask 8.
, a lens 9, and a synthetic quartz window 10 to irradiate the gap between the source electrode 2 and the drain electrode 1 with a beam pattern in which the length in the gap direction is equal to the gap width. As a result, CV
Disilane gas introduced into the D chamber 11 is photochemically decomposed by an ArF laser to form a-3i as the semiconductor layer 4:
A patterned thin film of H film is formed.

引き続いてゲート絶縁膜5としてのSiN層をプラズマ
CVDで形成する。最後に再びクロム膜をスパッタリン
グ法により成膜した後、パターニングを行うことにより
ゲート電極3を形成する。
Subsequently, a SiN layer as the gate insulating film 5 is formed by plasma CVD. Finally, a chromium film is formed again by sputtering, and then patterned to form the gate electrode 3.

以上のようにして薄膜トランジスタを製造した。A thin film transistor was manufactured as described above.

実施例で得られた薄膜トランジスタ構造では、半導体層
形成の工程で18W/cm2以上の照射光強度でレーザ
を照射しても、半導体膜中に電極金属が拡散することは
なく、薄膜トランジスタのOFF電流は十分に低かった
。また、成膜速度は0.1曲/Cm2以下の低い照射光
強度で電極上に直接照射する場合に得られる成膜速度の
10倍以上であった。また、ドレイン、ソース電極と半
導体層の間には良好なオーミックコンタクトが形成され
ていることをドレイン電流−ドレイン電圧特性から確認
した。
In the thin film transistor structure obtained in the example, even if the laser is irradiated with an irradiation light intensity of 18 W/cm2 or more in the process of forming the semiconductor layer, the electrode metal does not diffuse into the semiconductor film, and the OFF current of the thin film transistor is It was low enough. Further, the film formation rate was more than 10 times the film formation rate obtained when the electrodes were directly irradiated with low irradiation light intensity of 0.1 songs/Cm2 or less. Furthermore, it was confirmed from the drain current-drain voltage characteristics that good ohmic contact was formed between the drain and source electrodes and the semiconductor layer.

なお、ゲート絶縁膜には必ずしもSiNを用いる必要は
なく、SiO2でも構わない。また、各電極は必ずしも
クロムである必要はなく、タンタル、アルミニウムでも
構わない。また、半導体層は必ずしもa−3i:)−1
を用いる必要はなく、ポリシリコンでも構わない。
Note that it is not necessarily necessary to use SiN for the gate insulating film, and SiO2 may also be used. Further, each electrode does not necessarily need to be made of chromium, but may be made of tantalum or aluminum. Moreover, the semiconductor layer is not necessarily a-3i:)-1
There is no need to use polysilicon, and polysilicon may be used.

[発明の効果] 以上説明したように、本発明による薄膜トランジスタで
はドレイン、ソース電極を半導体層に拡散さぜることな
く大きな成膜速度で半導体層を形成することができる。
[Effects of the Invention] As described above, in the thin film transistor according to the present invention, the semiconductor layer can be formed at a high deposition rate without diffusing the drain and source electrodes into the semiconductor layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の部分断面図、第2図は本発
明の薄膜トランジスタの製造に用いられる装置の一例の
構成図である。
FIG. 1 is a partial sectional view of an embodiment of the present invention, and FIG. 2 is a configuration diagram of an example of an apparatus used for manufacturing the thin film transistor of the present invention.

Claims (1)

【特許請求の範囲】[Claims] (1)ソース電極およびドレイン電極間に半導体層が形
成され、該半導体層上にゲート絶縁膜およびゲート電極
が順次形成された薄膜トランジスタにおいて、ソース電
極およびドレイン電極と半導体層との接触は、各電極の
側壁部でのみなされていることを特徴とする薄膜トラン
ジスタ。
(1) In a thin film transistor in which a semiconductor layer is formed between a source electrode and a drain electrode, and a gate insulating film and a gate electrode are sequentially formed on the semiconductor layer, the contact between the source electrode and the drain electrode and the semiconductor layer is at each electrode. A thin film transistor characterized in that only a sidewall portion of the thin film transistor is formed.
JP2079589A 1989-02-01 1989-02-01 Thin film transistor Pending JPH02203567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2079589A JPH02203567A (en) 1989-02-01 1989-02-01 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2079589A JPH02203567A (en) 1989-02-01 1989-02-01 Thin film transistor

Publications (1)

Publication Number Publication Date
JPH02203567A true JPH02203567A (en) 1990-08-13

Family

ID=12037003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2079589A Pending JPH02203567A (en) 1989-02-01 1989-02-01 Thin film transistor

Country Status (1)

Country Link
JP (1) JPH02203567A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648662A (en) * 1991-06-19 1997-07-15 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device with amorphous and crystalline shift registers

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648662A (en) * 1991-06-19 1997-07-15 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device with amorphous and crystalline shift registers
US6124155A (en) * 1991-06-19 2000-09-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and thin film transistor and method for forming the same
US6166399A (en) * 1991-06-19 2000-12-26 Semiconductor Energy Laboratory Co., Ltd. Active matrix device including thin film transistors
US6335213B1 (en) 1991-06-19 2002-01-01 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and thin film transistor and method for forming the same
US6756258B2 (en) 1991-06-19 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6797548B2 (en) 1991-06-19 2004-09-28 Semiconductor Energy Laboratory Co., Inc. Electro-optical device and thin film transistor and method for forming the same
US6847064B2 (en) 1991-06-19 2005-01-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a thin film transistor

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