JPH02202778A - Vertical synchronizing circuit - Google Patents

Abstract

PURPOSE:To quickly lead in synchronization by discriminating plural kinds of period of an external input vertical synchronizing signal and setting one mask width corresponding to a discriminated period. CONSTITUTION:An input vertical synchronizing signal Vi from a terminal 1 is differentiated by a differentiating circuit 2, and a differential output Vs is supplied to the reset input of a vertical counter 5. The counter 5 successively generates timing pulses S1, S2..., corresponding to prescribed counted values in accordance with counting. These timing pulses are supplied to a mask width setting circuit 6 together with a self-reset pulse Se. The circuit 6 discriminates the period of the present input signal Vi and generates a mask signal having the mask width closest to the period. Thus, the optimum mask width adapted to the period of the signal Vi is set based on the counted output of the counter 5, and synchronization is quickly led in to immediately obtain a picture free from step out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical 91 circuit of a run 1-down type that forms a vertical synchronization signal by counting clocks.

[4th Summary of the Invention] By determining the period of the input vertical synchronizing signal and changing the noise mask width based on the determined output, the noise blocking ability is optimized, and the input frequency is 50/6011
NTSC/PA
This is a vertical synchronization circuit that increases the synchronization pull-in speed when switching modes of L (SECAM).

[Conventional technology]

A countdown-type vertical synchronization circuit is known that includes a vertical counter that counts clock pulses and is reset (externally synchronized) by an external input vertical synchronization signal (■ signal) (e.g., Japanese Patent Laid-Open No. 56-84079). Public bulletin)
.

In order to perform the reset operation of the vertical counter stably without being disturbed by noise, this type of vertical synchronization circuit masks a predetermined section of the external input V signal and resets the gate circuit or input prohibition circuit that blocks noise. There is a biff in the input section.

By the way, the external input V signal is 6011z (NTS
C) and 5011z (PAL, S'EC 8M), and in the case of a VTR playback signal, the period of the simulated signal inserted during variable speed playback (slow, still, high speed search) is determined by tape speed and It is often the case that the signal is slightly changed from the standard value of the broadcast signal depending on the direction.

Therefore, in the above-mentioned vertical synchronization circuit, it is conceivable to make the width of the noise mask (input prohibited band) variable in accordance with the period of the input signal (2).

In a multi-mode receiver capable of receiving both NTSC signals and PA, L, and SECAM signals, it is necessary to set multiple mask widths for the 60 Hz system and multiple mask widths for the 5011 z system.

[Problem to be solved by the invention]

In the vertical synchronization circuit of a multimode receiver having a large number of input mask widths as described above, it takes a long time to lock until the vertical period of the input video signal is discriminated and the input mask width closest to that period is selected. There are drawbacks. Especially 50
When switching to a 6011z input video signal while operating in the 11z mode, the input vertical synchronization signal is caught in the noise mask and determined to be noise. At this time, the vertical counter of the vertical synchronization circuit repeats the self-resetting state because there is no external reset input, so it determines that this state continues, resets the previously set mask width, and resets the input signal again. It is designed to determine the cycle. Therefore, it takes a long time for the screen to synchronize with the input video signal.

In view of this problem, it is an object of the present invention to enable a synchronization pull-in operation of a vertical synchronization circuit having a large number of input mask widths to be achieved in a short time.

[Means to solve the problem]

The input presence/absence determination circuit of the vertical synchronization circuit of the present invention counts clock pulses during the vertical synchronization period, and
A vertical counter 5 that is reset by one signal, a mask and gate circuit 3 that supplies the external input vertical synchronization signal with a predetermined section masked as a reset input to the vertical counter 5, and an increase in the number of vertical counters by 81. Based on the timing of multiple count values that occur, external input vertical synchronization 1
No. 3, multiple types of periods are determined, and one mask width corresponding to the determined period among the multiple types of mask width is selected from the above matrix,
Mask width setting circuit 6 set in the gate circuit and control that determines whether the external input synchronization signal is either 5011z or 60Hz and sets the mask width to the minimum value among the above multiple types when switching the frequency. and a discriminator circuit 7 that outputs the output to the mask width setting circuit.

[Effect]

When the input is not switched from the PA'L (SECAM) signal to the NTS C signal, the mask width is reset to the minimum value, so that every time the input vertical synchronization signal is caught by the previously set mask width. It locks immediately to the input vertical synchronization signal after switching.

〔Example〕

FIG. 1 is a block diagram of a vertical synchronization circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a main part of the mask width setting circuit of FIG. 1, and FIG. 3 is an operation waveform diagram.

In FIG. 1, input vertical synchronization Haigo V from input terminal 1
+ (FIG. 3A) is differentiated by the differentiating circuit 2 as shown in FIG.

The vertical counter 5 counts clock pulses CLK (for example, pulses obtained by frequency-dividing the burst synchronization APC signal lock output) supplied to the clock input terminal C for a period of approximately the vertical scanning period (V), and counts the clock pulses CLK (for example, pulses obtained by dividing the frequency of the burst synchronization APC signal lock output), and ■By being reset with , it is synchronously coupled with the outside.Based on the count output, the self-signal S is always 262
．． 5H (IV) +2.5H (H: horizontal scanning period, ■:
The counter 5 operates stably by self-resetting when the external vertical synchronizing signal is lost.

External signal V or internal signal S obtained from OR gate 4
, is supplied as a stable vertical synchronization signal to, for example, a vertical deflection circuit in a receiver.

As the count increases, the vertical counter 5 generates timing pulses S1, S2 corresponding to a predetermined count value.
...S, are generated sequentially. These timing pulses are supplied to the mask width setting circuit 6 together with the self-reset pulse S0. The mask width setting circuit 6 receives the current input signal V
Determine the period of , and select the third figure closest to that period, E.
. . . One of the mask widths shown in G is formed as a mask signal.

Based on this mask signal, the mask gate circuit 3 closes during most of the vertical synchronization period, preventing noise mixed into the input V from reaching the reset input of the counter 5.

As shown in FIG. 2, the mask width setting circuit 6 receives timing pulses S2, S4, etc. from the vertical counter 5.
m-ary (for example, quaternary) counter group 11 that counts ...
Then, the flip-flop group 12 that holds the count-up output is turned on.

The timing pulse from the vertical counter 5 is used to determine the period. That is, if the input signal (8) falls within the detection range Wl of St to S4 as shown in Fig. 3 y and l, the pulse S
2 occurs and the pulse S4 does not occur due to the reset of the counter 5 by the input v,', so the pulse S! By counting up only the counter 11a, it is determined that the input y% is within the detection range W from S-2 to S, and the flip-flop 12a holds the result.

The cent output of the flip-flop 12a selects one of the selection circuits 13 (13a
3 is open and the timing pulse Sl closest to the input V,′
is selected. This pulse SI is led out from the OR gate 14 to the mask gate 3 in FIG. 1 as a mask edge pulse ME.

This mask edge pulse ME determines the width (trailing edge) of the mask 1 as shown in the third diagram.

That is, as shown in FIG. 2, the mask gate 1/circuit 3 is provided with an RS flip-flop 15 which is sent by the output 3 of the mask gate ant gate 1/16 and reset by the mask edge pulse ME. The Q output is applied from the minute delay device 17 to the AND gate 16 to close the gate. Therefore, the mask width is from immediately after the input 5 to the mask edge ME, and noise during this period is prevented from being output from the AND gate 16 as a reset signal.

Note that these flip-flops 15 and AND gates 16
, the delay device 17 also serves as the differential circuit 2 in FIG.

In FIG. 2, when there are m inputs 8 of the same period, one of the corresponding counters in the counter group 11 performs count amplification, and the other counters are reset. Further, one of the corresponding flip-flops 12 is set by the count-up output, and the other flip-flops are reset.

From this, classification (discrimination) of the input period based on the period detection range W, Wff . . . and selection of the mask width are performed.

As shown in FIGS. 4A and 4H, when the input V is 5011z, the mask width a is set, and as shown in CSD, when the input V is (iollz), the mask width a is set. Therefore, when the vertical synchronization circuit shown in Fig. 1 is operating in 5011z mode, when input ■1 is switched to 6011z as shown in Fig. 4E, vl becomes 50112 mode mask a (Fig. 4 F).

Therefore, this vertical synchronizing signal is blocked by the mask gate circuit 3, and the subsequent synchronizing signal can pass without forming the next mask. In other words, as shown in FIG. 4F, every other input symbol is masked.

The vertical counter 5 is reset every other input Vm,
In the section where there is no reset input, it operates by self-resetting.

This state in which external reset and self-reset are repeated alternately can be distinguished from the self-reset that corresponds to a random vacancy in the input V, so when the repetition continues a predetermined number of times, the mask of the vertical synchronization signal is removed. It can be determined that this is occurring. Therefore, it is possible to obtain such a determination result and reset the currently set mask width to the minimum value.

However, this method of determining the number of external reset/self-reset repetitions has a very slow response and
When i switches from 5011z to GOIIz, it takes time for the images to synchronize on the monitor.

For this reason, as shown in FIG. 1, a 50/60 Hz discrimination circuit 7 is provided, and the mask width setting circuit 6 is reset by the discrimination pulse Sf. That is, as shown in FIG.
When the input V becomes 6011z, the discrimination pulse Sr shown in FIG. 5B is output from the discrimination circuit 7, and thereby the lowest flip-flop 12a of the flip-flop group 12 in FIG. 2 is set, and the others are reset. be done. As a result, the timing pulse S of the output of the vertical counter 5 is selected by the gate 1-13a, and the minimum width m is selected as shown in the fifth diagram.
A mask 1 (FIG. 3D) of in is set in the mask gate circuit 3.

Therefore, from now on, the input Vi is quickly determined, and the vertical synchronization circuit is locked in a state where the corresponding mask width is set.

The 50/6011z discrimination circuit 7 is constructed as shown in FIG. That is, as shown in FIG. 7A and B, 6011z and 501
1, K2 for the wind pulse that includes the trailing edge of period 1z
is formed starting from the input V. These wind pulses form a hysteresis band that overlaps with each other, taking into consideration that the period of the input vertical synchronizing signal changes from the standard during variable speed reproduction of VTII.

1, K2 for each wind pulse is supplied to the AND gates 20, 21 of FIG. Count up one and reset the other. Therefore, the input v of 5011z or 6011z
When eight consecutive t's are supplied, one of the counters 22 and 23 generates a count-up output, and the flip-flop 24 is set or reset.

When the [human] Vi is C1011z, the counter 22 generates a click up output, and the flip-flow knob 2
4 cents, and a high level discrimination output S, indicating 60IIz (FIG. 5C) is generated. In the case of 5011z, the counter 23 generates a count-up output, the flip-flop 24 is reset, and the discrimination output Sg becomes a low level (5011z).
The z discrimination output is given to the vertical counter 5 as a count number switching signal as shown in FIG.

In addition, the output of each counter 22 and 23 and the flip-flop 2
AND with Q of 4 and 100 output is AND gate 25.2
6, input ■1 is taken from 5Qllz to 6011
z or vice versa, the previously described 50/6011z discrimination pulse S shown in FIG. It will be output immediately after. This discrimination pulse sr
is applied to the mask width setting circuit 6 in order to reset the mask width to the minimum value win (FIG. 3D) as described above.

〔Effect of the invention〕

As mentioned above, the present invention combines the N'T'SC signal and I)
In a vertical synchronization circuit such as a multi-mode receiver that can accept ΔL (SECAM) signals, when the input is switched, the input that was set corresponding to the cycle of the immediately previous input vertical synchronization signal Since the noise mask width is reset to the minimum value, the vertical synchronization signal after switching is immediately supplied to the vertical counter as a reset input without being caught by the mask width. Therefore, from now on, the optimum mask width matching the period of the input vertical synchronizing signal is set based on the count output of the normally operating vertical counter, and prompt synchronization is carried out, so that an image without synchronization holes can be immediately obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main part of the vertical synchronization circuit to which the present invention is applied, Fig. 2 is a block diagram of the main part of the mask width setting circuit of Fig. 1, and Figs. 3 to 5 are operational waveforms of the vertical synchronization circuit. Figure, 6th
The figure is a block diagram of a 50/6011z discrimination circuit, and FIG. 7 is an operation waveform diagram of the discrimination circuit. In addition, in the symbols used in the drawings, 3...--Mask gate circuit 5--Vertical counter 6
−・・・−・・−・・−・−Mask width setting circuit 7 ・・
−・−・・−・・−・・−・・−・50/6011
Z discrimination circuit 11・-・−・・−・−・・・rr
ln counter group 12・・−・−・・・・−・−・・−
・・Flip-flop group 13−・−・−・・・−・
. . . This is a selection circuit. 50 /60 Hz Haribetsu @Fushi Figure 6 Wind signal Figure 7

Claims (1)

[Claims] A vertical counter that counts clock pulses during a vertical synchronization period and is reset by an external input vertical synchronization signal, and the external input vertical synchronization signal with a predetermined section masked is supplied to the vertical counter as a reset input. A mask gate circuit that determines multiple types of cycles of the external input vertical synchronization signal based on the timing of multiple count values that occur as the count of the vertical counter increases, and determines the determined cycle from among the multiple types of mask widths. a mask width setting circuit that sets one mask width corresponding to the above-mentioned mask width in the mask gate circuit; and a discriminator circuit that outputs a control output that sets the minimum value among the seeds to the mask width setting circuit.