JPH06197235A - Vertical synchronizing frequency deciding circuit - Google Patents

Abstract

PURPOSE:To surely decide and lock in the vertical horizontal frequency despite mixture of the vertical synchronizing frequency of 50/60Hz. CONSTITUTION:The vertical synchronizing signal is separated from an input decoding video signal by a vertical synchronizing separator 2. The window pulses W1 and W2 corresponding to the vertical synchronizing signals of 50Hz and 60Hz respectively are produced by a decoder circuit 5. Then the and 60 deciding circuits 6 and 7 detect that the vertical synchronizing signals are included in both pulses W1 and W2 in the prescribed times. A 60Hz detecting action is reset by a fact whether the VP produced from a vertical synchronizing signal is detected by a VP presence detecting circuit 8 or the deciding output of the circuit 6 is confirmed. Then a 50Hz deciding action is reset by the presence of the output detected by the circuit 8 or the deciding output of the circuit 7. Then a frequency deciding circuit is set by the deciding output of the circuit 6 and reset by the deciding output of the circuit 7 or the detection output of the circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention determines whether the vertical synchronizing frequency of a television receiver is 50 Hz or 60 Hz.
The present invention relates to a vertical sync frequency discrimination circuit.

[0002]

2. Description of the Related Art As a vertical synchronizing device for a television receiver, a circuit disclosed in Japanese Patent Application No. 2-293379 is well known and is shown in FIG. The composite video signal detected by the video detection circuit in the preceding stage is supplied from the input terminal 51 to the sync separation circuit 52, where it is separated into the vertical sync signal VS and the horizontal sync signal HS. Of these, the vertical synchronization signal VS is
Clock CK that is an integral multiple of the input horizontal frequency (fH)
Is input to the input terminal 53 and supplied to the vertical counter 54 which divides the frequency. The count data of the vertical counter 54 is supplied to the decoder circuit 55, and the decoder circuit 55 generates various pulses used internally. The vertical counter 54 waveform-shapes the vertical synchronizing signal VS to internally generate a constant pulse VP having a narrow pulse width. Whether the vertical synchronizing frequency is 50 Hz or 60 Hz is determined by 50/60 discriminating circuits 56 and 57 which discriminate the respective frequencies.

First, the 50 discriminating circuit 56 is supplied from the decoder circuit 55 with a window pulse W1 corresponding to a signal of 50 Hz count cycle. Further, if the pulse VP is input and the pulse VP is generated within the period of the window pulse W1, the number of times is counted. When the counted value reaches a predetermined value, the 50 determination circuit 56
To output an output pulse of 50 discriminations. Similarly, the window pulse W2 corresponding to the count cycle of 60 Hz is supplied from the decoder circuit 55 to the 60 determination circuit 57. It is detected that the pulse VP is in the window pulse W2, it is counted, and when it reaches a predetermined value, the 60-discrimination output 57 outputs the 60-discrimination output pulse.

The pulse VP from the vertical counter 54 is changed to VP.
It is supplied to the non-existence detection circuit 58, and the presence or absence of the pulse VP, that is, the presence or absence of the input signal is determined. When there is no input of the composite video signal, the output signal of the sync separation circuit 52 becomes no signal, so that there is no vertical sync signal VS and no pulse VP is generated.
This is detected by the VP absence detection circuit 58, and when there is no pulse VP, the H level is output. This VP-less signal and 50
OR 60 output and OR gates G1 and G2
The 50 discrimination output is connected to the reset terminal R of the 60 discrimination circuit 57, and the 60 discrimination output is connected to the reset terminal R of the 50 discrimination circuit 56 in a striking manner. Also, 50 discrimination output and 6
The 0 discrimination output is connected to the discrimination result memory 59, and the memory 59
Is used as the discrimination output of 50/60.

First, since there is no pulse VP in the no-signal state, the output of the VP no-detection circuit 58 is in the VP no-state (H level), and the 50, 60 both discriminating circuits 56, 57 are supplied via the gates G1, G2. Reset. Since the discrimination outputs of the 50/60 discrimination circuits 56 and 57 are fixed at the L level, the discrimination result memory 59 holds the discrimination result before that. When the vertical synchronizing signal VS is input from this state, the output of the VP non-existence detection circuit 58 is in the state with VP (L level), and the reset is released.

Now, when the 50 Hz vertical synchronizing signal VS arrives, the 50 discriminating circuit 56 starts the discriminating operation because the pulse VP is positioned within the window pulse W1.
Specifically, each of the discrimination circuits 56 and 57 is composed of a counter, and the pulse VP generated in the window pulse W1 is generated.
To count. When this exceeds a predetermined value, the output of the 50 discrimination circuit 56 becomes the H level, and the discrimination result memory 59
Is set to 50 Hz. At the same time, the 60 discrimination circuit 57 is reset via the gate G2 to prevent malfunction due to noise. When the input signal is 60 Hz, vice versa, the output of the 60 discriminating circuit 57 resets the 50 discriminating circuit 56 via the gate G1.

In this way, the output of the discrimination result memory 59 indicates either 50 or 60 Hz, so that the discrimination output does not switch when there is no signal, and the screen position (size) does not switch and the video signal is stable. Can be received.

However, when the no-signal state is changed to the signal state, the vertical counter 54 performs the pull-in operation, and after the pull-in, each circuit performs masking and sensitivity control in order to improve the noise resistance performance. In this process, the presence of the mask and the sensitivity control circuit may delay the pull-in. For example, when a signal of 50 Hz is received and a signal of 60 Hz is input from a VTR or the like, the mask signal for 50 Hz masks the pulse VP and masks the 60 Hz signal of a short cycle, and the screen size is switched. There was a problem that it would end up.

[0009]

In the above-described conventional vertical sync frequency discriminating circuit, since there is a mask and a sensitivity control circuit for improving the noise performance performed after the entrainment, the entrainment is delayed and the screen size is reduced. There was a problem that was switched.

An object of the present invention is to provide a vertical synchronizing frequency discriminating circuit which can discriminate and pull in smoothly even when 50/60 Hz systems are mixed.

[0011]

A vertical synchronizing frequency discriminating circuit of the present invention includes a circuit for separating a vertical synchronizing signal from an input composite video signal, and first and first circuits corresponding to the vertical synchronizing signals of 50 Hz and 60 Hz. Means for generating a second window pulse, a discriminating circuit for 50 Hz and 60 Hz for detecting that the vertical synchronizing signal is positioned a predetermined number of times in the first and second window pulses, and the vertical synchronizing signal A presence / absence detection circuit for detecting the presence / absence;
A means for resetting the 60 Hz detection operation by either the discrimination output of the 0 Hz discrimination circuit or the detection output of the presence / absence detection circuit, and the 50 Hz discrimination operation by either the discrimination output of the 60 Hz discrimination circuit or the discrimination output of the presence / absence detection circuit. It comprises reset means and memory means which is set by the discrimination output of the 50 Hz discrimination circuit and is reset by either the discrimination output of the 60 Hz discrimination circuit or the discrimination output of the presence / absence detection circuit.

[0012]

By the above-mentioned means, a memory dedicated to 50 discrimination is prepared in addition to the discrimination memory of 50/60, and the mask pulse or the sensitivity control signal for operating the system is switched by the output, and the discrimination result is 50 Hz. If it is operated in the system of 60Hz until it appears, the mask pulse and the sensitivity control signal will be generated at the timing that can correspond to both 50 and 60, so the pull-in will not be delayed and the screen size will not switch. Disappear.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, the composite video signal detected by the video detection circuit in the previous stage is supplied from the input terminal 1 to the sync separation circuit 2, where the vertical sync signal VS and the horizontal sync signal H are supplied.
Separate into S and. Among them, the vertical synchronization signal VS inputs a clock CK that is an integral multiple of the input horizontal frequency (fH) to the input terminal 3 and supplies it to the vertical counter 4 that divides the frequency. The counter data of the vertical counter 4 is supplied to the decode circuit 5, and the decode circuit 5 receives the window pulse W.
In addition to 1, W2, various pulses are generated.

Further, the vertical counter 4 also generates a pulse VP which is a waveform-shaped waveform of the vertical synchronizing signal VS and outputs it as 50H.
50/60 discrimination circuits 6 and 7 for discriminating between z and 60 Hz
Supply to. The window pulse W1 corresponding to the frequency is supplied from the decoder circuit 5 to the 50 discrimination circuit 6, and the window pulse W2 corresponding to the frequency is supplied from the decoder circuit 5 to the 60 discrimination circuit 7. In the 50/60 discrimination circuits 6 and 7, the pulse VP is the window pulse W1 or W2.
Detect if it is located inside. In the no-VP detection circuit 8,
The presence or absence of the pulse VP is detected. V of no-VP detection circuit 8
The P-less signal output is supplied to the reset terminals R of the respective discrimination circuits 6 and 7 via the OR gates G1 and G2.

The outputs of the 50/60 discrimination circuits 6 and 7 are output to the discrimination result memory 9, and the results are output to the outside as 50/60 discrimination output. The determination result of the 50 determination circuit 6 is supplied to the other input terminal of the gate G2, and the determination result of the 60 determination circuit 7 is supplied to the other input terminal of the gate G1 to reset each other. The output of the 50 discrimination and the output of the gate G1 are supplied to the 50 discrimination memory 10, and the output is used as the 50 discrimination output for controlling various pulses.

In the no-signal state, the output of the VP non-detection circuit 8 is in the VP non-state (H level), and the gates G1 and G
50/60 discriminating circuits 6 and 7 are reset via 2.
The memory 9 holds the result determined before that. 5
The 0 discrimination memory 10 is set by the discrimination output of the 50 discrimination circuit 6 and reset by the output of the gate G1. The output of the gate G1 is at the H level because there is no VP, and the 50 discrimination memory 10 is reset to the state of 60 Hz.

When a signal of 50 Hz arrives, the output of the non-VP detection circuit 8 becomes VP (L level), and 50 /
60 The reset of the discrimination circuits 6 and 7 is released. In the 50 discrimination circuit 6, since the pulse VP exists in the window pulse W1, counting is started and an output pulse is output when a certain value is reached. Then, the determination result memory 9 is 50H
Then, the 50 discrimination memory 10 is also set to the 50 Hz state. The output of the 50 discrimination memory 10 becomes H level, and each control signal is switched for 50 Hz.

When the 60 Hz signal arrives, the 50 discrimination memory 10 is reset through the gate G1 even if the discrimination result of the 60 discrimination circuit 7 appears, so that the memory output remains at the same L level as in the non-signal state. Become.

FIG. 2 shows a concrete circuit example of the 50/60 discrimination circuits 6 and 7 and the memories 9 and 10 of FIG. The 50 discrimination circuit 6 is composed of an AND gate G3 and flip-flops F1 and F2, and the 60 discrimination circuit 7 is composed of an AND gate G4 and flip-flops F3 and F4. The gate G3 detects whether or not the pulse VP is located within the window pulse corresponding to 50 Hz. The pulse VP passing through the gate G3 is counted by the flip-flops F1 and F2. The AND gate G5 has flip-flops F1 and F2.
Q output and pulse VP. Therefore, VP appears at the output of G5 at the fourth VP. Then gate G5
The outputs set flip-flops F5 and F6, and the outputs of both memories 9 and 10 are set to H level. The operation at the time of 60 Hz input is also the same, and the description is omitted. If the discrimination circuit malfunctions due to the pulse VP generated by noise, it can be dealt with by increasing the number of stages of the counter.

FIG. 3 shows another embodiment of the present invention. The same parts as those of the embodiment of FIG. The vertical counter 4 in this embodiment operates with a clock CK of 2fH, and the decode address is 2fH.
Will be shown in terms of expressions. For example, the standard vertical cycle for domestic broadcasting is 262.5 lines,
With the 2fH standard, this is 525 count cycles.

A vertical sync separation circuit 2'for separating the vertical sync signal VS and the horizontal sync signal HS from the composite video signal supplied to the input terminal 1 makes it possible to switch the separation sensitivity of the vertical sync signal VS. . Sensitivity control signal VSW
Is generated by an SR flip-flop F7. As shown in FIG. 4B, the sensitivity control signal VSW becomes H level at a certain address and falls to L level with the generation of the pulse VP.

From no signal state, as shown in FIG.
When the vertical synchronization signal VS of z is generated, the output of the 50-discrimination memory 10 is still at the L level as shown in FIG. 4B, and the address signal 520 from the decoder circuit 5'is
It is supplied to the set terminal R of the flip-flop F7. As a result, the sensitivity control signal VSW rises at the address of 520 and returns to the L level when the pulse VP is generated. It is assumed that the sensitivity of the vertical sync separation circuit 2 is high when the sensitivity control signal VSW is at H level, and is low when it is at L level.

By doing so, V shown in FIG.
Even if a 60 Hz cycle signal such as S ′ arrives,
Since the sensitivity is increased from the address of 520 that can pass 0 Hz, VS 'can be separated in a highly sensitive state. Since the separation sensitivity is low while the sensitivity control signal VSW is at the L level, it is difficult to separate noise and the like, and it is possible to prevent noise from being superimposed on the vertical synchronization signal VS.

When the pulse VP is generated several times and the output of the 50 discrimination memory 10 becomes H level, the address signal from the decoder circuit 5'is switched to 620 for 50 Hz and the generation timing of the sensitivity control signal VSW is changed to 50 Hz. Set. At this point, the separation sensitivity is set low for VS 'of 60 Hz cycle.

The present invention is not limited to the above-mentioned embodiment, the output of the 50-discrimination memory 10 is used for the masking of the similar sensitivity control signal and window pulse, and until the result of 50 discrimination is obtained. If the system is set so that the 60 Hz signal can pass, the pull-in operation can be performed satisfactorily regardless of which of the 50/60 vertical synchronizing signals arrives.

[0026]

As described above, according to the vertical synchronizing frequency discriminating circuit of the present invention, it is possible to surely perform the discrimination and the pull-in smoothly even if the 50/60 Hz systems are mixed.

[Brief description of drawings]

FIG. 1 is a system block diagram showing a 50/60 discrimination circuit of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the discrimination circuit of FIG.

FIG. 3 is a system block diagram showing another embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of FIG.

FIG. 5 is a system block diagram showing a conventional 50/60 discrimination circuit.

[Explanation of symbols]

2 ... Vertical synchronization circuit, 5 ... Decoder circuit, 6 ... 50 discrimination circuit, 7 ... 60 discrimination circuit, 8 ... VP-less detection circuit, 9 ... Memory, 10 ... 50 discrimination memory.

Claims (2)

[Claims] 1. A circuit for separating a vertical synchronizing signal from an input composite video signal, and a first circuit corresponding to the vertical synchronizing signals of 50 Hz and 60 Hz.
And a means for generating a second window pulse, a discriminating circuit for 50 Hz and 60 Hz for detecting that the vertical synchronizing signal is positioned a predetermined number of times in the first and second window pulses, and the vertical synchronizing A presence detection circuit for detecting the presence or absence of a signal, a means for resetting the 60 Hz detection operation by either the discrimination output of the 50 Hz discrimination circuit or the detection output of the presence detection circuit, and the discrimination output of the 60 Hz discrimination circuit or the presence detection Means for resetting the 50 Hz discriminating operation by either of the discriminating output of the circuit and the memory set by the discriminating output of the 50 Hz discriminating circuit and reset by either the discriminating output of the 60 Hz discriminating circuit or the discriminating output of the presence / absence detecting circuit. A vertical synchronizing frequency discriminating circuit comprising: 2. The separation sensitivity of the vertical sync separation circuit is controlled by the output of the memory means.
The vertical synchronization frequency determination circuit described.