JPH02202062A - Manufacture of mos type transistor - Google Patents

Abstract

PURPOSE:To protect a transistor of this design against deviation in alignment and to shorten a manufacturing time by a method wherein a polycrystalline Si layer deposited on a single crystal Si substrate is irradiated with particles to turn the polycrystalline Si layer or the polycrystalline Si layer and the upper part of the single crystal Si substrate amorphous, which is thermally treated to grow epitaxially in solid phase. CONSTITUTION:A polycrystalline Si layer 37 is deposited on an Si substrate 31, which is irradiated with accelerated particles 30 to turn the polycrystalline Si layer 37 or the polycrystalline Si layer 37 and the upper part of the semiconductor substrate 31 amorphous, and an amorphous Si layer 39 is epitaxially grown in solid phase, whereby the amorphous Si layer 39 of a source region 35 and a drain region 36 is selectively single crystallized. After the amorphous Si layer 39 has been epitaxial grown in solid phase, the single crystal Si substrate 31 is etched to selectively remove the polycrystalline Si layer 37 except that formed on the single crystal layer 40 of the source and the drain region 35 and 36. Therefore, the single crystal Si layer 40 of the source region 35 and the drain region 36 can be formed without using a photolithography technique. By this setup, a transistor of this design can be protected from misalignment and shortened in time required for manufacture.

Description

[Detailed description of the invention] Hair! 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor used in a semiconductor integrated circuit, particularly a short channel MOS transistor.

Semiconductor integrated circuits (ICs) include those that use MOS transistors and those that use bipolar transistors as active devices, but MOS transistors have an order of magnitude higher integration density than bipolar transistors. There are advantages that can be increased.

The structure of a MOS type transistor is, for example, M shown in FIG.
Like an OS type transistor, an insulating film 12 of Sin is formed on a semiconductor substrate 11 of single crystal Si, and the insulating film 1
A gate electrode 13 is formed on 2. Semiconductor substrate 1
A source region diffusion layer 14 and a drain region diffusion layer 15 are formed on both sides of the gate electrode 13 in the upper layer.

16 is an element isolation film.

Incidentally, in order to increase the integration and speed of ICs using MOS transistors, it is necessary to miniaturize the MOS transistors that constitute the ICs. M.O.S.
In principle, miniaturization of type transistors is carried out according to shrinking agents, but as the miniaturization progresses, various undesirable phenomena occur. The main one is the short channel effect that occurs when the channel length is shortened.

Although the threshold voltage of a MOS transistor should originally be unrelated to device dimensions, it tends to decrease as the channel length becomes shorter. Therefore, the threshold voltage, which is the most important characteristic value in constructing an LSI, is greatly influenced by the channel length.

Buried gate transistors and stacked source-drain transistors have been proposed as structures to prevent such adverse short channel effects.

Among these, the method for manufacturing the stacked source train transistor is as follows, for example (FIG. 3).

■ Forming an insulating film 12, a gate electrode 13, and an element isolation film 16 on the semiconductor substrate 11 (see Figure (a) ■ Semiconductor substrate 11
A polycrystalline Si layer 17 is laminated over the entire upper surface of the substrate (FIG. 2(b)).

(2) As a photolithography step, an etching mask 18 made of photoresist or the like is formed on the polycrystalline Si layer 17 (FIG. 3(c)).

(2) After etching the polycrystalline Si layer 17, the etching mask 18 is removed to form a source region 19 and a drain region 20 (FIG. 4(d)).

In this method of manufacturing a stacked source-drain transistor, a single crystal Si semiconductor substrate 11 and a polycrystalline Si semiconductor substrate 11 are used.
A discontinuous interface is formed between the source region 19 and between the semiconductor substrate 11 and the drain region 20 because surfaces having different properties, such as single crystal and polycrystal, come into contact. Then, the crystal defects existing at this discontinuous interface become the center of recombination, and junction leakage current occurs.

As a technique for preventing the formation of such a discontinuous interface between single crystal Si and polycrystalline Si, there is a selective epitaxial growth technique.

This selective epitaxial growth technique exposes the single-crystal Si substrate only in the regions where the source region, drain region, or diffusion layer will be formed, and the other regions are covered with Si.
0□, and single-crystal Si epitaxial growth is performed only on the exposed portion of the semiconductor substrate. Since the epitaxial growth layer is the same crystal as the seed crystal,
The source region and drain region above the exposed portion of the single crystal Si substrate are made of single crystal Si, and the other portions are made of polycrystalline Si. If etching is performed simultaneously with or after epitaxial growth, and etching conditions and growth conditions are appropriately selected, a single-crystal Si layer can be formed only on the exposed portion of the single-crystal Si substrate.

According to this selective epitaxial growth technique, single-crystal Si source and drain regions are formed continuously on the semiconductor substrate, and no discontinuous interface occurs.

However, the selective epitaxial growth technique described above requires special equipment, and many defects are formed in the epitaxial growth layer at low temperatures.
(℃ or higher). Furthermore, in the method of etching at the same time as epitaxial growth, there is a risk that HlCI or the like used for etching may be mixed into the epitaxially grown layer (autodoping).

Furthermore, since the source region and train region of stacked source-drain transistors are generally formed by photolithography, there are drawbacks such as misalignment and prolongation of manufacturing time as MOS transistors become smaller. Ta.

In view of the above-mentioned problems, the present invention makes it possible to form single-crystal source and drain regions without using photolithography, thereby eliminating misalignment and shortening manufacturing time. It is an object of the present invention to provide a method for manufacturing a MOS type transistor in which the region and the drain region are made of single crystal to prevent the formation of the discontinuous interface, which can be processed at low temperature, and does not contain impurities.

To achieve the above object, the present invention provides a method for manufacturing a MOS transistor comprising a gate electrode, an insulating film, a semiconductor layer, and a source/drain electrode. After forming a gate electrode on a Si substrate, a step of depositing a polycrystalline Si layer on the single crystal Si substrate including regions for forming a source and a drain; amorphous layer, or the polycrystalline Si layer and the upper layer of the single-crystalline Si substrate.

(2) selectively converting the amorphous Si layer in the source and drain regions into single crystals by heat-treating the amorphous Si layer to cause phase-phase epitaxial growth; (2) etching the heat-treated Si substrate; The method is characterized by the step of selectively removing Si layers other than the single crystal Si layer in the source and drain regions.

Further, in the step of irradiating the polycrystalline Si layer with accelerated particles, a St beam is used as the accelerated particles.

According to the method described above, the polycrystalline Si layer, or the upper layer of the polycrystalline Si layer and the single-crystalline Si substrate, is made amorphous by irradiating the polycrystalline Si layer with appropriately accelerated particles. This amorphized polycrystalline Si layer and single crystalline Si layer
When the substrate is heat-treated to cause phase-phase epitaxial growth, a single-crystalline Si layer is formed on the polycrystalline Si layer on the single-crystalline Si substrate, and since there are no crystal planes to serve as seeds except on the single-crystalline Si substrate, the polycrystalline Si layer or the non-crystalline Si layer is formed. A crystalline Si layer is formed. Since it is in-phase epitaxial growth, the temperature is low (50
The single-crystal Si layer grows at a temperature of about 0° C.), and there are no impurities or defects caused by etching gas or the like in the single-crystal Si layer near the inversion layer and depletion layer, which are important for transistor characteristics. By etching after epitaxial growth, the Si layer other than the single crystal formed by epitaxial growth can be removed, and single crystal source and train regions are formed continuously on the single crystal Si substrate.

Further, by using a Si ion beam as the accelerated particles, it is possible to avoid impurities from being mixed into the polycrystalline Si layer.

corridor Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows the manufacturing process of a miniature MO3 field effect transistor (MOSFET) that constitutes an LSI.

The structure of this MOSFET is as shown in FIG.
2. An insulating film 33 is formed in the center, and a gate electrode 34 is embedded in this insulating film 33. A single crystal SL source region 35 is located between the left and right element isolation films 32 and the insulating film 33.
and a drain region 36 are formed. The source region 35 and the drain region 36 are continuously formed from the semiconductor substrate 31 of single crystal Si, and are formed continuously from the semiconductor substrate 31 of single crystal Si.
There are no discontinuous interfaces between the semiconductor substrate 31 and the drain region 36 and the semiconductor substrate 31 and the source region 35 .

Next, an example of the manufacturing method of the above MO3FET is shown in FIG.
The explanation will be based on a) to (e).

First, to explain the outline of the manufacturing method of the example, Fig. 1 (
As shown in a), an element isolation film 32, an insulating film 33, and a gate electrode 34 surrounded by this insulating film 33 are formed on a semiconductor substrate 31 of single crystal Si.
A polycrystalline Si layer 37 is formed on the entire upper surface of the
)), the polycrystalline Si layer 37 is irradiated with accelerated particles 38, and the polycrystalline Si layer 37 and the single-crystalline Si semiconductor substrate 3 are
A part of the upper layer of the single crystal Si semiconductor substrate 31 is made amorphous to form an amorphous Si layer 39 with a thickness of Max, O, E5 um (FIG. 1(c)). The upper layer does not necessarily need to be made amorphous.Next, by heat-treating the amorphous Si layer 39 and causing phase epitaxial growth, a single portion of the amorphous Si layer 39 on the semiconductor substrate 31 is formed. The crystalline Si layer 40 is selectively epitaxially grown (FIG. 1(d)). At this time, the amorphous Si layer 39 other than the semiconductor substrate 31 is heated to become a polycrystalline layer 39 (a
).Finally, the remaining polycrystalline Si layer 39(a) is selectively removed by etching to form a source region 35 and a drain region 36 on the semiconductor substrate 31 (FIG. 1(e)). .

The method of amorphization is to irradiate accelerated particles 38 to form polycrystalline Si.
Energy is applied to the layer 37 or the polycrystalline Si layer and the upper layer of the semiconductor substrate 31 to break the crystal structure and turn it into an amorphous state. Ion beams, electron beams, neutron beams, etc. are suitable for the accelerated particles 38. When an ion beam is used, it has the advantage that it can be made amorphous with a lower dose than an electron beam. In particular, when a Si ion beam is used, the polycrystalline Si layer 37 or the semiconductor substrate 31 is
Since there is no risk of contamination with impurities other than i, a highly pure amorphous Si layer 39 is formed. Ion beam, e.g. S
To generate an i-ion beam, 5 i Ha gas is introduced under arc discharge, turned into plasma, and Si ions in the plasma are extracted using a mass spectrometer. When irradiating with a Si ion beam, ion implantation is performed at an acceleration voltage of 100 KV and a dose of I x 10 cm-, for example.

In contrast to conventional selective epitaxial growth, in which Si atoms are generated in a high-temperature (1000°C or higher) gas phase using a Si compound gas and deposited on a semiconductor substrate (epitaxial growth), surface-phase epitaxial growth
1, an amorphous Si layer 39 is formed on the semiconductor substrate 31.
The amorphous Si layer 39 is partially changed into single crystal Si at a low temperature (450 to 550° C.) using the single crystal Si as a seed. Therefore, in the plane phase epitaxial growth, only the amorphous Si layer 39 on the semiconductor substrate 31 can be made into a single crystal at a low temperature, and since no etching is performed during the epitaxial growth, the etching gas components such as H and CI are transferred to the epitaxially grown layer ( The single-crystal Si layer 40, which has no possibility of being mixed into the single-crystal Si layer 40), is continuously formed on the semiconductor substrate 31, and no discontinuous interface occurs.

For example, the conditions for phase epitaxial growth are atmosphere 2N2
Gas pressure: 0.1 torr A'1 ATM temperature:
450 to 550°C Time: 30ml to several hours.

Since the polycrystalline Si layer 39 (a) is a portion that is not single crystallized, etching is performed to remove this portion.Since there is a difference in the etching speed of single crystal Si and polycrystalline Si, By utilizing this difference, only the single crystal Si layer 40 can be left. When performing dry etching, for example, HCI, HF,
When wet etching is performed using CCL, CF, etc., for example, when etching is performed using a mixed solution of HNO3-HF-HzO, etching is performed at 20° C. for several minutes. Note that in this etching process, there is no risk of impurities being mixed into the source region 35 and drain region 36, and only the single crystal Si layer 40 is etched using the difference between the etching speed of single crystal Si and the etching speed of polycrystalline Si. Therefore, the source and drain regions can be formed without using an etching mask as in conventional stacked source/drain transistor manufacturing methods. Therefore, the photolithography process can be omitted.

The method for manufacturing the MOSFET in this example is a single crystal S
The growth of i and the etching are separated into separate steps, and the growth of single crystal Si is performed in an amorphous Si layer 39 which is a surface phase. Therefore, since there is no risk of impurities being mixed in during epitaxial growth, a highly pure single crystal Si layer can be obtained. Moreover, since the photolithography process can be omitted, it is possible to improve the yield by solving the problem of misalignment, shorten the manufacturing process, and shorten the manufacturing time.

As is clear from the above explanation, the MO according to the present invention
In a method for manufacturing a type 5 transistor, a polycrystalline Si layer is deposited on a Si substrate, and accelerated particles are irradiated to make the polycrystalline Si layer or the upper layer of the semiconductor substrate amorphous. , the amorphous Si layer in the source and drain regions is selectively made into a single crystal by subjecting the amorphous Si layer to phase epitaxial growth.

After in-phase epitaxial growth, the single crystal Si substrate is etched to selectively remove the polycrystalline Si layers other than the single crystal Si layers in the source and drain regions. Therefore, a stacked source/drain region with few defects can be obtained at low temperature, and since epitaxial growth and etching are not performed simultaneously, etching gas is not mixed in as an impurity during epitaxial growth, and Si beam is used for accelerated particles. By doing so, it is possible to avoid impurities from being mixed into the polycrystalline Si layer. Additionally, since the single-crystal Si layer for the source and drain regions is formed without using photolithography, the problem of misalignment is resolved, which improves yield, shortens the manufacturing process, and shortens manufacturing time. can.

[Brief explanation of the drawing]

1(a) to (e) are cross-sectional process diagrams showing a method for manufacturing an MO3-type transistor, which is an embodiment of the MO3-type transistor according to the present invention; FIG. 2 is a cross-sectional view of a conventional MO3-type transistor; 3(a) to 3(d) are cross-sectional process diagrams of a stacked source-drain transistor.

Claims (2)

[Claims] (1) In a method for manufacturing a MOS transistor consisting of a gate electrode, an insulating film, a semiconductor layer, and a source/drain, [1] After forming a gate electrode on a single crystal Si substrate constituting the semiconductor layer, forming a source and a drain. a step of depositing a polycrystalline Si layer on the single-crystalline Si substrate including a region where the polycrystalline Si layer is formed; a step of amorphizing the upper layer of the Si substrate; [3] selectively converting the amorphous Si layer in the source and drain regions into a single crystal by heat-treating the amorphous Si layer to cause phase epitaxial growth; [4] A step of etching the heat-treated Si substrate to selectively remove Si layers other than the single-crystal Si layer in the source and drain regions. (2) The method for manufacturing a MOS transistor according to claim (1), characterized in that a Si beam is used as the accelerated particles.