JPH0219461B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in character display devices.

Since kanji characters generally have a large number of strokes, the size of their character shapes should be at least twice as large as the character shapes on character display devices that display only alphanumeric characters and kana (hereinafter referred to as kana). is necessary. Therefore, when trying to realize a character display device for Japanese characters containing kanji, it is necessary to unify the size of the kana figures to the size of the kanji figures, or to
The size of the kana figure is either the same as the size of the character figure on a character display device that displays only kana, or it is made so that kanji of twice the size can also be mixed therein.

Regarding character display devices, those that only display kana were developed earlier and are in circulation, so in order to ensure compatibility with that, a system that mixes kana and kanji that are twice the size was adopted. .

Conventionally, character display devices that mix two types of characters with different sizes have two types of refresh memory, and they store screen information consisting only of large graphic characters and screen information consisting of only small graphic characters out of one screen's worth of screen information. Screen information consisting only of characters is stored separately,
There is a system in which both images are superimposed on the screen at the display stage. In such devices, mutually closely related information for one screen exists separately in two refresh memories, so the processing to associate them and handle them in a unified manner is extremely complex. become. Furthermore, in such a device, the display position of a character on the screen is defined for each small graphic character, so a large graphic character occupies the display position of two small graphic characters. Therefore, it is inconvenient that the display address of large graphic characters cannot be arbitrarily set, for example, it is limited to even-numbered addresses of small graphic characters.

Additionally, in devices that display a mixture of large and small graphic characters, if the line reaches the end of the line after half of the large graphic characters are displayed, the large graphic characters will be displayed as being cut in half. There was a problem.

The present invention was made to solve these problems, and it is possible to centrally manage large graphic characters and small graphic characters using a common refresh memory, and specify the display position using a common cursor. It is an object of the present invention to realize a character display device that can display characters in an easy-to-read manner by appropriately performing line end processing on characters.

The present invention comprises: a display section, an operation section, a control section that processes display information and control information given from the operation section or an external computer to generate display character codes and control signals for each section below; A refresh memory section that stores and outputs the display character code given from the control section, a character generator section that converts the display character code output from the refresh memory section into a dot pattern, and this character generator. and a video signal generating section that converts a dot pattern given from a dot pattern into a serial video signal and outputs it to the display device, wherein the control section converts a dot pattern given by a small graphic character into a serial video signal and outputs it to the display device. A character clock that specifies the update, a load pulse that specifies the update of the dot pattern in the video signal generation section delayed by a predetermined phase from the character clock, and a timing of the serial output of the video signal in the video signal generation section. means for generating a display timing signal that defines a dot clock that defines a display period of one line of an image; When storing a character code having a code that distinguishes it from a graphic character in the refresh memory section, when a code for a large graphic character is stored, the next character code is stored by skipping the next address by one. When a large graphic character identification code is output from the refresh memory (described later),
It is set at the timing of the first character clock to prohibit the passage of the load pulse, and is reset at the timing of the second character clock to cancel the prohibition of the passage of the load pulse. a flip-flop circuit that continuously outputs a video signal from a video signal generating section for a period twice as long as , and a one-line display period defining signal that is a logical sum of the Q output of this flip-flop circuit and the display timing signal and sent to the video signal generating section. Even if the display timing signal specifies the end of the display period of one line when half the video signal of the large graphic character is output at the end of the line,
and a means for causing the video signal generation section to continue outputting the video signal until the remaining half is output, and the refresh memory section stores an address counter for counting the character clock and a character code forming the display screen. It also has a refresh memory that outputs the stored contents from the address specified by the count value of the address counter, and the character generator section has a dot pattern for large graphic characters and a dot pattern for small graphic characters. and a character generator that stores a character code given from the refresh memory and outputs a dot pattern of a corresponding character according to a character code given from the refresh memory and an identification code included therein; a shift register that sets a dot pattern given from the control unit according to a load pulse given from the control unit, shifts the dot pattern according to a dot clock given from the control unit, and outputs the dot pattern serially; This character display device has a gate that is opened and closed in response to a display period defining signal for one row to control passage of a serial output signal from a shift register.

Hereinafter, the present invention will be explained in detail with reference to Examples. In the following description, large graphic characters are represented by Kanji characters, and small graphic characters are represented by non-Kanji characters, but large graphic characters and small graphic characters are not limited to Kanji characters and non-Kanji characters.

FIG. 1 is a conceptual block diagram of an embodiment of the present invention. In FIG. 1, CRT is a display section and KEY is an operation section. These display section CRT and operation section KEY
Man/machine communication is carried out by

CNT is the control section, REF is the refresh memory section,
CHR is a character generator section, and SYC is a video signal generation section.

The control unit CNT is given information to be displayed and control information from an external computer (not shown) and an operation unit KEY. The control unit CNT processes the given information and stores the code of the displayed character in the refresh memory unit REF, and also generates a predetermined control signal and sends it to the refresh memory unit REF,
Provided to character generator section CHR and video signal generation section SYC.

The code of the character to be displayed is read from the refresh memory section REF at a predetermined timing, and is converted into a dot pattern by the character generator section CHR.
It is given to the display section CRT through SYC.

A control unit CNT, a refresh memory unit REF,
FIG. 2 shows a more detailed configuration of the portions related to the present invention of the character generator section CHR and the video signal generation section SYC. In Fig. 2, 1 is the refresh memory main body (hereinafter simply referred to as the refresh memory), 2 is an address counter for reading it, and 3 is a character for kanji.
4 is a character generator for non-kanji characters, 5 is a shift register, 6 is a flip-flop circuit, and 7, 8, 9, and 10 are gate circuits, respectively.

In order to control each of these circuits, the control section CNT
Various control signals are given from. Among those signals, those related to the description of the present invention are shown below.
Character clock CHRCLK, load pulse
LOAD-, dot clock DOTCLK, and display timing signal DSPTMG.

Character clock CHRCLK and load pulse
LOAD- is given for each non-Kanji character. The dot clock DOTCLK is given corresponding to the dots that make up the character. Display/
The timing signal DSPTMG is given corresponding to one raster scanning period of the display CRT.

Address counter 2 has a character clock.
CHRCLK is given. Address counter 2 is
This clock is counted, and the read address of the refresh memory 1 is designated by the counted value. The character code read from the refresh memory 1 is given to a character generator 3 for kanji and a character generator 4 for non-kanji. At this time, a signal KANJI is also given to distinguish whether the character code is a kanji or a non-kanji. According to this signal, the kanji character code is set in the kanji character generator 3, and the non-kanji character code is set in the non-kanji character generator 4.
These character generators 3 and 4 output dot pattern signals corresponding to the set character codes, respectively, and are applied to the shift register 5. The number of dots in the character code for kanji is twice as many as the character code for non-kanji.

The dot pattern applied to the shift register 5 is set by a pulse applied to the load terminal LD, shifted by the dot clock DOTCLK applied to the clock terminal CC, and serially output one dot at a time. The output pulse of the shift register 5 is guided to the display section CRT through the AND gate 10.

The character clock CHRCLK is also applied to the T terminal of the flip-flop circuit 6. In this flip-flop circuit 6, the logical product of the kanji designation signal KANJI output from the refresh memory 1 and the Q- output of the flip-flop circuit 6 is applied to the D terminal through the AND gate 7, and the reset terminal R is given the A reset signal is provided based on the leading edge of display timing signal DSPTMG.

The load pulse LOAD- is applied to the load terminal LD of the shift register 5 through the NAND gate 8. The opening and closing of the NAND gate 8 is controlled by the Q-output of the flip-flop circuit 6.

The display timing signal DSPTMG is
By the OR gate 9, the flip-flop circuit 6
It is ORed with the Q output of and given to the AND gate 10 as an opening/closing control signal.

In such a device, the character code stored in the refresh memory 1 is, for example, the fourth character code.
As shown in the figure, 16 bits are used. In such a character code, the first bit is a code that distinguishes between Kanji (large graphic characters) and non-Kanji (small graphic characters), with 0 representing a non-Kanji character and 1 representing a Kanji character. Other bits are treated as the original character code.

Conceptually, the address space of refresh memory 1 is as shown in Figure 5.
A storage address for each character code is provided corresponding to the display position of the non-kanji character on the screen. FIG. 5 shows an example of a display screen having 80 characters x 25 lines.

A character code as shown in FIG. 4 is written to each address of the refresh memory 1, but
At this time, when a kanji code is written, the next character code is not written to the next address, but is written to the next address. That is, the address next to the address where the Kanji code is written on the refresh memory is blank. Such writing is performed by the control unit CNT.
This is done by a program or appropriate firmware.

The operation of the device configured in this way is as follows. An explanatory diagram of the operation is shown in FIG.

When the display timing starts, the display
The timing signal DSPTMG is turned on, and this turns on the AND gate 10 for dot pattern output.
will be held. Additionally, the leading edge of the display timing signal DSPTMG resets the flip-flop circuit 6, and its Q-output opens the NAND gate 8, causing the load pulse LOAD-
It becomes possible to pass through.

In this state, when the character clock CHRCLK occurs, the address counter 2 that counted it
A one character code is read from the address corresponding to the count value and given to the character generators 3 and 4. When the character code is a non-kanji character, the dot pattern corresponding to the character code is read out from the character generator 4 for non-kanji characters, and the dot pattern is read out from the character generator 4 for non-kanji characters.
The shift register 5 is controlled by the load pulse LOAD which is generated with an appropriate phase delay from CHRCLK.
is set to And the dot clock
shifted by DOTCLK and gate 1
Output through 0.

This operation is repeated as long as the non-kanji continues. During that time, the kanji identification signal KANJI output from refresh memory 1 is off, so
AND gate 7 is closed, so flip-flop circuit 6 remains in the reset state.

When the character code read from the refresh memory 1 becomes a kanji character, the kanji identification signal KANJI is turned on and the character code is set in the kanji character generator 3. As a result, the corresponding dot pattern is output from the kanji character generator 3, and the load pulse is
It is set in shift register 5 by LOAD-. At this time, since Kanji characters are large graphic characters, their dot patterns consist of twice as many dots as non-Kanji characters. The set dot pattern is shifted by the dot clock DOTCLK and output serially.

In the flip-flop circuit 6 in the reset state, the kanji identification signal KANJI applied from the refresh memory 1 is turned on, so the output signal of the AND gate 7 is turned on, and the input signal at the D terminal is turned on.

In this state, the next character clock CHRCLK
When this occurs, flip-flop circuit 6 is set, thereby closing NAND gate 8. The Q output signal of flip-flop circuit 6 is ORed with display timing signal DSPTMG by OR gate 9. Further, the input signal of the D terminal is turned off by applying the Q-output signal to the AND gate 7.

As the character clock CHRCLK counts up, the next address is read from refresh memory 1, but since the contents of the address next to the address where the kanji code is stored is blank, no characters are read. . Also, the passage of the next load pulse LOAD- is NAND gate 8.
Therefore, there is no new set of dot patterns in the shift register 5. For this reason,
The dot pattern of the previous kanji set in the shift register 5 is then output. As a result, a dot pattern for kanji consisting of twice as many dots as non-kanji characters is output for the display period of two non-kanji characters, and large graphic characters are output with dots equal to two small graphic characters. displayed in the display pane.

Furthermore, the next character clock CHRCLK
When this occurs, the flip-flop circuit 6 is reset and the NAND gate 8 is opened because the input signal at the D terminal is off. That is, when the kanji display starts, the flip-flop circuit 6
The set state is continued until the dot pattern is completely output, the Q output signal is supplied to the OR gate 9, and the NAND gate 8 is closed by the Q- output signal.

Since the flip-flop circuit 6 has been reset, the load pulse for a new character passes through the NAND gate 8 and is applied to the character generator 3.
Alternatively, the dot pattern read from 4 is set in the shift register 5.

Thereafter, kanji and non-kanji characters are displayed in the same manner.

When the character display ends at the 79th character on the display screen, the display timing signal DSPTMG
is turned off until the next raster scan begins.
Therefore, if things continue as they are, the kanji displayed at the 79th character will be cut in half.
This is solved by ORing the display timing signal DSPTMG and the Q output signal of the flip-flop circuit 6 using the OR gate 9.

That is, by this logical sum, the AND gate 10 outputs the display timing signal.
Even if DSPTMG is turned off, it remains open as long as the Q output of flip-flop circuit 6 is on.
Moreover, when displaying a kanji character, the Q output signal of the flip-flop circuit 6 remains on until the dot pattern is completely output, so that the 79th kanji character is completely displayed up to the 80th character. At this time, the screen of the display device CRT is 80, as shown in Figure 6.
It becomes an expanded form to the letter.

As described above, according to the present invention, screen information in which large graphic characters and small graphic characters coexist can be stored in a common refresh memory and managed in a unified manner. In addition, the storage address of large graphic characters in the refresh memory can be determined for each small graphic character, so the display position can be set arbitrarily using a common cursor, without distinguishing between large and small graphic characters. .

In addition, even if the line reaches the end after half of the large graphic characters are displayed, the display starts on a new line after the remaining half has been displayed. As a result, even if large graphic characters and small graphic characters coexist, the large graphic characters can be displayed in an easy-to-read manner by performing appropriate line end processing.

Although the present invention has been described above with reference to preferred embodiments, the present invention may have various embodiments within the scope of the claims.

[Brief explanation of drawings]

Fig. 1 is a conceptual configuration diagram of an embodiment of the present invention;
The figure is a conceptual configuration diagram of the main parts of Figure 1, and Figure 3 is
FIG. 2 is an explanatory diagram of the operation of the apparatus, FIG. 4 is a configuration diagram of a character code, and FIGS. 5 and 6 are conceptual configuration diagrams of a refresh memory or a display screen. CRT...display section, KEY...operation section, REF...refresh memory section, CHR...character generator section, SYC...video signal generation section, 1...refresh memory, 2...address counter, 3,
4... Character generator, 5... Shift register, 6... Flip-flop circuit, 7, 8, 9,
10...Gate.

Claims (1)

[Scope of Claims] 1. A display section, an operating section, and a control section that processes display information and control information given from the operating section or an external computer to generate display character codes and control signals for each section below. a refresh memory section that stores and outputs the display character code given from the control section; a character generator section that converts the display character code output from the refresh memory section into a dot pattern; In a character display device comprising a video signal generation section that converts a dot pattern given from a character generator section into a serial video signal and outputs it to the display device, the control section is configured to: convert one of the displayed characters into a small graphic character; A character clock that specifies the update of each character, a load pulse that specifies the update of the dot pattern in the video signal generator that is delayed by a predetermined phase from the character clock, and a serial output of the video signal in the video signal generator. means for generating a dot clock that defines the timing of the image; and a display timing signal that defines the display period of one line of the image; When storing a character code that has a code that distinguishes characters from small graphic characters into the refresh memory section, if a code for a large graphic character is stored, the next character code is stored by skipping the next address. When a large graphic character identification code is output by reading from the storage means and the refresh memory described later,
It is set at the timing of the first character clock to prohibit the passage of the load pulse, and is reset at the timing of the second character clock to cancel the prohibition of the passage of the load pulse. a flip-flop circuit that continuously outputs a video signal from a video signal generating section for a period twice as long as , and a one-line display period defining signal that is a logical sum of the Q output of this flip-flop circuit and the display timing signal and sent to the video signal generating section. Even if the display timing signal specifies the end of the display period of one line when half the video signal of the large graphic character is output at the end of the line,
and a means for causing the video signal generation section to continue outputting the video signal until the remaining half is output, and the refresh memory section stores an address counter for counting the character clock and a character code forming the display screen. It also has a refresh memory that outputs the stored contents from the address specified by the count value of the address counter, and the character generator section has a dot pattern for large graphic characters and a dot pattern for small graphic characters. and a character generator that stores a character code given from the refresh memory and outputs a dot pattern of a corresponding character according to a character code given from the refresh memory and an identification code included therein; a shift register that sets a dot pattern given from the control unit according to a load pulse given from the control unit, shifts the dot pattern according to a dot clock given from the control unit, and outputs the dot pattern serially; A character display device comprising: a gate that is opened and closed by a given display period defining signal for one line to control passage of a serial output signal of a shift register.