JPS5960475A - Character display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] This defense relates to improvements in character display devices.

Kanji generally has a large number of strokes, so the size of the character shapes is at least as large as alphanumeric characters or kana (hereinafter referred to as kana). It needs to be twice as large. When I tried to realize this IC, a character display device for Japanese characters mixed with kanji,
Either the size of the kana figure should be unified to the size of the kanji figure, or the size of the kana figure should remain the same as the size of the character figure on a character display device that only displays kana, but be doubled. Either the size of kanji can be mixed, or one of these is done.

Regarding character display devices, the kana display device, Jino's, was developed first and is now in circulation, so from the standpoint of ensuring compatibility with that device, we decided to use a system that mixes kana and kanji of the size 2 ([1]. Adopted.

Conventional character display devices that mix two types of characters of different sizes have two types of refresh memory, and they store one screen's worth of screen information, as well as large graphic characters (
There is a system in which the screen information consisting of small letters (1) and the screen information consisting of small graphic characters (1) are stored separately, and the images of both are superimposed on the screen at the display stage. In such devices, the information for one screen that is closely related to each other exists in two separate refresh memories, so the processing to associate them and handle them in a unified manner is extremely complicated. become. Mano c % In such a device, the character display position on the screen is defined for each small graphic character, so the large graphic character occupies the display position of two small graphic characters. For this reason, the display address of large graphic characters is limited to even-numbered addresses of small graphic characters, for example, and cannot be arbitrarily set.

It is an object of the present invention to store screen information containing a mixture of graphic characters and small graphic characters in a common refresh memory so that it can be centrally managed; To provide a character display device in which display positions can be arbitrarily set using a common cursor without distinction.

The present invention includes a display section, an operation section, and a control section that processes display information and control information given from this operation device or an external HI calculator to generate display character codes and control signals for each section below. , a refresh memory section that stores and outputs the code of the display character given from this control section, and a refresh memory section that stores the code of the display character output from this refresh memory section.
A character generator section that converts into a pattern and a driver l- given from this character generator section.
In a character display device comprising a video signal generating section that converts a pattern into a serial video signal and outputs it to the display device, the control section specifies updating of each displayed character converted into a small graphic character. A character clock, a load pulse that specifies the update of the dot pattern in the video signal generator with a delay of J, and a dot clock that specifies the timing of serial output of the video signal in the video signal generator. and means for generating a display timing signal that defines the display period of one line of an image; When storing a character code that identifies a code to the right in the refresh memory section, when a code for a large graphic character is stored, the next character code is stored by skipping the next address. , When the large graphic character identification code is output by reading from the refresh memory mentioned above, the next character mark [1-1-1-1-1-1-1] is prohibited and the video signal generator is currently outputting it. a means for generating a control signal for continuously outputting the video signal until the next load pulse arrives; means for supplying a one-line display period regulation signal to the video signal generation section; the refresh memory section includes an address counter for counting the character clock by 81; It has a refresh memory that outputs the stored contents from the address specified by the count value of the address counter, and the character generator section has a dot pattern for large graphic characters and a dot pattern for small graphic characters. a character generator that stores a pattern and outputs a dot pattern of a corresponding character according to a character code given from the refresh memory and an identification code included therein; a shift register that shifts the dot pattern according to the load pulse given from the control section and outputs it serially according to the dot pattern given from the control section; The above object is achieved by means of a character display device 5 having gates that are opened and closed by a display period defining signal for one line to control the passage of serial output signals from shift 1 to the register.

Hereinafter, the present invention will be explained in detail with reference to Examples.

In the following description, large graphic characters are represented by Kanji e, and small graphic characters are represented by non-kanji U, but large graphic characters and small graphic characters are not limited to kanji and non-kanji.

FIG. 1 is a conceptual block diagram of an embodiment of the present invention.

FIG.
Man/machine communication is performed by T and the operating section KEY.

CNT is a control unit, REF is a refresher memory unit, and C
I-11-( is a character generator section, and SYC is a video signal generation section.

Information to be displayed and control information are directed to the control unit CNT from the outside: 1R (jJH not shown) and the operation unit KEY. The control unit CNT processes the given information and stores the code of the displayed character in the refresh memory unit R'EF, and also generates a predetermined control signal and sends it to the refresh memory unit REF and the controller.・Generator section CI-1rt 't video signal generation section S
Give to YC.

The code of the displayed character is read out from the refresh memory section REF at a predetermined timing, converted into a dot pattern by the character generator section CHR, and provided to the display section CRT through the video signal generation section SYC.

A more detailed configuration of the parts related to the present invention is shown in FIG. . In FIG. 2, 1 is the refresh memory main body (hereinafter simply referred to as the refresh memory), 2 is an address counter for reading the memory, and 3 is an address counter for reading the refresh memory.
4 is a character generator for Kanji characters, 4 is a character generator for non-Kanji characters, 5 is a shift register, 6 is a flip-flop circuit, and 7, 8, 9, and 10 are gate circuits, respectively.

In order to control each of these circuits, various control signals are given from the control section CNT. Among these signals, those related to the explanation of the present invention are: Killer Rafter Flock C
There are HRCLK, load pulse L○ΔD-, dot clock DOTCLK, and display timing control No. 6 DS Pl-M Gr.

A kill rough block CI-I RCL K and a load pulse L OA D- are given to each non-Kanji character. Dora 1-ri 1 Kotoku I) O'r CL K is given corresponding to Dora 1- which constitutes the character. Display timing signal o sp T-M a IL,
The ``I'' scanning amount of the raster of the display CRT is given correspondingly.

At 1 counter 2, =I: 12 raktak L1
TSCT I RCL K is given. The address counter 2 counts this tally to 51, and the count is 11 (l
The read address of refresh memory 1 is specified by . The character code read from the refresh memory 1 is applied to a character generator ζ3 for kanji and a character generator 4 for non-kanji. that time,
Signal KANJ to distinguish whether the character code is a kanji or a non-kanji
I is also given. According to this signal, the kanji character code is set in kanji character generator 3, non-kanji character code number 3 is set, and non-kanji character code number 4 is set in kanji character generator 3.
Retz 1- is given. These 21 character generators 3.4 output dot pattern signals corresponding to the character codes sent to the cellar 1, respectively, and are applied to the shift register 5. The number of dots in the character code for kanji is twice as many as the character code for non-kanji.

The dot pattern given to shift 1 to register 5 is set to -C by the pulse given to the load terminal LD, and the dot pattern given to the clock terminal CC is set to -C by the pulse given to the load terminal LD.
It is shifted by TCLK and serially output one dot at a time. The output pulse of the shift register 5 is guided to the display section CRT through the AND gate 10.

The character clock CHRCLK is also applied to the T terminal of the Noritsubu flop circuit 6. In this Noritsubu flop circuit 6, a logical product of the kanji designation signal KANJI outputted from the refresh memory 1 and the Q-output of the Noritsubu flop circuit 6 is applied to the D terminal through the Andogoo 1-7. The reset terminal R has a reset 1 signal based on the leading edge of the display timing signal DSPTMG.
~A signal is given.

U-dobars 10ΔD- is applied to the load terminals LD of shift 1 to register 5 through Nandogoo l to 8. 1 lil 11) kL of the Nant gate 8 is controlled by the Q-output of the Noritub Sorotub circuit 6.

Display timing signal RD SP-1-M
G is ORed with the Q output of the 79771071 circuit 6 by the OAGs 1 to 9, and is given to the AND gate 10 as an opening/closing control signal.

In such a device, the character code stored in the refresh memory 1 is, for example, 1 as shown in FIG.
A bit consisting of 6 bits is adopted. In such a character code, the first pip 1- is a kanji (large graphic character)
It is used as a code to distinguish between non-kanji (small graphic characters), with 0 representing a non-kanji and 1 representing a kanji. The other characters, P1-, are used as the original character code.

Conceptually, the address space of the refresh memory 1 is as shown in FIG. There is. Figure 5 shows that the display screen has a configuration of 80
An example of 25 characters x 25 lines is shown.

At each address of the refresh memory 1, a fourth
The character code shown in the figure is written, but at that time, when the kanji =1-d is written, the character code after the ``i'' is not written to the next address, but is written to the next address. will be written to. In other words, the address next to the address where the Kanji code is written on the refresh memory is blank. Such writing is performed by the control unit CN.
This is done by the King's program or appropriate firmware.

The operations of the trading system configured in this way are as follows. An explanatory diagram of the operation is shown in FIG.

When the display timing begins, the display timing signal D S P T M G is turned on, thereby opening the AND gate 1Q for outputting the driver 1 pattern. In addition, the display timing signal DSI
) The leading edge of TMG causes the flip-flop circuit 6 to be reset to 1, and its Q-output causes the NAND game to be reset.
1-8 is heard, and the state is passed through U-dobars LOAD-.

In this state, when the -1-Yarakuta clock CHRcLK is generated, one character code is read out from the address corresponding to the count value of the address counter 2 by dividing it, and is sent to the chitractor generator 3.4. Given.

When the character code is a non-kanji character, a dot pattern corresponding to the character code is read from the character generator 4 for non-kanji characters, and then the appropriate pattern is read out from the character code CHRCLK. (The shift 1 is set to the register 55 by the pulse LOAD which is generated by shifting. Then, the shift 1 is set to the register 55.
It is shifted 1- by O'r CLK and output through AND GO l-10.

This 4T operation is repeated as long as the non-kanji characters continue. During that time, the kanji identification signal KANJI output from refresh memory 1 is off, so
7 is closed, so the flip-flop circuit 6 remains in the reset state.

When the character code read from refresh memory 1 becomes a kanji, the kanji identification signal KANJI turns on.
The character code is set in the kanji character generator 3. As a result, the corresponding dora 1 pattern is output from the kanji character generator 3, and the shift 1 register 5 is output by the load pulse LOAD-.
is set to At this time, the kanji is a large graphic character (pa), so its dot pattern consists of twice the number of dots as for non-kanji characters.The set dot patterns are shifted by the dot clock DOTCLK and output serially. be done.

In the Noritsu flop circuit 6 which is in the state of relay 1, C
1 Kanji identification signal K given from refresh memory 1
Since ANJ I is turned on, the output horn signals of ANDGOO 1-7 are turned on, and the input signal of the D terminal is turned on.

When the next 1-tractor clock CHRCLK is generated in this state, the Noritub flop circuit 6 is hit, thereby closing the Nant gate (3). Display timing signal D S P T M G by 〇
It is logically summed with. Further, the input signal of the I) terminal is turned off by applying the Q-output signal to the node 7.

Character Taku L1 Tsuku Cl-I RCL K's Karan 1
As the C1 refresh memory 1 moves up, the next address is read out from the C1 refresh memory 1, but since the kanji code is stored and the contents of the address next to the address C is blank, no characters are read out. Also, the next load pulse LO
Since the passage of AD- is prohibited by the Nant gate 8, there is no new set of Dora 1~ patterns in the shift register 5. Therefore, the previous kanji dot pattern set in the shift register 5 is output continuously. As a result, a dot pattern for kanji consisting of twice the number of dora 1- as non-kanji characters is output for a display period of two non-kanji characters, and large graphic characters are displayed in a display section corresponding to two small graphic characters. will be displayed.

Furthermore, when the next character clock CHRCLK is generated, since the input signal of the D terminal is off,
When the kanji display starts, the Noritsubu flop circuit 6 (flip flop 1) will open the gate 8. Continuing the set state, the Q output signal is supplied to the OR gate 9, and the Q-output signal closes the gates 1-8.

As the flip-flop circuit 6 is reset, a load pulse for a new character passes through the Nant gate 8, and the dot pattern read from the gileractor generator 3 or 4 is transferred to the shift register 5. do.

Thereafter, kanji and non-kanji characters are displayed in the same manner.

When the character display ends at the 79th character on the display screen, the display timing signal DSPTMG becomes A) until scanning of the next raster begins.

Therefore, if things continue as they are, the kanji displayed at the 79th character will be cut in half, but such a problem can be solved by display timing advice @ D S by Oagoo 1-9.
Theory 1 between PTM G and the Q output signal of the flip-flop circuit 6! I! solved by the sum.

In other words, by this logical sum, Andgoo 1-10 is the display timing (e + 9 D S +)
Even if the 7MG is turned off, the Q output of the flip-flop circuit 6 is heard as long as it is A-on, and what's more, the Q output signal of the flip-flop circuit 6 is displayed as a kanji character. - Continue A until the pattern is completely output.
Therefore, the 79th kanji is completely displayed until the 80th character is C or the number. At this moment, the screen of display unit c RT is as follows.
As shown in Figure 6, it is expanded to the 80th character.

As described above, according to the present invention, it is possible to store screen information containing a mixture of large graphic characters and small graphic characters in a common refresh memory and to embed the screen information in a unified manner. In addition, the storage address of large graphic characters to be pulled into the refresh memory can be determined by the small graphic character position, so the display position can be set arbitrarily using a common cursor, regardless of whether large or small graphic characters are used. I can do it.

Hereinafter, the present invention has been described in terms of preferred embodiments (1-1), but various embodiments may be made within the scope of the claims.

[Brief explanation of the drawing]

Fig. 1 is a conceptual block diagram of an embodiment of the present invention, Fig. 2 is a conceptual block diagram of the main parts of Fig. 1, Fig. 3 is an explanatory diagram of the operation of the device in Fig. 2, and Fig. 4 5 and 6 are conceptual diagrams of the refresh memory or display screen. CRT...display section, KEY...operation section, RIEF...
...Refresh memory part, CI-IR...Character generator part, SYC...Videt A signal valve."
Part 2 1... Refresh memory, 2... j/dress counter, 3.4... Character generator, 5
...Shift register, 6...Fritzbuf [171 circuit, 7,8°9.10...Ghet 480

Claims (1)

[Claims] A display unit, an operating unit, and a control unit that processes display information and control information provided from an external camera to control each of the following units, such as display character codes. A control unit that generates a signal, a fresh memory unit that stores and outputs the =1- code of the display character given from this control unit, and a controller that outputs the =1- code of the display character output from the refresh memory unit. A character display device comprising a character generator section that converts the dot pattern into a pattern, and a video signal generation section that converts the dot pattern given from the character generator section into a serial video signal and outputs it to the display device, comprising: a control section; is at a predetermined phase from the character clock that specifies the update of each display character converted into small graphic characters (the video A signal is generated after a delay). 1 - A load pulse that specifies pattern update, a dot clock that specifies the serial output timing of the via A signal that goes to the video signal generator, and a display timing signal that specifies the display period of one line of the image. -, and refresh the character code that is specified by the one-word format 1~ that is common to large and small graphic characters and that sets the code for identifying large and small graphic characters to the right. When storing the code of a large graphic character in the memory section, there is a means for storing the code for the next character by skipping the next 77th dress, and a method for storing the code for the next character, as described later. , when a large graphic character identification code is output by reading it, the load pulse associated with the next character clock is prohibited, and the video signal currently being output by the video signal generator is further input to the next [1-de pulse]. means for generating a control signal that avoids continuous output until a video signal generating section generates a logical sum of the output signal of the continuous control signal generating means and the display timing signal;
The refresh memory section has an address counter for counting the character clock by 51, and a means for storing character codes constituting the display screen. It has a refresh memory that outputs stored contents from a specified address, and a character generator section stores dot patterns for large graphic characters and dot patterns for small graphic characters, and outputs the characters given from the refresh memory. The video signal generating section has a character generator that outputs a dot pattern of a corresponding character according to the code and the identification code included therein, and the video signal generating section converts the dot pattern given from the chitractor generator into a load pulse given from the control section. This dot pattern is shifted and serially output according to the driver I-L signal given from the control section. A character display device having a shifter 1 and a shifter 1 which controls passage of a serial output signal of the register.