JPH02189953A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02189953A JPH02189953A JP902289A JP902289A JPH02189953A JP H02189953 A JPH02189953 A JP H02189953A JP 902289 A JP902289 A JP 902289A JP 902289 A JP902289 A JP 902289A JP H02189953 A JPH02189953 A JP H02189953A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- wiring
- semiconductor integrated
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 230000010354 integration Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体集積回路装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.
第4図は従来の多層配線構造の半導体集積回路装置の断
面図で、図中、L1〜L4は配線層、■1〜I4は絶縁
層、T1〜T3はスルーホールである。FIG. 4 is a sectional view of a conventional semiconductor integrated circuit device having a multilayer wiring structure, in which L1 to L4 are wiring layers, 1 to I4 are insulating layers, and T1 to T3 are through holes.
配線層L1.L2.L3.L4が電気的に同一ノードの
配線を実現・する場合、次のような手順で行なう。Wiring layer L1. L2. L3. When L4 realizes wiring of the same electrical node, the following procedure is used.
工程■、絶縁層■1の上に配線層L1を形成する。Step (2): A wiring layer L1 is formed on the insulating layer (2) 1.
工程■、配線層L1の上に絶縁層I2を形成する。Step (2): forming an insulating layer I2 on the wiring layer L1;
工程■、絶縁層■2にスルーホールT1をあける。Step (2): Drill a through hole T1 in the insulating layer (2).
工程■、絶縁層I2の上に配線層L2を形成する0この
時、スルーホールT1を通じて、配線層L1とL2は電
気的に同一ノードとなる。Step (3): Forming the wiring layer L2 on the insulating layer I2 At this time, the wiring layers L1 and L2 become electrically at the same node through the through hole T1.
上記工程■〜工程■を順次くり返えすことによって、配
線層L1〜L4、絶縁m11〜工4、スルーホールT1
〜T3ヲ形成する。この時、スルーホールT1〜T3を
通じて、配線層L1〜L4は電気的に同一ノードとなる
。By sequentially repeating the above steps ① to ②, the wiring layers L1 to L4, the insulation m11 to 4, and the through hole T1
~ Form T3. At this time, the wiring layers L1 to L4 become electrically the same node through the through holes T1 to T3.
ここで、配線層L2はスルーホールT1部分で段差がで
き、その影響で絶縁農工3もT1部分で段差ができる。Here, a step is formed in the wiring layer L2 at the through hole T1 portion, and due to this, a step is also formed in the insulation layer 3 at the T1 portion.
従って、スルーホールnを形成する場合、この段差を避
けて形成する。スルーホールT3についても同様で、ス
ルーホールT1とスルーホールT2の位置からある程度
能れた位置に形成する。Therefore, when forming the through hole n, it is formed while avoiding this step. The same applies to the through hole T3, and it is formed at a position that is a certain distance from the positions of the through hole T1 and the through hole T2.
従来の半導体集積回路装置は以上のように構成されてい
たので、複数の配線層を電気的に同一のノートとする時
に各配線層間に設けるスルーホールの位置をずらす必要
があるために、回路の集積度向上を妨げるという問題点
があった。Conventional semiconductor integrated circuit devices have been configured as described above, so when multiple wiring layers are electrically connected to the same node, it is necessary to shift the position of the through holes between each wiring layer, which causes problems in the circuit. There was a problem in that it hindered the improvement of the degree of integration.
この発明は上記のような問題点を解消するためになされ
たもので、複数の配線層を電気的にrJ −のノードと
する時でも、スルーホールによる回路集積度向上を妨げ
ないよう(こすることを目的とする。This invention was made in order to solve the above-mentioned problems, and even when multiple wiring layers are electrically connected to rJ - nodes, it is possible to avoid impeding the improvement of circuit integration by using through holes. The purpose is to
この発明に係る半導体集積回路装置は電気的に同一ノー
ドの複数の配線層をただ1つのスルーホールで接続する
ようにしたものである。In the semiconductor integrated circuit device according to the present invention, a plurality of wiring layers at the same electrical node are electrically connected by a single through hole.
この発明における半導体集積回路装置は電気的に同一ノ
ードの複数の配線層をただ1つのスルーホールで接続す
るようにしたので、スルホールによる回路集積度向上を
妨げることなく形成ができる。In the semiconductor integrated circuit device of the present invention, a plurality of wiring layers at the same electrical node are electrically connected by a single through hole, so that the semiconductor integrated circuit device can be formed without hindering the improvement of circuit integration due to through holes.
以下、この発明の一実施例を図について説明する。第1
図において、L1〜L4は配線層、■1〜■4は絶縁層
、TIはスルーホールである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, L1 to L4 are wiring layers, 1 to 4 are insulating layers, and TI is a through hole.
次に動作について説明する。配線層Ll、L2.L3゜
L4が電気的に同一ノードの配線を実現する場合、次の
ような手順で行う。Next, the operation will be explained. Wiring layers Ll, L2. When wiring L3 and L4 are electrically connected to the same node, the following procedure is used.
工程(D、 絶縁層■1の−にに配線層L1を形成す
る。Step (D) A wiring layer L1 is formed on the insulating layer (1).
工程■、配線層L1の上に絶縁層■2を形成する。Step (2): An insulating layer (2) is formed on the wiring layer L1.
工程■、工程■と工程■をくり返して、配線層L1〜L
3、及び絶縁層11〜■4を形成する。Repeat process ■, process ■, and process ■ to form wiring layers L1 to L.
3 and insulating layers 11 to 4 are formed.
工程■、絶縁層14から配線層L1まで貫くスルーホー
ル1゛1をあける。Step (2): A through hole 1'1 penetrating from the insulating layer 14 to the wiring layer L1 is opened.
工程■、絶縁層I4の上に配線層L4を形成する。この
時、配線層L1〜L4はスルーホールTIヲ通じて、電
気的に同一ノードとなる。Step (2): forming a wiring layer L4 on the insulating layer I4; At this time, the wiring layers L1 to L4 become electrically the same node through the through hole TI.
なお、上記実施例では、スルーホールT1を円筒形とし
た場合を示したが、第2図に示すよう(こ、円錐形状の
スル−ホールにすると、各配線層の接続部分のml積が
大きくなり、接続抵抗の低い接続を実現できる。In the above embodiment, the through hole T1 is cylindrical, but as shown in FIG. Therefore, a connection with low connection resistance can be realized.
また、上記円錐形状のスルーホールにおいて、配線Pi
はエツチングされず、絶縁層のみをエツチングするとい
う選択的エツチングを行ない、スルーホールの形状を第
3図に示す様段階状にすれば、さらに抵抗の低い接続を
実現できる。In addition, in the conical through hole, the wiring Pi
If selective etching is performed in which only the insulating layer is etched without being etched, and the shape of the through hole is made stepwise as shown in FIG. 3, a connection with even lower resistance can be realized.
以上のようにこの発明によれば、多層配線構造の半導体
集積回路装置の複数の配線層を電気的に同一ノードに接
続する場合に、スルーホールによる回路集積度向上を妨
げることなく実現できるという効果がある。As described above, according to the present invention, when a plurality of wiring layers of a semiconductor integrated circuit device with a multilayer wiring structure are electrically connected to the same node, it is possible to realize the improvement of circuit integration by through holes without hindering the improvement of circuit integration. There is.
第1図はこの発明の一実施例である半導体集積回路装置
の断面図、第2図、第3図はこの発明の他の実施例であ
る半導体集積回路装置の断面図、第4図は従来の半導体
集積回路装置の断面図を示す。
図中、L1〜L4は配線層、■1〜■4は絶縁層、T1
〜T3はスルーホールを示す。
なお、図中、同一符号は同一 または相当部分を示す。FIG. 1 is a sectional view of a semiconductor integrated circuit device which is an embodiment of the present invention, FIGS. 2 and 3 are sectional views of a semiconductor integrated circuit device which is another embodiment of the invention, and FIG. 4 is a conventional 1 shows a cross-sectional view of a semiconductor integrated circuit device. In the figure, L1 to L4 are wiring layers, ■1 to ■4 are insulating layers, and T1
~T3 indicates a through hole. In addition, the same symbols in the figures indicate the same or equivalent parts.
Claims (1)
層とを有する半導体集積回路装置において、前記複数の
配線層と前記複数の絶縁層を貫くスルーホールを有する
ことを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a plurality of wiring layers and a plurality of insulating layers that insulate the wiring layers from each other, the semiconductor integrated circuit device having a through hole passing through the plurality of wiring layers and the plurality of insulating layers. circuit device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP902289A JPH02189953A (en) | 1989-01-18 | 1989-01-18 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP902289A JPH02189953A (en) | 1989-01-18 | 1989-01-18 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02189953A true JPH02189953A (en) | 1990-07-25 |
Family
ID=11709032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP902289A Pending JPH02189953A (en) | 1989-01-18 | 1989-01-18 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02189953A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07153842A (en) * | 1993-11-30 | 1995-06-16 | Nec Corp | Semiconductor device and its manufacture |
US5760429A (en) * | 1993-06-01 | 1998-06-02 | Matsushita Electric Industrial Co., Ltd. | Multi-layer wiring structure having varying-sized cutouts |
JP2005044927A (en) * | 2003-07-25 | 2005-02-17 | Kyocera Corp | Piezoelectric actuator and its manufacturing method, and liquid discharge apparatus |
JP2009037115A (en) * | 2007-08-03 | 2009-02-19 | Sony Corp | Semiconductor device, its manufacturing method, and display device |
JP2012231148A (en) * | 2012-06-04 | 2012-11-22 | Sony Corp | Semiconductor device, method of manufacturing the same, and display apparatus |
US8836135B2 (en) | 2011-03-01 | 2014-09-16 | Kabushiki Kaisha Toshiba | Semiconductor device with interconnection connecting to a via |
JP2015076299A (en) * | 2013-10-10 | 2015-04-20 | セイコーエプソン株式会社 | Light-emitting device and electronic equipment |
-
1989
- 1989-01-18 JP JP902289A patent/JPH02189953A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5760429A (en) * | 1993-06-01 | 1998-06-02 | Matsushita Electric Industrial Co., Ltd. | Multi-layer wiring structure having varying-sized cutouts |
JPH07153842A (en) * | 1993-11-30 | 1995-06-16 | Nec Corp | Semiconductor device and its manufacture |
JP2005044927A (en) * | 2003-07-25 | 2005-02-17 | Kyocera Corp | Piezoelectric actuator and its manufacturing method, and liquid discharge apparatus |
JP2009037115A (en) * | 2007-08-03 | 2009-02-19 | Sony Corp | Semiconductor device, its manufacturing method, and display device |
US9053985B2 (en) | 2007-08-03 | 2015-06-09 | Sony Corporation | Semiconductor device having a contact pattern electrically connecting at least three conductive layers |
US8836135B2 (en) | 2011-03-01 | 2014-09-16 | Kabushiki Kaisha Toshiba | Semiconductor device with interconnection connecting to a via |
JP2012231148A (en) * | 2012-06-04 | 2012-11-22 | Sony Corp | Semiconductor device, method of manufacturing the same, and display apparatus |
JP2015076299A (en) * | 2013-10-10 | 2015-04-20 | セイコーエプソン株式会社 | Light-emitting device and electronic equipment |
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