JPH0218948A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0218948A
JPH0218948A JP16951788A JP16951788A JPH0218948A JP H0218948 A JPH0218948 A JP H0218948A JP 16951788 A JP16951788 A JP 16951788A JP 16951788 A JP16951788 A JP 16951788A JP H0218948 A JPH0218948 A JP H0218948A
Authority
JP
Japan
Prior art keywords
substrate
hole
forming
semiconductor substrate
polishing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16951788A
Other languages
Japanese (ja)
Inventor
Takaharu Nawata
名和田 隆治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16951788A priority Critical patent/JPH0218948A/en
Publication of JPH0218948A publication Critical patent/JPH0218948A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To enable control of a thin film so as to improve the performance of a device by opening an hole at one side of a semiconductor substrate for element formation, and measuring the depth of the hole in a filming process. CONSTITUTION:A hole is opened at one side of a semiconductor substrate 1 for element formation, and the semiconductor substrate 1 for element formation is bonded to a semiconductor substrate for supporting through an insulating layer. And the depth of the hole is measured in a filming process. Accordingly, when forming the substrate, the dispersion of film thickness by undulation, etc., is suppressed, and the film thickness and distribution of an element formation layer during etching polishing can be measured. Hereby, the control of the thickness of a thin film of the element formation layer is made possible, and performance improvement of a device becomes possible.

Description

【発明の詳細な説明】 〔概要〕 接着方法による5OI(Silicon on In5
ulator)基板の製造方法に関し。
[Detailed description of the invention] [Summary] 5OI (Silicon on In5) by adhesion method
(ulator) substrate manufacturing method.

素子形成層の膜厚と分布を測定できるようにし。Enables measurement of the thickness and distribution of the element formation layer.

薄い膜厚の制御を可能としてデバイスの性能向上をはか
ることを目的とし。
The purpose is to improve device performance by making it possible to control thin film thickness.

素子形成用半導体基板に少なくとも片面に開口した穴を
開け、絶縁層を介して該素子形成用半導体基板を支持用
半導体基板に接着する工程と、該素子形成用半導体基板
を薄膜化する工程と、該薄膜化する工程で前記の穴の深
さを測定する工程とを有する構成にする。
A step of making a hole opening on at least one side in a semiconductor substrate for forming an element, bonding the semiconductor substrate for forming an element to a supporting semiconductor substrate via an insulating layer, and a step of thinning the semiconductor substrate for forming an element, The structure includes a step of measuring the depth of the hole in the step of thinning the film.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に係り、特に接着法によ
るSo1基板の製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a So1 substrate using an adhesive method.

近年、シリコン(St)IC技術の進歩により、デバイ
スの高速、低消費電力化の要請が増している。
In recent years, advances in silicon (St) IC technology have increased the demand for higher speed and lower power consumption devices.

これに対応するには、単に微細化や電源電圧の最適化等
の従来技術の範囲内では限界があるので。
There are limits to how far conventional technology can respond to this, such as simply miniaturization and optimization of power supply voltage.

使用するバルク材料を変えるというアプローチが行われ
るようになった。
An approach has been to change the bulk materials used.

そのため、高度に蓄積されたSt IC技術をそのまま
用いて、 CMO3IC,3次元IC等のデバイス性能
、特に高速性を画期的に向上させるためにSOI基板が
使用される。
Therefore, SOI substrates are used to dramatically improve device performance, especially high speed, of devices such as CMO3 ICs and 3D ICs by using the highly accumulated St IC technology as is.

その経済的な形成方法の1つとして、絶縁層を介して2
枚のSi基板を接着して形成する方法がある。
One of the economical methods for forming it is to
There is a method of bonding two Si substrates together.

〔従来の技術〕[Conventional technology]

絶縁層を介して2枚のSi基板を接着してSO1基板を
形成する方法は次のとおりである。
The method for forming an SO1 substrate by bonding two Si substrates via an insulating layer is as follows.

まず、素子形成層となる薄いSi基板を酸化して表面に
二酸化シリコン(Si(h)Jlを形成し、これを支持
基板となる厚いSi基板に圧接した後に800℃程度の
熱処理を行って接着する。
First, a thin Si substrate, which will become the element formation layer, is oxidized to form silicon dioxide (Si(h)Jl) on the surface, which is then pressure-bonded to a thick Si substrate, which will become the supporting substrate, and then heat treated at about 800°C to bond it. do.

次いで、薄いSi基板をエツチング研磨して所期の厚さ
に仕上げ、素子形成層とする。
Next, the thin Si substrate is etched and polished to a desired thickness to form an element forming layer.

このエツチング研磨がSol基板の良否を決めるポイン
トとなる。
This etching polishing is the key to determining the quality of the Sol substrate.

従来法では2膜厚の均一性を得るためには、エツチング
研磨を高精度に行う必要があり、そのために途中でエツ
チング研磨を中断して何度も膜厚のモニタリングを行っ
ていた。
In the conventional method, in order to obtain uniformity in the thickness of the two films, it is necessary to perform etching polishing with high precision, and for this purpose, etching polishing has to be interrupted midway through and the film thickness has to be monitored many times.

〔発明が解決しようとする諜・題〕 上記のように従来法では、薄いSi基板をエツチング研
磨して素子形成層とする場合、エンチング研磨中にこの
素子形成層の厚さがどの程度になったかを認識すること
ができなかった。従ってデバイス特性に影響を与える膜
厚分布も測定できなかった。
[Problem to be solved by the invention] As mentioned above, in the conventional method, when etching and polishing a thin Si substrate to form an element formation layer, it is difficult to determine how thick the element formation layer becomes during etching polishing. I couldn't recognize Taka. Therefore, the film thickness distribution, which affects device characteristics, could not be measured.

特に、デバイスの集積度向上のためには、薄い素子形成
層を制御性よく作製することが必要である。
In particular, in order to improve the degree of device integration, it is necessary to fabricate thin element formation layers with good controllability.

高性能のCMOS ICを作製するには、素子形成層の
膜厚を1μm以下にする必要があるが、用いる薄い基板
は30μm以下にすることができないため。
In order to manufacture a high-performance CMOS IC, the thickness of the element formation layer must be 1 μm or less, but the thin substrate used cannot be made 30 μm or less.

かなりの量のエツチング研磨をする必要がある。A considerable amount of etching and polishing is required.

このため、エツチング研磨の際に、基板にうねりを生じ
1周辺が薄く中央が厚くなり、膜厚は不均一になるとい
う問題があった。
For this reason, during etching polishing, there was a problem in that the substrate was undulated and the film became thinner at one periphery and thicker at the center, resulting in non-uniform film thickness.

本発明は接着方法によりSo1基板を形成する際に、う
ねり等による膜厚のばらつきを抑え、エツチング研磨時
の素子形成層の膜厚と分布を測定できるようにし、薄い
膜厚の制御を可能としてデバイスの性能向上をはかるこ
とを目的とする。
The present invention suppresses variations in film thickness due to waviness and the like when forming a So1 substrate using an adhesion method, makes it possible to measure the film thickness and distribution of the element forming layer during etching polishing, and enables control of thin film thickness. The purpose is to improve device performance.

C課題を解決するための手段〕 上記課題の解決は、素子形成用半導体基板に少なくとも
片面に開口した穴を開け、絶縁層を介して該素子形成用
半導体基板を支持用半導体基板に接着する工程と、該素
子形成用半導体基板を薄膜化する工程と、該薄膜化する
工程で前記の穴の深さを測定する工程とを有する半導体
装置の製造方法により達成される。
Means for Solving Problem C] The solution to the above problem is a step of making a hole opening on at least one side in a semiconductor substrate for forming an element, and bonding the semiconductor substrate for forming an element to a supporting semiconductor substrate via an insulating layer. This is achieved by a method for manufacturing a semiconductor device comprising the steps of thinning the semiconductor substrate for forming an element, and measuring the depth of the hole in the thinning step.

〔作用〕[Effect]

本発明は素子形成用基板の接着面側、又は研磨面側に所
定の深さの穴を複数個開け、又は両面に開口する貫通孔
を複数個開け、その後この基板を酸化して厚い支持用基
板と接着し、その後素子形成用基板をエツチング研磨す
るとき、上記の穴または貫通孔の深さを測定することに
より膜厚を判定できるようにしたものである。
In the present invention, a plurality of holes of a predetermined depth are made on the adhesive side or the polished side of a substrate for forming an element, or a plurality of through holes are made on both sides, and then this substrate is oxidized to form a thick support. When bonding to a substrate and then etching and polishing the element forming substrate, the film thickness can be determined by measuring the depth of the hole or through hole.

接着面側に所定の深さの穴を開けた場合は、所定の膜厚
に達すると穴が露顕するので、この穴の深さを測定して
膜厚をモニタリングすることができる。この場合1貫通
孔でもエツチング研磨途中のモニタリングは可能である
が、所期厚さに近づいたときに穴が露顕するというアラ
ームは得られない。
If a hole is made to a predetermined depth on the adhesive side, the hole will be exposed when a predetermined film thickness is reached, and the film thickness can be monitored by measuring the depth of the hole. In this case, even with one through hole, monitoring during etching and polishing is possible, but an alarm indicating that the hole is exposed when the desired thickness is approached cannot be obtained.

研磨面側に深い穴(但し、所望の膜厚骨を余裕を持って
残した深さ)を多数開けると、エツチング研磨の途中で
この穴の深さを測定することにより均一に研磨が行われ
ているかどうかが判定できる。さらに2表面に多くの穴
があるので、穴の開けである深さまでは研磨速度は速く
、研磨の負荷が軽減され、うねりのような不均一な膜厚
分布を改善できる。研磨が進んで穴がなくなると研磨速
度が低下して膜厚制御が行いやすくなる。
By drilling a large number of deep holes (with enough depth to leave the desired thickness of bone) on the polishing surface side, uniform polishing can be achieved by measuring the depth of these holes during etching polishing. It can be determined whether the Furthermore, since there are many holes on the two surfaces, the polishing speed is high until the depth of the holes is reached, the polishing load is reduced, and uneven film thickness distribution such as waviness can be improved. As the polishing progresses and the holes disappear, the polishing speed decreases, making it easier to control the film thickness.

〔実施例〕〔Example〕

(1)素子形成用基板の接着面に穴を形成した例:第1
図(1)〜(3)は本発明の一実施例によるSOI構造
の形成方法を説明する断面図である。
(1) Example of forming holes on the adhesive surface of the element forming substrate: 1st
FIGS. (1) to (3) are cross-sectional views illustrating a method for forming an SOI structure according to an embodiment of the present invention.

第1図(1)において、素子形成用半導体基板として厚
さ30μm程度のSi基板1を用いる。
In FIG. 1(1), a Si substrate 1 with a thickness of about 30 μm is used as a semiconductor substrate for forming elements.

Si基板1に所定の深さ9例えば5μmの複数の穴を開
ける。
A plurality of holes with a predetermined depth 9, for example 5 μm, are made in the Si substrate 1.

穴の大きさは任意であるが、目視ができるように1 m
W@角程度にする。
The size of the hole is arbitrary, but it should be 1 m to allow visual inspection.
Make it about W@square.

Siの穴開けは、レジストマスクを用いたりアクティブ
イオンエツチング(RIE)により行う。
Holes in Si are formed using a resist mask or by active ion etching (RIE).

SiのRIEは、エツチングガスとして5iC14を用
い、これを10−” Torrに減圧して1周波数13
.56MHzの電力を400w印加して行う。
For Si RIE, 5iC14 is used as the etching gas, and the pressure is reduced to 10-” Torr and the frequency is 13.
.. This is performed by applying 56 MHz power of 400 W.

第1図(2)において、Si基板1を熱酸化してその表
面に厚さ1000人のSin、層IAを形成する。
In FIG. 1(2), a Si substrate 1 is thermally oxidized to form a 1000-layer Si layer IA on its surface.

支持用基板として1表面に厚さ5000人の5iOz層
2Aを形成した厚いSi基板2を用意する。
A thick Si substrate 2 having a 5000-thick 5iOz layer 2A formed on one surface is prepared as a supporting substrate.

Si基板1の穴を開けた面を支持基板の5i02層2^
上に載せ接着する。
Place the holed side of the Si substrate 1 on the support substrate 5i02 layer 2^
Place it on top and glue it.

接着は、 ioo v程度の直流電圧を印加し、窒素中
で450℃、60分程度の熱処理により行う。
Adhesion is performed by applying a direct current voltage of about IOOV and heat treatment at 450° C. for about 60 minutes in nitrogen.

第1図(3)において、Si基板1のエツチング研磨を
、穴が表面に現れるまで行う。
In FIG. 1(3), the Si substrate 1 is etched and polished until holes appear on the surface.

エツチング研磨は1例えばメカノケミカルと呼ばれてい
る方法を用いる。
For etching polishing, for example, a method called mechanochemical is used.

この方法は通常、ウェハ製作の際ポリッシングに使用さ
れている研磨法で、研磨終了時に研磨面が鏡面となる特
徴を持っている。
This method is a polishing method normally used for polishing during wafer manufacturing, and has the characteristic that the polished surface becomes a mirror surface upon completion of polishing.

以上で、接着Sol基板が、完成する。基板表面の穴の
深さを測定することにより、素子形成層1の膜厚及びそ
の分布を知ることができる。この測定値はエツチング途
中のモニタとして利用することができる。
With the above steps, the adhesive Sol substrate is completed. By measuring the depth of the holes on the substrate surface, the thickness of the element forming layer 1 and its distribution can be determined. This measured value can be used as a monitor during etching.

又、前記のように素子形成用基板に貫通孔を開けても、
エツチング研磨途中の膜厚のモニタリングができる。
Moreover, even if a through hole is made in the element forming substrate as described above,
Film thickness can be monitored during etching and polishing.

(2)素子形成用基板の研磨面に穴を形成した例:第2
図(11〜(3)は本発明の他の実施例によるSol構
造の形成方法を説明する断面図である。
(2) Example of forming holes on the polished surface of the element forming substrate: 2nd
Figures (11 to 3) are cross-sectional views illustrating a method for forming a Sol structure according to another embodiment of the present invention.

第2図(11において、素子形成用半導体基板として厚
さ30μm程度のSi基板1を用いる。
In FIG. 2 (11), a Si substrate 1 with a thickness of about 30 μm is used as a semiconductor substrate for forming an element.

Si基板1に所望の膜厚骨を余裕を持って残した深さに
深い穴を多数開ける。例えば深さ20μm程度の多数の
穴を開ける。
A large number of deep holes are drilled in the Si substrate 1 at a depth that leaves a desired thickness of bone with plenty of room. For example, a large number of holes with a depth of about 20 μm are made.

穴の大きさは任意であるが、この場合は初期の研磨負荷
を軽(するため第1図の例より大きくした方がよい。
The size of the hole is arbitrary, but in this case it is better to make it larger than the example shown in FIG. 1 in order to reduce the initial polishing load.

第2図(2)において、Si基vi1を熱酸化してその
表面に5i02層IAを形成する。
In FIG. 2(2), the Si group vi1 is thermally oxidized to form a 5i02 layer IA on its surface.

支持用基板として1表面にSiO□層録を形成した厚い
Si基板2を用意する。
A thick Si substrate 2 with a SiO□ layer formed on one surface is prepared as a supporting substrate.

Si基板1の穴を開けていない面を支持基板のSiO□
層2A上に載せ接着する。
Place the non-hole side of the Si substrate 1 on the support substrate SiO□
Place and adhere on layer 2A.

第2図(3)において、 Si基板1のエツチング研磨
を、穴が表面からなくなるまで行う。
In FIG. 2(3), etching and polishing of the Si substrate 1 is performed until holes disappear from the surface.

続いて、 Si基板1のエツチング研磨を継続して所定
の膜厚に仕上げて素子形成層とする。
Subsequently, etching and polishing of the Si substrate 1 is continued to finish the film to a predetermined thickness to form an element forming layer.

この例によると、従来接着基板で問題となっていたうね
り等による膜厚のばらつきを抑制し、薄い膜厚のSo1
基板を再現性よ(作製することができる。
According to this example, the variation in film thickness due to waviness, which has been a problem with conventional bonded substrates, can be suppressed, and the thin film thickness of So1
Substrates can be manufactured reproducibly.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、接着方法によりS
O1基板を形成する際に、うねり等による膜厚のばらつ
きを抑え、エツチング研磨時の素子形成層の膜厚と分布
を測定できる。
As explained above, according to the present invention, S
When forming an O1 substrate, variations in film thickness due to waviness or the like can be suppressed, and the film thickness and distribution of the element forming layer during etching and polishing can be measured.

従って、素子形成層の薄い膜厚の制御を可能としてデバ
イスの性能向上をはかることが可能となる。
Therefore, it becomes possible to control the thin film thickness of the element forming layer and improve the performance of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(1)〜(3)は本発明の一実施例によるSol
構造の形成方法を説明する断面図。 第2図(11〜(3)は本発明の他の実施例によるSO
I構造の形成方法を説明する断面図である。 図において。 1は素子形成用半導体基板で薄いSi基板。 LAはSiO□層。 2は支持用基板で厚いSt基板 2AはSiO2層 実施イテjの画面図 名 1 閃
Figures 1 (1) to (3) show Sol according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method of forming a structure. FIG. 2 (11-(3)) shows an SO according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method of forming an I structure. In fig. 1 is a semiconductor substrate for element formation, which is a thin Si substrate. LA is a SiO□ layer. 2 is a support substrate, and the thick St substrate 2A is the name of the screen diagram of the SiO2 layer implementation item J. 1 Flash

Claims (1)

【特許請求の範囲】 素子形成用半導体基板に少なくとも片面に開口した穴を
開け、絶縁層を介して該素子形成用半導体基板を支持用
半導体基板に接着する工程と、該素子形成用半導体基板
を薄膜化する工程と、前記薄膜化する工程で前記の穴の
深さを測定する工程 とを有することを特徴とする半導体装置の製造方法。
[Claims] A step of making a hole in at least one side of a semiconductor substrate for forming an element and bonding the semiconductor substrate for forming an element to a supporting semiconductor substrate via an insulating layer; A method for manufacturing a semiconductor device, comprising the steps of: thinning the film; and measuring the depth of the hole in the thinning step.
JP16951788A 1988-07-07 1988-07-07 Manufacture of semiconductor device Pending JPH0218948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16951788A JPH0218948A (en) 1988-07-07 1988-07-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16951788A JPH0218948A (en) 1988-07-07 1988-07-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0218948A true JPH0218948A (en) 1990-01-23

Family

ID=15887975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16951788A Pending JPH0218948A (en) 1988-07-07 1988-07-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0218948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204282A (en) * 1988-09-30 1993-04-20 Nippon Soken, Inc. Semiconductor circuit structure and method for making the same
JPH05160088A (en) * 1991-12-05 1993-06-25 Fujitsu Ltd Semiconductor substrate manufacturing method and device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204282A (en) * 1988-09-30 1993-04-20 Nippon Soken, Inc. Semiconductor circuit structure and method for making the same
JPH05160088A (en) * 1991-12-05 1993-06-25 Fujitsu Ltd Semiconductor substrate manufacturing method and device

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