JPH0218780B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a confidential communication circuit system for guaranteeing confidentiality of telephone calls in wireless communications.

(B) Prior art In normal wireless communication, when Party A and Party B are talking, if third party C receives a signal in the carrier frequency range used for communication between Party A and Party B, Party A and Party B There is a problem in that the confidentiality of calls is lost because the contents of calls between users can be intercepted.

An effective method for ensuring this privacy is to scramble the audio signal, send it out, and restore it on the receiving side. According to this method, the contents of the call will not be understood by a third party who does not have a restoration circuit in the receiving unit or who has a different key code because the received audio remains scrambled. Confidentiality can be maintained.

Conventionally, as one type of such a confidential communication circuit, a circuit element having a built-in balanced modulator (balanced modulation type) is generally commercially available. This method modulates the audio signal with a carrier wave of, for example, 5KHz.
This method extracts only the lower sideband wave by filtering and transmits it. In this case, the frequency of the audio signal is inverted with respect to the original signal. That is,
If the audio frequency is f, then f'=5-f (KHz). To restore it, just do the opposite, and the audio frequency will be inverted again, so it will return to its original state. In this case, even if the carrier frequency of the balanced modulator is slightly changed, the pitch of the reproduced sound is only slightly shifted from the original sound, and there is no problem with intelligibility. This means that in this method, only one key code for secret information can be obtained. Therefore, it has the disadvantage that the effect of maintaining confidentiality cannot be exhibited for those equipped with the same type of scrambling circuit.

(c) Purpose The purpose of the present invention is to provide a device in which a large number of key codes are provided in response to the requirement for guaranteeing confidentiality.

(d) Configuration The present invention basically includes a transmitter that scrambles an audio signal and a receiver that restores the scrambled audio signal.

More specifically, the present invention provides a variable delay circuit for sequentially sampling and storing signals in accordance with clock pulses and outputting the signals at the same time, a clock frequency control circuit for controlling the frequency of the clock pulses, and synchronization between the transmitting side and the receiving side. a synchronization signal circuit for counting the clock pulses included in the clock frequency control circuit and applied to the variable delay circuit; and a synchronization signal and synthesizing the output audio signal of the variable delay circuit on the transmitting side. It consists of a synthesis circuit.

(E) Embodiments Next, the apparatus of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating the principle of the apparatus of the present invention, in which A indicates the transmitting side and B indicates the receiving side. In addition, in Figure 1A, 1 is an audio input terminal, and 2 is an audio input terminal.
It is LPF. Reference numeral 3 denotes a delay circuit (memory circuit) having N delay stages, which samples and stores the audio according to the clock of the clock frequency control circuit (CP1) 4, and at the same time samples and stores the audio sampled and stored before the N sample time. This is a variable delay circuit that constantly stores N sampling values and sequentially outputs the values. After passing through the LPF 5, the output of the delay circuit is added to the output of the synchronization signal circuit 6 by a synthesis circuit 7, and then sent to a wired or wireless transmission system 9 via a transmission circuit 8 that performs modulation and amplification for transmission. be done.

On the receiving side in FIG. 1B, the received signal that has passed through the transmission system 9 is demodulated by a receiving circuit 10 including an amplification and demodulation circuit, and then passed through an LPF 11 to a clock frequency control circuit (CP2) 4'. At the same time, sampling and storing the received audio according to the clock;
The sampling values sampled and stored before the N sample time points are stored in the N sample storage circuit 3' which sequentially outputs them via the LPF 12. The synchronization between the transmitting side and the receiving side is achieved by separating the synchronizing signal sent from the transmitting side's synchronizing signal generation circuit 6 from the received signal by the synchronizing signal separating circuit of the receiving side's synchronizing signal circuit 6', and using this separated synchronizing signal to perform reception. This is done by completely synchronizing the clock on the transmitter side with that on the transmitter side.

Next, basic circuits on the transmitting side and receiving side of the present invention are shown in FIGS. 2 and 3, respectively. This basic configuration is substantially the same on both the transmitting and receiving sides. That is, a delay circuit 3 such as a BBD that inputs and outputs audio signals;
3', clock frequency control circuits 4, 4' for controlling the frequencies of clock pulses 13, 13', and synchronizing signal circuits 6, 6'. More specifically, the clock frequency control circuits 4, 4' are as follows:
master clock frequency oscillation circuits 15, 15';
variable frequency divider circuits 16, 16' that frequency divide the output;
Counter circuits 17, 17' that count clock pulses to delay circuits 3, 3' such as BBD, and logic circuits 18, 18 that control the frequency division number of the frequency divider circuits 16, 16' based on the output signals of the counters. ′. The synchronizing signal circuit 6 on the transmitting side in FIG. 2 is composed of a gate signal generating circuit 19, a synchronizing carrier generating circuit 20, and a gate control circuit 21, and the synchronizing signal circuit 4' on the receiving side in FIG. It consists of a synchronization separation circuit 21, a synchronization trigger generation circuit 22, and a preset value control circuit 23.

The basic principle of the present invention, for example, using a sine wave signal as an input signal, is to perform processing to periodically shift the frequency of the input sine wave signal up and down as shown in FIG. , which changes the spectral structure of the audio signal and reduces its intelligibility. More specifically, in FIG. 2, by changing the frequency division number of the variable frequency divider circuit 16 in the clock frequency control circuit 4, the clock frequency to the BBD 3 is changed, and the clock pulse when the audio signal is input to the BBD is changed. By making the frequency different from the clock frequency at the time of output after delay, the frequency of the output audio signal is changed with respect to the original one, and the audio is scrambled.

On the other hand, on the receiving side (Fig. 3), in a circuit having approximately the same configuration as the transmitting side (Fig. 2), the receiving side is
By changing the clock frequency to the BBD 14, the frequency of the received scrambled audio is converted again to return to the original frequency, thereby performing a restoring operation.

Next, the above-mentioned operation will be explained in more detail with reference to FIGS. 2 and 3.

First, the relationship between the operations of the variable delay circuit 3 and the counter circuit 17 will be explained. That is, in FIG. 2, the clock from the variable frequency divider circuit 16 is applied to the variable delay circuit 3, and at this time, the variable frequency divider circuit 16 selectively controls the frequency division number according to the count value of the counter 17. be done. The variable delay circuit 3 shifts the sampled signal to the next stage every time the clock is input. Since a shift operation is performed every time a clock is applied in this way, the delay time of the variable delay circuit 3 is controlled by the frequency of the applied clock (more specifically, the period of the reciprocal of this).

The audio signal is sent to the delay circuits 3, 3' with the clock 13,
13', and is further transferred to the next stage of the memory cell in the delay circuit like a bucket brigade, and is output after inputting clocks corresponding to the number of delay stages. Here, if the clock frequency when the audio signal is input is fa, and the clock frequency when the delayed signal is output is fb, then the audio signal at the time of output is converted to fb/fa times the frequency and sent out. Therefore, scrambling can be performed by changing the clock frequency.

Here, if the clock frequency when the audio signal is input to the transmitting side delay circuit 3 is _f1 , and the clock frequency when the signal is output after delay is _f2 , then the clock frequency when inputting to the receiving side delay circuit is f1. ₂ ,
Furthermore, if the clock frequency when outputting from the receiving side after delay is f ₃ , then in order to restore and output the original audio signal from the receiving side delay circuit, f ₂ /f ₁ ×f ₃ /f ₂ = 1, that is, , f ₃ = f ₁ by changing the clock frequency in synchronization with the sum of the delay times between the transmitting side and the receiving side. The clock frequency control circuit 4 in FIGS. 2 and 3,
4' is a circuit for controlling audio frequency conversion as described above.

Now, unless both the transmitter and receiver circuits operate with clocks of the same frequency and phase, the original signal will not be restored correctly. The present invention utilizes this relationship between frequency and phase to provide the ability to create many keys using the clock phase as a parameter on the transmitter and receiver sides. That is, the present invention utilizes the fact that the clock frequency is determined by the values of counters 17 and 17'. When the transmission side counter 17 has a certain value, a gate signal is generated from the gate signal generation circuit 19, and this signal is used to gate the carrier wave (for example, a sine wave with a frequency of 5 to 10 KHz) of the synchronization carrier generation circuit 20. Control circuit 2
1, and this gated signal is used as a synchronization signal. This synchronization signal is then applied to the synthesis circuit 7 to be superimposed on the scrambled audio signal and transmitted to the transmission system 9.

On the other hand, on the receiving side (Fig. 3), the synchronization separation circuit 2
1 separates the synchronization signal in the received signal, generates a trigger signal in the synchronization trigger generation circuit 22, applies the trigger signal to the preset value control circuit 23, and the preset value control circuit 23 generates the counter circuit 1.
7' is preset to the same value as the counter 17 on the transmitting side.

In the present invention, in order to create a key, the value of the transmitting side counter 17 when sending out the output gate signal of the gate signal generation circuit 11 and the value for presetting the receiving side counter 17' are set as parameters in pairs, and the keys are different. , the original signal is not restored correctly and the content is configured in such a way that the content cannot be understood.

Next, specific embodiments of the present invention are shown in FIGS. 5 and 6.
This will be explained with figures.

First, in FIG. 5, the clock frequency on the transmitting side is determined according to the value of the counter 17. The period of the highest output Q1 of the counter 17 is equal to the sum of the delay times of the delay circuits 3 and 3' on the transmitting side and the receiving side,
That is, it is the time for counting clocks by the sum of the number of delay stages on the transmitting and receiving sides, and the clock frequency changes in this period. The output gate signal of the gate signal generation circuit 19 is obtained from the output of the NOR circuit 24 in the figure. In the example shown, the key setting terminals T1, T2,
For example, T3 and T4 are (1, 0, 1,
0), the value of the counter 17 is Q ₁ = 1, Q ₂ =
0, Q ₃ =1, and Q ₄ =0, the output G of the NOR circuit 24 is "1", and in other cases it is "0". Using this gate signal, synchronization carrier wave (5~
A signal obtained by gate-controlling a 10 KHz sine wave or rectangular wave by a gate control circuit 21 is used as a synchronization signal.

On the receiving side, on the other hand, this synchronizing signal is extracted by a synchronizing separation circuit 21 consisting of a filter, the rising timing of this signal is detected, a trigger pulse is generated, and a counter 17' on the receiving side is preset. If the circuit shown in FIG. 6 is configured, the preset value at this time will be the same value as that on the transmitting side.
In Fig. 6, T ₁ , T ₂ , T ₃ , T ₄ are key set terminals, L ₁ , L ₂ , L ₃ ... are load input terminals for counter preset, Q ₁ , Q ₂ , Q ₃ ... are counter outputs. It is.

Next, an example of a circuit for generating a trigger for presetting the counter circuit 17' on the receiving side will be described. 7th
In the figure, a is a gate-controlled synchronization signal, and when this signal is passed through a comparator circuit, b
The pulse train shown in the figure is obtained. In figure a, V is the carrier wave signal for the synchronization signal with a frequency of 5 to 10 KHz, and V ₁
is the reference voltage of the comparator. Furthermore, if the pulse train shown in figure b is passed through a monostable circuit, etc., a single pulse consisting of a series of pulse trains as shown in figure c will be obtained.
A trigger pulse as shown in the figure is generated and used as a preset trigger for the counter circuit 17'.

At this time, the trigger generation timing in figure d is the rise time of the first pulse of the pulse train in figure b, which is the comparator output waveform, but if the carrier wave is about 5 to 10 KHz, this timing is the same as the gate signal on the transmitting side. The rise of the original gate control signal, which is the output of the generation circuit 19, is slightly delayed (Δt). This delay can be sufficiently compensated for by further presetting the lower values (Q ₅ , Q ₆ , Q _{7 ,} etc.) of the receiving side counter 17'.

In the above description of the embodiment, for convenience, an example was shown in which 2 ⁴ =16 keys were created. Experiments have shown that if the clock operating phases on the transmitting and receiving sides differ by more than 10 to 15 degrees, the content of the reproduced audio signal becomes almost inaudible. Therefore, in this case, as many as 20 to 40 key codes can be created.
In this way, by creating keys using the phase of the clock frequencies on the transmitting side and the receiving side as parameters, it is possible to have a large number of keys. Furthermore, keys can be created by changing other parameters such as the master clock frequency on the transmitting and receiving sides, so by combining these, hundreds of keys can be created.

Furthermore, in the above, as a variable delay circuit
Although the explanation has been given using BBD as an example, it goes without saying that a similar configuration can be made using CCD or shift registers. Furthermore, when using a digital memory circuit such as a RAM, the circuit can be appropriately rearranged by combining it with a D/A circuit or an A/D circuit.

(F) Effect As described above, the present invention provides a scrambling device that can have a large number of keys by creating keys using the preset values of the counter circuits that control the clock frequencies on the transmitting and receiving sides as parameters. Based on the method, if wired or wireless devices equipped with circuits are used, the contents of the call will not be intercepted even if received by a third party, and a great practical effect can be obtained in conducting confidential communication.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the principle of the present invention.
FIG. 2 is a block diagram of the circuit on the transmitting side of the confidential communication device of the present invention, FIG. 3 is a block diagram of the circuit on the receiving side of the same device, FIG. 4 is a characteristic diagram of the scramble signal waveform processed by the device of the present invention, and FIG. The figure shows a specific embodiment of the gate signal generation circuit used in the device of the present invention.
The figure shows a specific example of a preset value control circuit used in the apparatus of the present invention, and FIG. 7 shows signal waveforms used for synchronization. Explanation of main drawing numbers, 1...input terminal, 3, 3'...
...variable delay circuit, 4, 4'... clock frequency control circuit, 6, 6'... synchronization signal circuit, 7... synthesis circuit, 9... transmission system, 13... clock pulse,
14... Output terminal, 15, 15'... Master clock frequency oscillation circuit, 16, 16'... Variable frequency dividing circuit, 17, 17'... Counter circuit, 18,
18'...Logic circuit, 19...Gate signal generation circuit, 20...Synchronization carrier wave generation circuit, 21...Synchronization separation circuit, 22...Synchronization trigger generation circuit, 2
3...Preset value control circuit.

Claims (1)

[Claims] 1 (a) A delay operation is performed by sequentially sampling, storing and outputting a signal according to a clock pulse, and the delay time of the delay operation is dependent on the frequency of the applied clock pulse. (b) a clock frequency control circuit for controlling the frequency of the clock pulse; and (c) a synchronization signal circuit for synchronizing the transmitting side and the receiving side. The clock frequency control circuit includes a counter circuit for counting the clock pulses applied to the variable delay circuit, and controls the frequency of the clock pulses in relation to the output of the counter circuit. , applying the clock pulse to the variable delay circuit and generating a synchronizing signal in the synchronizing signal circuit in response to the output of the counter circuit when the counter circuit on the transmitting side counts a predetermined clock pulse; The output audio signal of the variable delay circuit and the synchronization signal are synthesized by a synthesis circuit, and then transmitted to a transmission system, and the synchronization signal is separated on the receiving side,
The counter circuit on the receiving side is preset by the separated synchronizing signal, and a key code is created using the value of the counter circuit at the time of sending the synchronizing signal on the transmitting side and the value for presetting the counter circuit on the receiving side as parameters. Confidential communication device. 2. The confidential communication device according to claim 1, wherein the upper part of the counter circuit is used for setting a key code, and the lower part is used for compensating for a synchronization delay on the receiving side.