JPS61123335A - Signal synchronous circuit of privacy call communication equipment - Google Patents

Abstract

PURPOSE:To improve the performance of privacy call of a privacy call communication equipment by providing two waves of synchronizing signals at a low frequency side from a voice frequency band to synchronize transmission and reception without spreading the transmission signal band. CONSTITUTION:A clock frequency fed to a variable delay circuits 3, 15 of the transmission side (a) and the reception side (b) of a privacy call communication system is controlled by clock frequency control circuits 5, 20 including counters 6, 21 counting clocks. In order to synchronize the transmission and reception sides, a voice signal is added to a synchronizing signal Sp from a synchronizing signal generating circuit 9 of the transmission side (a) at an adder circuit 10 and the result is transmitted to the reception side (b). A gate signal is extracted from a gate signal generating circuit 8 in relation to the value of the counter 6 included in the circuit 5 and two waves at a low frequency side from the voice frequency band are outputted. After the synchronizing signal superimposed on the voice signal is extracted by the filter processing at the reception side (b), the gate signal is demodulated. Then the transmission and reception sides are synchronized without spreading the transmission signal band.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a confidential communication circuit for maintaining the confidentiality of telephone calls in wired or wireless communications. This invention relates to a signal synchronization circuit for a communication system.

(ci) Prior Art In wired or wireless communication, there is an inherent problem that if a suitable receiving device is used, the contents of the communication can be intercepted by anyone, thereby impairing the privacy of the call.

A method to solve this problem is to scramble the audio signal and send it out so that even if it is received by a third party, the contents cannot be known.The circuit that plays back this processed signal (descrambler) A so-called scrambling technique has been used in the past, which allows only a recipient with a processing circuit (processing circuit) to restore the audio signal. Conventional confidential communication methods are described, for example, in the Journal of the Institute of Electronics and Communication Engineers (August 1982), “Secret Communication Technology J (P832-P834)” and “About the Secret Communication Method”, IEICE Branch 0880-149 (November 1980). , each Uekaba style is introduced.

Since audio information is composed of a spectrum and its temporal changes, the intelligibility of the audio can be reduced by scrambling processing that changes the spectral structure. From this point of view, scrambling methods that have been put to practical use include the spectrum inversion method and the frequency division permutation method.

For example, Special Publication No. 58-8621 (HO4K 1104
) "Secret conversation system with frequency correction function" and JP-A-58-1
48541 (HO4 to 1104) r secret speech circuit" relates to the spectrum inversion secret speech method, and is also
(ELO4JL1106) r Confidential communication device" relates to a method of performing signal processing after dividing into a predetermined spectrum, and the IEICE branch axis C8-80-149 once converts an audio signal into a digital signal and then converts it into a frequency axis by FFT processing. This paper proposes methods for improving each method of performing conversion processing. However, the spectral inversion method does not have a sufficient number of combinations (number of keys) for the secret story, and the latter three methods have a large number of keys, but they use many filters and There were problems such as a processing circuit was required and the circuit scale was large, the cost was high, and the amount of power consumed was large.

From these viewpoints, the applicant previously proposed a scrambling method with a large number of keys, excellent secret communication performance, and a simple circuit configuration. Patent Application No. 184916 (filed on September 20, 1984), "Clock Circuit for Confidential Communication System" (filed on October 20, 1988)
19702 "Secret Communication Device" (filed on October 20, 1988). This uses a variable delay circuit to periodically change the frequency of the clock that controls the delay time, repeatedly compresses and expands the time axis, scrambles the audio signal, and sends it out. This method performs descrambling processing.

In this method, in order to correctly restore the original audio on the receiving side, the operation of the clock applied to the variable delay circuit must be synchronized on the sending and receiving sides so that the signal processing is the opposite of that on the sending side. Therefore, it is necessary to send a synchronization signal from one transmitting/receiving device to the other. Therefore, for example, amplitude modulation of a single-frequency sine wave is performed at the period of time change of the clock frequency, and FS is performed by changing the frequency.
A method is used in which the signal is subjected to jL modulation and is superimposed on a transmission signal as a synchronization signal and sent out.

However, the above-mentioned conventional synchronization method has the disadvantage that the spectrum spread 9 during modulation falls within the audio band and degrades the 8N ratio of the audio signal as noise. Furthermore, it is necessary to provide the frequency of the single sine wave on the high frequency side of the audio band, which poses a problem of widening the transmission signal band.

(c) Problems to be Solved by the Invention The present invention provides a signal synchronization circuit that can solve the drawbacks of the synchronization circuit, such as deterioration of the S/N ratio, in conventional confidential communication devices.

B) Means and operation for solving the problems First, the basic circuit configuration of the present invention will be explained with reference to FIG. 1. In the figure, (1) is an audio signal input terminal, (2) is an LPF, (3) is a variable delay circuit, (4) is an LPF, and (5) is an LPF.
) is a clock frequency control circuit, which consists of a clock frequency control counter circuit (6) and a logic circuit (7). (8+ is a gate signal generation circuit, (9) is a clockwise signal generation circuit, αOj is an addition circuit, (Company) is a transmission circuit, or is a wired or wireless transmission system, (131 is a reception circuit, and circle is an LPF. ,
■ is a variable delay circuit, C6 is an LPF, 0η is an audio output terminal, α is a gate signal demodulation circuit, (1!ll is a trigger generation circuit, ■ is a clock frequency control circuit, and a control counter circuit (2) It consists of a logic circuit ■.

Now, a variable delay circuit whose delay time can be controlled by a clock (3
) A decoy is provided on each of the transmitting and receiving sides, and the clock frequency of the delay circuit is changed over time at a cycle equal to the sum of the delay times of the transmitting and receiving side delay circuits, and the transmitting side performs scrambling processing, and the receiving side performs descrambling processing. .

In this circuit, the variable delay circuit (3) is BB.
D (Buokat Brigade Device)
CC1) (Charge Coupled De
An analog shift register such as VICE) and a memory element such as RAM are used. In addition, the frequency of the clock applied to the variable delay circuit is determined by the clock frequency control circuit (5) including the counter circuit (6) (21i) that counts the clock.
It is configured to be controlled by the mother. In order to synchronize clock operations on the transmitting and receiving sides, a synchronizing signal (8p) generated by a synchronizing signal generating circuit (9) on the transmitting side (a) is superimposed on the audio signal signal by an adder αα and sent out.

The following signal is used as this synchronization signal. That is, as shown in FIG. 2(a), a gate signal is extracted from the gate signal generation circuit (8) in relation to the value of the transmission side control counter circuit (6) included in the transmission side clock frequency control circuit (5). The synchronization signal generation circuit (
9), for example, a tone burst wave obtained by gate-controlling a sine wave as shown in Figure 2 (b), or a tone burst wave ((+)
Phase modulation as shown [Figure (8) shows two-phase, 180 degree modulation]
This is used as a synchronizing signal or a signal for F8.

On the receiving side (b), after extracting the synchronization signal superimposed on the audio signal through filter processing by a filter circuit,
The gate signal corresponding to FIG. 2(a) is demodulated (see FIG. 2(d)).

Now, the clock frequency is determined by the value of the counter (61 (211), so in order to synchronize the clock operation, it is sufficient to set the counter value on the receiving side to the same value as on the transmitting side, and the transmitting side (a) The counter circuit (6) when sending out the gate signal (Gt) from the gate signal generation circuit (8)
) on the receiving side (b) so that the trigger signal obtained from the output gate signal (Gm) of the gate signal demodulation circuit (2) (Fig. 2 (d)) is the same as the value of In other words, the pulse waveform has a rising edge or a falling edge every period equal to the sum of the delay times of the transmitting side delay circuit and the receiving side delay circuit. (rectangular wave) as a synchronization signal, and is configured to perform a preset operation by a trigger obtained from a demodulated synchronization signal on the reception side, which is the same as the counter value at the rise (or fall) of the synchronization signal on the transmission side. has been done.

In the present invention, as a synchronization signal, two waves, a low frequency signal with a constant frequency and a signal obtained by multiplying this signal, are provided on the lower side of the audio signal band, and these are superimposed on the audio signal and transmitted, and these are transmitted on the receiving side. It is separated and used as a synchronization signal.

(C) Embodiment FIG. 6 shows an embodiment of the transmitting side of the synchronous circuit of the present invention. In the figure, (2) is an LPF that prevents aliasing noise due to sampling, and (3) is a variable delay circuit with a storage capacity of N, which samples the input signal according to the clock and sequentially transfers and outputs it. Here, BBD is used. The clock that controls the BBD is the output (
CP) is used. It is controlled by a color counter (2) that counts the variable frequency dividing circuit CP and a matrix circuit (4) that receives the output of the counter as an input, and changes the frequency (fl) of the output CP in a stepwise manner as shown in Fig. 4. .

Every time the counter counts N 3Ps, it switches between raising and lowering fl and outputs a Q signal with a period equal to the changing period of OF as shown in the figure, which is used as a synchronization signal.The period (T) is T = Matashitsuki.Here, R is the storage capacity of the variable delay circuit, i is the minimum value of the frequency division number of the variable frequency divider circuit, m is the number of frequency division stages, and fO is the master clock frequency.For example, fo=250xu
z, t=13, m=8, N=512, T=67
．． 6ms, f=1/T=i4°8Hz. Further, the Q signal is multiplied by M using PLL@ and used as a QM times signal synchronization signal.

QM times signal frequency (fQM) is 100H below the audio frequency
Choose z degree. In the above example, the frequency fQ of the Q signal is 14
, 8H2, so it is multiplied by 8 and becomes fQM=14.8x8=118.4 (Hz). The center frequencies of the Q signal and QM multiplied signal are applied to the head of the arithmetic circuit through the level adjuster @(9) which continues these and adjusts each output level, respectively. Ru.

On the other hand, the output of the variable delay circuit (3) passes through an LPFQ31 that removes high frequency components contained in the output of the circuit, and is added and superimposed with the output of the level adjuster @(2) in the adder circuit α4. The summed output is then subjected to amplification modulation processing in a transmitting circuit, and is sent out from a transmitting antenna.

Next, the receiving side of the embodiment of the present invention will be explained with reference to FIG. The two low-frequency synchronization signals of the frequencies (fQ) and (fQM) are generated from the baseband signal received by the receiving antenna (2) and subjected to reception amplification and detection demodulation in the receiving circuit (2) following the receiving antenna. ) (f QM) OB
P F ((3134) and Hiko n+c (by PLL (2)-) are extracted. The output of PLL (to) (the demodulated QM multiplied signal is clocked into the counter (to)). The outputs (demodulated Q signals) of the PLL (3 and 9) are input to the single pulse generation circuit (support), and the counter (to) is reset by the single pulse generated at the falling timing of the Q signal. counts the fall 9 of the demodulated QM multiplied signal, M/2 (however, M is an even number, and in this example, M=
8) Detect the next rising edge after counting by the gate matrix circuit.

A single pulse is generated by the single pulse generating circuit at the timing of the rising edge.

On the other hand, the received signal, which is the output of the receiving circuit, is passed through an RPF (4Q1
, an LPF (141) for preventing aliasing noise, an analog shift register (to) to the storage capacity, and an LPF (lil) for removing high frequency components.The clock pulse that controls the analog shift register @ is transmitted. As well as the side
The master clock circuit (6), the variable frequency divider circuit (421), the counter (■, gate matrix) are controlled by the master clock circuit (6), the variable frequency divider circuit (421), and the gate matrix (Incorporated). ] The counter (resets to 0) by the output pulse.

According to such a configuration, the Q signals are supposed to be synchronized between transmitting and receiving, but it is difficult to achieve this with high precision because noise components are superimposed. Therefore, fine adjustment is performed on the QM multiplied signal. That is, it is considered that the QM multiplied signal rising point closest to the rising edge of the Q signal has more accurate phase information. Figure 6 (
As in a), when the demodulated QM multiplied signal lags behind the demodulated Q signal, after the counter (G) is reset at the falling edge of the Q signal, the falling edge of the QM multiplied signal, which is the clock input, is
2=Rise 9 of the next clock after counting 4 times (18 in the figure)
point) is detected by the gate matrix circuit (support), and the corresponding K
At point a, "H" is output and input to the single pulse generator circuit. As shown in Fig. 5(b), for the demodulated Q signal, the demodulated QM
Similarly, when the double signal is leading, after the counter is reset, the next clock fall fi (point JLb) after counting the falling edge of the QM double signal four times is detected. That is, in either case, the QM times signal rising edge closest to the rising edge of the Q signal can be detected. However, the condition is that the relative phase difference between the Q signal of frequency (fQ) and the QM multiplied signal of frequency (fqM) is ±1/2 f 9M or less.

FIG. 7 shows an example of the gate mask IJ circuit, and FIG. 7 shows a time chart for explaining its operation. With the configuration shown in FIG. 6, pulse 4 can be detected as the Qm output. When gate Q/D and QM with an AND gate (383,), in order to prevent noise from occurring due to the influence of pulse O,
A delay circuit (382) is inserted. The delay circuit (38
The delay time in 2) must be less than 1/2 of the QM times the signal period.

Incidentally, in this embodiment, the case where M is an even number has been described, but M
If is an odd number, a counter can be used to count the rising edges of the demodulated QM multiplied signal.

(f) Effects of the Invention As described above, the circuit of the present invention provides synchronization signals with two waves lower than the audio frequency band, so that synchronization between transmission and reception can be achieved without widening the transmission signal band. Further, the variable delay circuit type confidential communication device using the synchronization method according to the present invention allows communication with excellent confidential communication performance.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the confidential communication system that is the basis of the present invention.
Fig. 2 is an example of the waveform of a synchronization signal used in the above system, Fig. 3 is an embodiment of the transmitting side circuit of the present invention, Fig. 4 is a clock frequency transition diagram, and Fig. 5 is an embodiment of the receiving side of the present invention. 6 is a time chart of a synchronizing signal, FIG. 7 is an example of a gate matrix circuit, and FIG. 8 is a time chart of gate matrix circuit signals. (3) Tomoe...variable delay circuit, (5) ■...
...Clock frequency control circuit, (6)@...Clock frequency braking counter circuit, (7)...
Logic circuit, (81... gate signal generation circuit, (
9+...Synchronization signal generation @path, αα...
Addition circuit,... Gate signal demodulation circuit, yesterday...
...Trigger pulse generation circuit. ← lJJ's] Ku. u'+ro
Deception O Kano a 10 lo a OG O=

Claims (3)

[Claims] (1) A variable delay circuit for signals that sequentially samples signals according to clock pulses, stores them, and outputs them; a clock frequency control circuit that controls the frequency of the clock pulses; and a clock frequency control circuit for synchronizing the clock operations on the transmitting and receiving sides. A signal synchronization circuit is provided on the transmitting side and the receiving side of the communication system,
On the transmitting side, by changing the clock frequency when inputting the signal to the variable delay circuit and the clock frequency when outputting it, the frequency of the transmitted signal is changed and transmitted, and the signal is received on the receiving side and input to the variable delay circuit. The received signal frequency is adjusted by synchronizing clock pulses on both the transmitting and receiving sides so that the clock frequency when the signal is output from the delay circuit is equal to the clock frequency when the signal is input to the transmitting side variable delay circuit. A secret communication device for reproducing,
As a synchronization means on the transmitting side, first and second sine wave signals synchronized with the transmitting side clock pulse, whose frequencies are in an integer ratio, and whose frequency band is lower than the audio frequency band and are phase-synchronized, are superimposed on the transmitted audio signal, and are sent out and received. The side separates these first and second sine wave signals from the received signal, generates first and second synchronization signals corresponding to the first and second sine wave signals, and generates first and second synchronization signals. A signal synchronization circuit for a confidential communication device, characterized in that the clock control circuit is initialized in relation to the above. (2) A synchronization pulse is generated near the time of polarity reversal of the first synchronization signal on the low frequency side and when the polarity of the corresponding second synchronization signal is reversed to initialize the receiving side clock control circuit. A signal synchronization circuit for a confidential communication device according to claim 1. (3) The confidential communication device according to claim 2, wherein the first and second synchronization signals are rectangular waves obtained by passing the first and second sine wave signals through a PLL circuit, respectively. Signal synchronization circuit.