JPH0149217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a confidential communication circuit system for guaranteeing confidentiality of telephone calls in wireless communications.

(B) Prior art In normal wireless communication, when Party A and Party B are talking, if third party C receives a signal in the carrier frequency range used for communication between Party A and Party B, Party A and Party B There is a problem in that the confidentiality of the calls is lost because the contents of the calls can be intercepted.

An effective method for ensuring this privacy is to scramble the audio signal, send it out, and restore it on the receiving side. According to this method, the contents of the call will not be understood by a third party who does not have a restoration circuit in the receiving unit or who has a different key code because the received audio remains scrambled. Confidentiality can be maintained.

As one type of secret circuit, a circuit element with a built-in balanced modulator (balanced modulation type) is generally commercially available. This method uses the audio signal as
For example, after modulating with a 5KHz carrier wave, only the lower sideband is extracted by filter processing and sent out. In this case, the frequency of the audio signal is inverted with respect to the original signal. That is, the audio frequency is f
Then, f'=5-f (KHz). To restore, you can perform the same operation, and the audio frequency will be inverted again, so it will return to its original state. In this case, even if the carrier frequency of the balanced modulator is slightly changed, the pitch of the reproduced sound is only slightly shifted from the original sound, and there is no problem with intelligibility. This means that in this method, only one key code for secret information can be obtained. Therefore, it has the disadvantage that the effect of maintaining confidentiality cannot be exhibited for those equipped with the same type of scrambling circuit.

(C) Purpose The purpose of the present invention is to provide a system in which a large number of key codes are provided in response to the requirement for guaranteeing confidentiality.

(d) Configuration The present invention basically includes a transmitter that scrambles an audio signal and a receiver that restores the scrambled audio signal.

Next, the apparatus of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating the principle of the apparatus of the present invention, in which A indicates the transmitting side and B indicates the receiving side. First, in Figure 1A, 1 is an audio input terminal, 2 is an audio input terminal, and 2 is an audio input terminal.
It is LPF. 3 is a delay circuit (memory circuit) having N delay stages, and a clock circuit (CP1).
This is a variable delay circuit that samples and stores audio in accordance with the clock of No. 4, and at the same time constantly stores N sampling values, which sequentially outputs sampling values sampled and stored before N sample times. After passing through the LPF 5, the output of the delay circuit is added to the output of the synchronizing signal circuit 6 by an adder circuit 7, and then sent to a wired or wireless transmission system 9 via a transmitting circuit 8 that performs modulation and amplification for transmission. Ru.

On the receiving side in FIG. 1B, the received signal that has passed through the transmission system 9 is demodulated by a receiving circuit 10 including an amplification and demodulation circuit, and then passed through an LPF 11 and is clocked by a clock circuit (CP2) 12. At the same time, the received voice is sampled and stored in an N sample storage circuit 14 which sequentially outputs sampling values sampled and stored before the N sample time points via the LPF 13. Synchronization between the transmitting side and the receiving side is performed by a synchronization separation circuit 15 which separates the synchronizing signal sent from the synchronizing signal generating circuit 6 on the transmitting side from the received signal, thereby completely synchronizing the clock on the receiving side with that on the transmitting side. It will be done.

Next, the basic circuit configuration of the present invention is shown in FIG. This basic configuration is the same on both the transmitting and receiving sides. That is, it is composed of a delay circuit 3 such as a BBD that inputs and outputs audio signals, and a clock frequency control circuit 4 that controls the frequency of its clock pulse 21. Furthermore, the clock frequency control circuit includes a master clock frequency oscillation circuit 17 and a clock frequency control circuit 4 that controls the frequency of its clock pulse 21. A frequency divider circuit 18 that divides the output, a counter circuit 19 that counts clock pulses to the delay circuit 3 such as BBD, and a logic circuit 20 that controls the frequency division number of the frequency divider circuit based on the output signal of the counter. configured.

The basic operation of the circuit shown in Figure 2 is to change the clock frequency to the BBD 3 by changing the frequency division number, and change the frequency of the clock pulse 21 when the audio signal is input to the BBD and the clock frequency when outputting after the delay. By changing the frequency of the output audio signal with respect to the original one,
This is to scramble the audio.

On the other hand, on the receiving side B, in a circuit having the same configuration as the sending side A, the received scramble is The structure is such that the restoration operation is performed by converting the audio frequency again so that it returns to the original frequency.

Furthermore, the present invention is configured so that a large number of key codes can be obtained by setting the logic circuit 20 that controls the frequency and frequency division number of the master clock 17.

(E) Embodiment An embodiment of the present invention will be described based on FIGS. 2 and 3. FIG. 3 shows an example of the configuration of the control counter 19, the frequency dividing circuit 18, and the logic circuit 20 connecting them. For convenience of explanation, a case will be described in which the number of delay stages (N) of the BBDs 3 and 14 used on the transmitting side and the receiving side are both 1024 stages. In this case, BBD3,
The signal component input to 14 is delayed by a time equivalent to N/2 (for example, 512) clock pulses 21, and then
Output from BBD3 and BBD14. The control counter 19 used in the example of FIG. 3 is a 1024-base counter with the same number as the number of delay stages (N), and the highest counter output (Q) is 1 and 0 for every 512 clock pulses to the BBD. Repeat the switch to value.

Now, as shown in FIG. 3, the frequency dividing circuit 18 also basically consists of a counter, and performs AND logic 23 on the output of the OR circuit 22 between each output and the logic circuit output corresponding to each stage. This output resets the counter 18. Depending on the type of counter, it may also be necessary to reset it after inserting an inverter. However, frequency division counter 1
The output of the highest stage of 8 is directly input to the AND circuit 23 without passing through the OR circuit 22. In this case, the clock frequency can be changed by about one octave by changing the frequency division. For example, in the example shown in FIG. 3, the frequency division number is approximately one octave from 32 to 63, and 32 frequency division numbers are obtained.

FIG. 4 shows a logic diagram when the logic circuit of FIG. 3 is used. In FIG. 4, the outputs (Q, a, b, ......e) of the control counter 19 and the frequency division counter 1
The inputs of the OR circuit 22 at 8 (A, B, ......
E) and the frequency division number. In addition, in the frequency dividing circuit 18,
When A=B=……=E=1, the division number is 32, A
When =B=...=E=0, the frequency division number is 63.

Figure 5 shows changes in clock frequency. Although there are 32 frequency changes, they are drawn continuously to simplify the diagram. As shown in FIG. 5, the clock frequency repeats rising and falling every 512 clocks.

Since the input signal to the BBD 3 is delayed by 512 clocks and output, the clock frequency is different between input and output, so the output audio frequency is different from the original one. If the clock frequency at input is (f ₁ ) and the clock frequency at output is (f ₂ ), the audio frequency is converted to f ₂ /f ₁ times. FIG. 6 shows changes in the audio frequency conversion ratio. The frequency changes periodically between about 1/2 and 2 times.

Figure 7 shows an example of a scrambled signal.
The case where a positive arc wave is input to BBD3 is shown.

Next, the operation during restoration (receiving system) will be explained. The restoration circuit basically operates in the same way as the transmission side scramble circuit. Note that the change in clock frequency must be synchronized with the transmitting side. The audio signal input to the BBD3 on the transmitting side is delayed by 1024 clocks and output from the receiving section BBD14.
As shown in Figures 5 and 6, the period of change in clock frequency is 1024 clocks, so
The audio signal input to the BBD 3 (transmitting side) with a clock of frequency (f ₁ ) is outputted from the receiving side BBD 14 with a clock of the same frequency (f ₁ ). Therefore, when looking at the transmitting and receiving system as a whole, the frequency of the audio signal output from the receiving side is restored to the original frequency. To explain this operation in more detail, for example, (a) the audio signal input to the BBD circuit on the transmitting side using the clock (f ₁ ) is output using the clock (f ₂ ), and the frequency of the audio signal is multiplied by f ₂ /f ₁ . is converted to

(b) On the receiving side, the received signal is input to the BBD14 at the same clock frequency (f ₂ ) as the output on the transmitting side,
Since the BBD outputs the clock (f ₁ ),
The frequency of the received signal is converted to f ₁ /f ₂ times.

Therefore, for the entire transmission and reception system, f ₂ /f ₁ ×
f ₁ /f ₂ =1, and the original audio signal is restored.

Now, in the above explanation, it is assumed that the changes in the clock frequency on the transmitting side and the receiving side are synchronized. The operation when the output frequency is different between the transmitting side and the receiving side will be explained. In this case, the periods of change in clock frequency are both 1024 clocks, but since the clock frequencies are different, the period times are different. For this reason, an audio signal whose frequency has been converted to f ₂ /f ₁ times on the transmitting side, for example, will not be converted to the reciprocal f ₁ /f ₂ on the receiving side due to the difference in period time, so it will be the original signal. The audio remains scrambled without being restored to audio. This shows that the difference in the frequency of master clock oscillator 17 can be used as a key code for secret communication.

As a result of experiments conducted using the method of the present invention regarding the correlation between the degree of scrambling effect and the degree of frequency difference, it has been confirmed that a practically sufficient scrambling effect can be obtained by changing the frequency by about 1.05 times. According to this result, approximately 15 key chords can be obtained per octave. Also BBD
The clock frequency range for commercially available clocks is about 10 to 100 KHz, so it can actually cover 2.5 octaves.

Furthermore, the combinations of logic circuits 20 that control the frequency dividing circuit 18 have considerable variety, and from this point of view as well, the number of key codes can be expanded. Therefore, it can be seen that in the method of the present invention, the number of key codes for secret messages can be a practically sufficient number. FIG. 8 shows a logic configuration that is simpler than the embodiment shown in FIG. The change in clock frequency in this case is
As shown in the figure, there is a switching change of two frequencies.
FIG. 10 shows the change characteristics of audio frequency.

Now, when restoring, it is necessary that the changes in clock frequency be synchronized between the transmitting side and the receiving side, but if this synchronization is slightly off (however, the period is the same and the switching time is slightly different). Let us compare the operation during restoration of the case) for the logical configurations of FIGS. 3 and 8. In Figure 8, the audio frequency changes only in two values, 1.5 times and 1/1.5, and if the audio signal at this switching point is out of synchronization, for example, the transmitting side will receive a signal whose frequency has increased by 1.5 times. But on the receiving side,
A state in which the signal increases by 1.5 times exists for the time of the synchronization difference, which causes deterioration of the restored and playback sound quality. From this point of view, this method requires sufficient synchronization control. On the other hand, in the case of FIG. 3, the degree of change in the audio frequency changes stepwise, so even if a slight synchronization shift occurs, there is little shift in the reproduced audio frequency during restoration and there is little deterioration in sound quality. Therefore, the case shown in FIG. 3 is more advantageous in terms of simplifying the synchronization control method and improving restored sound quality.

The above has explained the case of two logic configurations as an example, but various clock frequency controls can be performed by changing the logic configuration, and the present invention also has the advantage of being highly flexible in this respect. .

In the above explanation, in order to simplify the explanation, the BBD variable delay circuits 3 and 14 on the transmitting side and the receiving side are used.
Since we have described an example in which the number of delay stages is N, the repetition frequency of the clock pulses applied to the delay circuits 3 and 14 may be a period during which the counter circuit 19 counts N pulses as shown in FIG. If the number of delay stages of the variable delay circuit 14 on the receiving side is M, the repetition frequency of the frequency control voltage may be set to a period during which the counter circuit counts (M+N)/2 pulses.

Note that when a general delay circuit receives N clock pulses equal to the number of delay stages (N), the signal applied to the input is output from the delay circuit.
In the case of BBD, the signal is stepped by a two-phase clock drive, so the input signal is output with N/2 clock pulses. However, the present invention
It can be applied to CCD and other general delay circuits, so
The claims of the present invention are written so that they can be applied to general delay circuits.

(f) Effects As described above, the present invention provides a secret communication circuit that can obtain a large number of key codes, and if a radio equipped with this system is used, the contents of the call will not be intercepted even if received by a third party. This has a great practical effect in guaranteeing the privacy of calls.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the principle of the present invention.
FIG. 2 is a block circuit diagram of the main part of the confidential circuit according to the present invention, FIG. 3 is an embodiment of the logic circuit, FIG. 4 is a logic diagram when the logic circuit of FIG. 3 is used, and FIG.
The figure shows the clock frequency characteristics when using the logic circuit in Figure 3, Figure 6 shows the conversion ratio characteristics of the output audio frequency when using the same circuit, and Figure 7 shows the scramble waveform when using the same circuit. For example, FIG. 8 is an example of another logic circuit, FIG. 9 is a clock frequency characteristic when using the logic circuit in FIG. 8, and FIG. 10 is an example of another logic circuit.
This is the conversion ratio characteristic of the output audio frequency when the logic circuit shown in the figure is used. Explanation of figure numbers, 3, 14... BBD delay circuit, 1
7... Master clock oscillation circuit, 18... Frequency dividing circuit, 19... Control counter, 20... Logic circuit, 21... Clock pulse, 22... OR circuit, 23... AND circuit.

Claims (1)

[Scope of Claims] 1 (a) a variable delay circuit for signals that sequentially samples and stores signals in accordance with clock pulses and simultaneously outputs them; (b) a master clock frequency oscillation circuit that supplies the clock pulses; (c ) a frequency divider circuit that divides the output frequency of the oscillation circuit; (d) a counter circuit that counts clock pulses supplied to the variable delay circuit; (e) a frequency divider circuit that divides the output frequency of the frequency divider circuit according to the output signal of the counter circuit; A logic circuit for controlling the frequency is provided on the transmitting side and the receiving side of the communication system, and the counter circuit divides the clock pulse supplied to the variable delay circuit by the number of delay stages of the variable delay circuit on the transmitting side and the number of delay stages on the receiving side. By changing the frequency of the clock pulse supplied to the variable delay circuit with a time period counted by the sum of the number of delay stages of the variable delay circuit, the transmission signal is compressed and expanded alternately on the time axis of the transmission signal. A confidential communication device characterized in that the frequency of the signal is converted and sent from the transmitting side to the transmission system, and the original signal is reproduced on the receiving side. 2. The confidential communication device according to claim 1, wherein the frequency division number of the frequency dividing circuit is controlled so that the frequency of the clock pulse supplied to the variable delay circuit periodically repeats a stepwise increase and decrease. . 3 (a) a variable delay circuit for sequentially sampling and storing signals in accordance with clock pulses, and simultaneously outputting the signals; (b) a master clock frequency oscillation circuit for supplying the clock pulses; and (c) an output of the oscillation circuit. (d) a counter circuit that counts clock pulses supplied to the variable delay circuit; and (e) logic that controls the frequency division number of the frequency divider circuit based on the output signal of the counter circuit. A circuit is provided on a transmitting side and a receiving side of a communication system, and the counter circuit divides the clock pulse supplied to the variable delay circuit into the number of delay stages of the variable delay circuit on the transmitting side and the number of delay stages of the variable delay circuit on the receiving side. The frequency of the transmission signal is converted by alternating compression and expansion of the time axis of the transmission signal by changing the frequency of the clock pulse supplied to the variable delay circuit in a time period that is counted by the sum of . The signal is sent from the transmitting side to the transmission system, the original signal is regenerated on the receiving side, and the signal is supplied to the variable delay circuit by changing the output frequency of the master clock frequency oscillation circuit or the logical configuration of the logic circuit. What is claimed is: 1. A confidential communication device characterized in that the frequency change of a clock pulse is set to a predetermined characteristic and converted into a key code.