JPS60109941A - Signal synchronism circuit of ciphered communication device - Google Patents

Abstract

PURPOSE:To improve the secrecy of communication by changing a clock frequency at the reception side in synchronization with the change in the clock frequency at the transmission side. CONSTITUTION:The clock frequency of a variable frequency divider circuit 16 in a clock frequency control circuit 4 is changed to change the clock frequency to a variable delay circuit Delay 3. The frequency of an output voice signal is changed to the original signal to scramble the voice by making the clock pulse frequency when the voice signal is inputted to the Delay 3 different from the clock frequency at output after delay. On the other hand, the frequency of the received scrambled voice is restored to the original signal by changing the clock frequency to a Delay 3' in synchronization with the change in the clock frequency to the Delay 3 at the transmission side by a synchronizing signal circuit 6' at the reception side.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a confidential communication circuit for maintaining communication confidentiality in wired or wireless communication, and more specifically to a signal synchronization circuit for the communication system. It is related to.

(b) Prior art When A, Party A, and Party B are talking in normal wired or wireless communication, if Third Archeology receives a signal in the carrier frequency range used for communication between Party A and Party B, Party A, Party B, There is a problem in that the confidentiality of calls is lost because the content of calls between colors can be intercepted.

An effective method for ensuring this privacy is to scramble the audio signal, send it out, and restore it on the receiving side. According to this method, a third party who does not have a restoration circuit in the receiving section or a third party with a different key code can
Since the received voice remains scrambled, the contents of the call cannot be understood by the person receiving the call, and confidentiality can be maintained.

Conventionally, a circuit element with a built-in balanced modulator (balanced modulation method) has been used as one method of such a confidential circuit.
is generally commercially available. In this method, an audio signal is modulated with a carrier wave of, for example, 5KH2, and only the lower sideband thereof is extracted by filter processing and transmitted. In this case, the frequency of the audio signal is inverted with respect to the original signal.

That is, if the audio frequency is f, then f'-5-f(K
H2). To restore, simply perform the reverse operation, and the audio frequency will be inverted again, so it will return to its original state. In this case, even if the withdrawal wave frequency of the balanced modulator is slightly changed, the pitch of the reproduced sound is only slightly shifted from the original sound, and there is no problem with intelligibility. This means that in this method, only one key code for secret information can be obtained.

Therefore, the content is intercepted by a person equipped with the same type of scrambling circuit, and the message has the drawback that the effect of maintaining confidentiality cannot be achieved. To prevent this,
It is necessary to set a common parameter on the receiving and transmitting sides and create a key code for confidential communication. The larger the number of keys, the higher the privacy.However, in the above method, as mentioned above, the spectrum is simply inverted, so for example, using the carrier frequency of the balanced modulator as a parameter, the carrier wave on the receiving side is Even if the sound is different from the one on the transmitting side, the pitch of the reproduced sound is only slightly different from the original sound, so there is no problem with the intelligibility of the content, and with this method, the number of keys is only two at most. It has the disadvantage that it cannot be used for communication purposes, and it has low practical confidentiality.

Therefore, the present applicant previously proposed Patent Application No. 5'7-164763 dated September 20, 1981, entitled ``Secret phone call method and device.'' In other words, we proposed a method that compresses and expands the time axis of an audio signal and transmits it as a method that has a relatively simple circuit scale and has high confidential speech performance. Also October 2, 1981
He proposed Japanese Patent Application No. 184916/1984 entitled ``Clock circuit for confidential communication system'' on the date 0. The confidential communication method of the applicant's earlier application allows for multiple keys.

(C) Object of the Invention The present invention provides a signal synchronization circuit for a confidential communication system that is a more specific improvement over the technology of the prior application.

(d) Structure of the Invention In order to achieve the above-mentioned object, the present invention provides a variable delay circuit for signals that sequentially samples and stores signals according to clock pulses and outputs the signals, and a clock frequency control circuit that controls the frequency of the clock pulses. The transmission side and the reception side of the communication system are provided with a circuit and a synchronization signal circuit for synchronizing the clock frequencies of the transmission side and the reception side, and the above-mentioned 6
The synchronizing signal circuit is controlled by the first gate signal generated in connection with the frequency control circuit to convert the sine wave etc. into AM.
Modulation modulation- generates a synchronization signal by performing phase modulation processing,
Then, the receiving side demodulates the gate signal in response to the synchronization signal, and generates a trigger signal generated in response to the rising edge of the gate signal in relation to the clock frequency control circuit on the receiving side. Select either the AND output or the trigger signal by using the AND output with a second gate signal that is generated and has the same repetition period as the gate signal, and the selected selection signal The signal synchronization circuit for a confidential communication device is characterized in that it controls the clock frequency control circuit on the receiving side to prevent noise interference in the synchronization signal circuit.

(e) Example Next, the apparatus of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating the principle of the apparatus of the present invention, in which (A) shows the transmitting side and (B) shows the receiving side. First of all
In figure (A), (1) is the audio input terminal, and 2) is the L
It is PF. (3> is a delay circuit (memory circuit) having N delay stages, and a clock frequency control circuit (CPI
) (4) This is a variable delay circuit that samples and stores audio according to the clock, and at the same time constantly stores N sampling values that sequentially output the sampling values that were sampled and stored N sampling points ago. The output of the delay circuit passes through an LPF<5), is added to the output of the synchronizing signal circuit (6) and a synthesis circuit (7), and then passes through a transmitting circuit (8) that performs modulation and amplification for transmission. It is transmitted to a wired or wireless transmission system (9).

On the receiving side of FIG. 1(B), the received signal passes through the transmission system (9) and receives the receiving circuit (10) including an amplification and demodulation circuit.
), the received audio is sampled and stored via the L'PF (11) according to the clock of the clock frequency control circuit (CP 2 ) (4'), and at the same time, the received audio is sampled and stored before the N sampling point. The sampling values are stored in the N sample storage circuit (3') which sequentially outputs the sampling values via LPF (12). 6 Synchronization between the transmitting side and the receiving side is sent from the synchronizing signal generating circuit (6) on the transmitting side. This is done by separating the synchronization signal from the received signal by a synchronization separation circuit of the synchronization signal circuit (6') on the reception side, and using this separated synchronization signal, the clock on the reception side can be completely synchronized with that on the transmission side.

Next, basic circuits on the transmitting side and receiving side of the present invention are shown in FIGS. 2 and 3, respectively. This basic configuration is essentially the same for both the transmitting and receiving sides. In other words, it is synchronized with a variable delay circuit (3) (3'') such as a BBD that inputs and outputs audio signals and a clock frequency control circuit (4) (4') that controls the frequency of its clock pulse (13) (13'). Signal circuit (6
)<6').

To explain in more detail, the clock frequency control circuit (4) (4'
) is the master clock frequency oscillation circuit (15) (15
') and a variable frequency divider circuit (16) (1
6') and a counter circuit (17) (17') that counts clock pulses to delay circuits (3) (3') such as BBD.
and a frequency dividing circuit (16) (16') whose frequency division number is controlled by the output signal of the counter circuit. Also,
The synchronizing signal circuit (6) on the transmitting side in FIG. 2 consists of a gate signal generating circuit (18), a synchronizing sine I wave generating circuit (19), and a gate control circuit (20), as shown in FIG. The synchronization signal circuit (4') on the receiving side shown in FIG. 3 consists of a synchronization separation circuit (21) and a synchronization trigger generation circuit (22).

・ The basic principle of the confidential speech operation of the present invention is explained by taking a sine wave signal as an input signal as an example. The input sine wave signal is processed to periodically shift its frequency up and down, and the audio signal is converted into a voice signal. This changes the spectral structure of the signal and reduces intelligibility. To explain in more detail, in FIG. 2, by changing the frequency division number of the variable frequency divider circuit (16) in the clock frequency control circuit (4), B B D
Allow the clock frequency to change to (3'), so that the audio signal is B
A device that scrambles audio by changing the frequency of the output audio signal relative to the original by making the frequency of the clock pulse when inputting to the BD different from the clock frequency when outputting after a delay. It is.

On the other hand, in the third section on the receiving side, in a circuit having substantially the same configuration as the transmitting side in FIG.
By changing the clock frequency to 4), the frequency of the received scrambled audio is converted again to just return to light, thereby performing a restoration operation.

Next, the above-mentioned operation will be explained in more detail with reference to FIGS. 2 and 3.

The audio signal is taken into the delay circuit (3) according to the clock (13), and is further transferred to the next stage of the memory cell in the circuit like a bucket brigade, and after the clocks for the number of delay stages are input, it is output.Here, 1 The frequency of the input clock f'(i
). Also, if the number of delay stages of the transmitting side delay circuit is N1 and that of the receiving side is N2, then the audio signal (frequency, 0) taken into the transmitting side delay circuit at the first clock is clocked at the (1+N1)th clock. is output from the delay circuit, and at this time the audio frequency (,S) is converted to .

Therefore, by changing f(i) over time, audio frequency conversion can be performed and scrambling processing can be performed.

Next, in order to perform reverse frequency conversion processing on the receiving side and restore it, ...... (2) Therefore, r (i + N1 + N2) = f (+) ...
...(3) It is only necessary to allow r(i) to change periodically so as to satisfy the equation (3).

Furthermore, as a restoration condition, it is necessary that the transmitting and receiving side circuits operate with clocks (13) (13') having the same frequency and phase.

Therefore, if the clock operation is changed on the sending and receiving sides, the original audio signal will not be restored. Therefore, multiple keys can be created by setting the period, phase, and frequency value of the clock frequency change as parameters on the sending and receiving sides. be able to. For example, experiments have shown that when the period differs by 5% or more between the transmitting side and the receiving side, a practically sufficient scrambling effect can be obtained.

It is determined by the number of delay stages, the master clocker frequency of the clock generation circuit, and the configuration of the frequency division control logic. Period T
The easiest way to set this is to change the master clock frequency, which is the output of the clock generation circuit. In this case, the number of keys is approximately 16 per octave. When using a BBD element as an example of a variable delay circuit, the usable range of BBD clock frequencies is IOK.
HZ ~ 200K HZ", which is quite a wide range,
Multiple keys can be created. Further, the number of keys increases further depending on the combination of the phase in the clock frequency change, the frequency division number control logic configuration, etc. If you use this secret method like this,
Communication with high confidential communication performance is possible.

Now, in order to correctly restore the original signal, it is very important to synchronize the clock operations on the transmitting and receiving sides as described above. As shown in Figures 1, 2, and 3, the synchronization method is to transmit a synchronization signal superimposed with an audio signal on the transmitting side, and to perform synchronization control after separating the synchronization signal and audio signal on the receiving side. A configuration is taken. Since the clock frequency value on the transmitting side is controlled by the value of the counter (17), synchronization control can be performed by setting the value of the counter (17') on the receiving side to the same value as that on the transmitting side.

The present invention provides a method for further improving synchronization performance in a synchronization method based on this idea. The basic configuration of the synchronization method according to the present invention is shown in FIGS. 4 and 5. FIG. 4 shows the transmitting side, and FIG. 5 shows the receiving side. BBD in Figure 4
The synchronization signal generation circuit (18) generates a synchronization gate signal (see Figure 6 (a)) based on the output of the counter (17) that counts the input clock in (3), and this signal generates a sine wave oscillation. A tone burst signal (see FIG. 6(b)) obtained by gate-controlling the output of the circuit (19) is superimposed on the audio signal (after scrambling processing) and transmitted as a synchronization signal in the synthesis circuit (7). The frequency of the oscillator (19) should be approximately 5 to 10 KH2, considering the band required for audio reproduction (usually 300 to 3.4 KH2). Figure 7 is created from the output of the counter circuit (17). This is an example of a gate control signal generation logic circuit [:NOR circuit (23)]. In the figure, when the value of the upper four digits of the counter (17) is 0, the gate signal (see FIG. 9(a)) is 1. becomes.

On the receiving side, as shown in Fig. 3, the synchronization signal superimposed on audio No. 3 is separated by a filter (21) [Fig. 6 <C>
When applied to a comparator or a Schmitt trigger inverter, a pulse train as shown in FIG. 6(d) is obtained. In FIG. 6(C), (Vl) indicates the reference voltage of the comparator, and the broken line (N) indicates noise.

Further, when this pulse train signal is passed through an integrating circuit or the like, a single pulse as shown in FIG. 6(e) is obtained. f
Based on the method of presetting the value of the receiving side counter (17') to make it the same value as the transmitting side, it also provides a synchronization protection circuit to prevent synchronization errors caused by noise superimposition. be.

As shown in FIG. 9, the trigger generation timing is slightly delayed (△1) from the rise timing of the gate signal [see G in FIG. 9(a)] [see S in FIG. 9(b)].
This can be compensated for by adjusting the preset value of the counter (17').

Therefore, in the circuit according to the present invention, since a fairly high level is used as the reference voltage for comparison of the comparator etc. [v1 reference voltage in Fig. 6(c)], the synchronization signal [Fig. 6(c)]
However, if there is noise exceeding the reference voltage, the counter will be preset by a trigger caused by the noise, resulting in a synchronization error. In addition, a filter (21) is applied to prevent the audio signal from being mixed into the synchronization signal, but if the audio level is high, this will cause the synchronization
There is also a possibility that the synchronization error may be mixed in with the code [Fig. 6(C)] and cause a synchronization error.

It becomes. That is, as shown in FIG. 5, the circuit for this synchronization protection consists of a single pulse generation circuit (25) and a trigger generation circuit (25) following the pulse train generation circuit (24) on the receiving side.
22), it is inserted between the trigger generation circuit (22) and the load terminal for the counter (17°).

As an example, the basic operation and configuration of the synchronization protection circuit when inserted after the trigger generation circuit (22) will be explained below with reference to FIG. The timing of generation of the trigger (S), which is synchronized by presetting the counter (17'), is slightly delayed (Δt) from the rise of the gate signal (G), as shown in FIG. 9(b).

Furthermore, the receiving side counter (,
17゛), the generation timing of the gate signal (G) controlled by the receiving side counter will also be as shown in Figure 9(a).
This is the same as that on the sending side shown in (G).

Therefore, in the present invention, the preset trigger signal [see S in FIG. 9(b)] and the gate signal [S in FIG. 9(a)]
The signal obtained by AND logic with [Figure 9 (C) is used to preset the counter (17'):
ing. Furthermore, this AND output signal is sent to a counter (17
'>(7), the state used for presetting will be referred to as the synchronization locked state.

Now, as mentioned above, the preset trigger is shown in Figure 6(e).
However, the time width of this single pulse is approximately equal to the gate signal width, so no trigger due to noise is generated during this time. Therefore, synchronization protection can be achieved by AND logic with the gate signal (G) as described above. Furthermore, in order to enter the correct state of synchronization lock, in the present invention, as shown in FIG.
Lock 0N-O consisting of F (28) and counter (29)
The FF control circuit (30) is configured to do this.

In addition, the counter (17') that controls the clock frequency is shown below.
will be referred to as a first counter, and the synchronous control counter (29) will be referred to as a second counter.

(27) is a selection circuit, which receives the trigger signal and the output AND signal of the AND circuit (26) of the trigger signal and the gate signal.

Further, an example of a time chart is shown in FIG. Gate signal (
The time relationship between G) and the preset trigger signal is shown in Fig. 9. When the gate output signal is at the counter (17') value corresponding to "o", the counter (1
7°), the gate signal on the receiving side becomes "1" from the preset timing. Note that the timing of switching to "o" is the same as in the case of FIG. In the receiving side time chart Figure 11, when the trigger (al) is in the state (this is assumed to be a noise signal), the lock is not applied, and in this case, the counter (17') is preset by this trigger. ,
Since the gate signal (bl) is output approximately at the timing of this trigger (al) (actually with a slight delay), (cl)
An AND signal like this can be output.

Now, R8-FF (28) is set at the rising edge of this AND signal. When the Q signal of this R8-FF is set to 1'', the lock defined above is applied and the AND signal is selected as the load input to the counter (17').

Further, when the Q signal is "0" (lock OFF state), the preset trigger signal is immediately input to the load terminal.

In addition, the second counter (29) performs a counting operation at the rising edge of the gate signal as a clock pulse, and is reset by AN.
It becomes active when the D signal is "1".

Therefore, the counter (29) counts one digit at the rise of the gate signal (bl) as shown in FIG. 11, but after several n Sec [
The delay time of the AND circuit (26> and the inverter circuit (31)) is reset.RS-FF (28) is reset when the value of the counter (29) is 2 (QB
It works when -1>.

Now, by the signal (al) in FIG. 11(a), R3-F
Since F is set and locked, the preset signal (a2) (synchronization signal) is ignored (that is, AND
The signal 'o'') does not preset the counter (17').The gate signal is output after - period like b2), but it is locked not by the synchronization signal but by the noise signal (al). At the timing b2), the AND signal output is 0". Subsequently, the gate signal is output as shown in (b3). Even at this timing, the AND signal output is "0". - Therefore, the value of the counter (29) becomes 2 due to these gate signals (b 2) (b 3), and at this time [RS -F at the rising edge of gate (b3)
F(2g) is reset and unlocked. Next, the lock is applied in the same way with the synchronization signal (a4), but if the lock is applied with the synchronization signal, the timing of the synchronization signal in the preset signal, for example (a5) or (a7), and the gate signal ( b5, b6), the value of the counter (29) does not become 2 and the locked state continues. Furthermore, noise in the preset signal (a6, a8, etc.) does not affect the preset operation due to synchronization lock.

Next, in the circuit of the embodiment, the synchronization signal in the preset signal is 1
The structure is such that synchronization protection works even if an individual is missing. That is, when the synchronization signal is lost at the timing (a9), the lock is lost at the rising timing of the gate signal (b8), but the synchronization lock is immediately applied by the synchronization signal (all). Therefore, even if there is noise (alo) or (al2), synchronization will not be lost.

Although the above description has been made using B and BD as examples of variable delay circuits, it goes without saying that the same configuration can be achieved using CCDs and shift registers.Furthermore, when using digital memory circuits such as RAM, For this purpose, the circuit can be appropriately rearranged by combining it with a D/A circuit or an A/D circuit. Furthermore, in the above description, the sine wave oscillation circuit (1
We have explained an example in which a tone burst signal obtained by gate-controlling the output of step 9) is used as a synchronization signal, but synchronization can also be achieved by controlling the synchronization signal generation circuit with a signal generated in conjunction with the clock frequency control circuit and performing phase modulation. A signal may also be generated. In this way, even if the synchronization lock circuit of the present invention is incorrectly locked due to initial noise, the response until it is properly synchronized is quick, and even if the synchronization signal is lost, there will be no malfunction due to noise, and the synchronization will not occur immediately. Since it operates as if relocking is applied, the improvement in synchronization performance is very large.

(f) Effects of the Invention As described above, by using the synchronization signal circuit according to the present invention, it is possible to prevent synchronization malfunctions even when noise is mixed in, and it is possible to solve the problem of deterioration of reproduced sound quality due to synchronization errors. Also,
The present invention is very useful in practice, as it is possible to carry out a telephone call with excellent confidential communication performance using a confidential communication circuit using a variable delay circuit using the synchronization method according to the present invention.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the principle of the present invention, FIGS. 2 and 3 are block diagrams explaining the basic principle of the confidential communication system of the present invention, and FIGS. 4 and 5 are block diagrams of the above system. A block diagram to explain the basic principle of a synchronous circuit,
Figure 6 shows signal waveforms in the circuits of Figures 3 and 4, Figure 7 is a circuit diagram showing an example of a circuit that generates the gate signal of Figure 6(a), Figure B A specific block diagram for explaining the basic configuration of the signal synchronization circuit of the invention, FIG. 9 is a drawing showing signal waveforms in the circuit of FIG. 8, FIG. 10 is a specific embodiment of the present invention, and FIG. 11 is a time chart for explaining FIG. 1θ. Explanation of main drawing numbers (1)...Input terminal, (3)(3')...Variable delay circuit, (4> path, (13)(ts゛)...Clock pulse, (15)( 15')...Clock generation circuit, (
16〉ri16゛〉...Variable frequency divider circuit, (17) (17
')... Counter, (18>... Gate signal generation circuit, (20)... Gate control circuit, (22)... Trigger generation circuit, (27)... Selection circuit. 8th Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Scope of Claims] (1) (a) A variable delay circuit for a signal that sequentially samples and stores a signal according to a clock pulse, and outputs the same; (b) A clock frequency control circuit that controls the frequency of the clock pulse; (c) a synchronization signal circuit for synchronizing the clock frequencies of the transmitting side and the receiving side; and a synchronizing signal circuit provided on the transmitting side and the receiving side of the communication system, and generated in association with the clock frequency control circuit on the transmitting side. A first gate signal controls the synchronizing signal circuit to generate a sine wave, etc.
A synchronizing signal is generated by performing modulation or phase modulation, and the receiving side demodulates the gate signal in response to the synchronizing signal, and a trigger signal is generated in response to the rising edge of the gate signal. and a second gate signal which is generated in connection with the clock frequency control circuit on the receiving side and whose repetition period is the same as that of the gate signal. A signal synchronization circuit for a confidential communication device, characterized in that one of these is selected and the clock frequency control circuit on the receiving side is controlled by the selected selection signal to prevent noise interference in the synchronization signal circuit. (2) A signal synchronization circuit for a secure communication device according to claim 1, wherein the clock frequency control circuit includes at least a counter circuit for counting the clock pulses that can be applied to the variable delay circuit. (3) The signal synchronization circuit of the confidential communication device according to claim 2, which performs preset control of the counter circuit on the reception side using the selection signal. (4) The synchronization signal circuit on the reception side controls the trigger signal and the second the AND circuit that outputs an AND with a gate signal;
a second counter circuit that counts the gate signal that is the output of the counter circuit that counts clock pulses applied to the variable delay circuit and is reset by the AND output; It consists of an R8 flip-flop circuit that is reset by the output of the second counter, and a selection circuit that selects either the trigger signal or the output signal of the AND circuit according to the output of the R8 flip-flop circuit. A signal synchronization circuit for a confidential communication device according to claim 2 or 3.