JPS60109342A - Privacy communication device - Google Patents

Abstract

PURPOSE:To increase the number of keys by using the output of a sampling frequency changing counter as a key to produce a synchronizing signal. CONSTITUTION:The sound signals are fetched into delay circuits 3 and 3' at the transmission and reception sides according to clocks 13 and 13' and then delivered after the clocks of the same number as the delay stages are supplied. The frequencies of clocks 13 and 13' are changed by control circuits 4 and 4'. The clock frequencies of the transmission side is changed by a variable frequency divider 16, and a synchronizing signal is delivered via a synchronizing signal circuit 6 when a counter 17 has the specific count value. At the reception side a counter 17' is preset by the output of a synchronizing separator circuit 6' and the phase of the clock pulse is synchronized with that of the transmission side. In such a way, the values of counters 17 and 17' can be used as keys. This increases the number of keys.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Industrial Application The present invention relates to a confidential communication circuit system for guaranteeing confidentiality of telephone calls in glueless communication.

(Explanation 1) In conventional technology and government communication, when Party A and Party B are talking, if Party C receives a signal in the carrier frequency range used for communication between Party A and Party B. There is a problem in that the confidentiality of the calls is lost because the contents of the calls between the two parties can be intercepted.

An effective method for guaranteeing this privacy is to scramble the audio signal, send it to -C, and restore it on the receiving side. According to this method, the contents of the call will not be understood by the sixth party who does not have a restoration circuit in the receiving unit or who has a different key code because the received voice remains scrambled. Conventionally, as one method of such a confidential communication circuit, a circuit element using a balanced modulator (balanced modulation method) is generally commercially available. After modulating with a 5KH2 carrier wave, only the lower side band wave is extracted by filter processing and transmitted.In this case, the frequency of the audio signal is inverted with respect to the original signal.In other words, the audio frequency If f is
f'=5-f(KH2). To restore it, just do the opposite, and the audio frequency will be inverted again, so it will return to its original state. In this case, even if the carrier frequency of the balanced modulator is slightly changed, the pitch of the reproduced sound is only slightly shifted from the original sound, and there is no problem with intelligibility. This means that in this method, only one key code for secret information can be obtained. Therefore, it has the disadvantage that the effect of maintaining confidentiality cannot be exhibited for those equipped with the same type of scrambling circuit.

l/i Purpose It is an object of the present invention to provide a device in which a large number of key codes are provided in response to such a request for guaranteeing confidentiality.

B) Structure The present invention basically consists of a transmitter that scrambles an audio signal and a receiver that restores the scrambled audio signal.

More specifically, the present invention includes a variable delay circuit for sequentially sampling and storing signals according to clock pulses and outputting the signals at the same time, a clock frequency control circuit for controlling the frequency of the clock pulses, a transmitter 41111, and a receiver. a synchronization signal circuit for synchronization, a counter circuit included in the clock frequency control circuit and counting the clock pulses applied to the variable delay circuit, and an output audio signal and synchronization signal of the variable delay circuit on the transmission side. (E) Example Next, the apparatus of the present invention will be explained in detail with reference to the drawings.0 Figure 1 is a block diagram illustrating the principle of the apparatus of the present invention.
A] indicates the transmitting side, and (B) indicates the receiving side.
In figure (A), Ill is an audio input terminal, (21 is L
It is PF. (31 is a delay circuit (memory circuit) having N delay stages, and a clock frequency control circuit (CP1
At the same time, a variable delay circuit constantly stores N sampling values, which sequentially outputs the sampling values sampled and stored before the N sample time points. The output of the delay circuit is added to the output of the synchronization signal circuit (6) by the synthesis circuit (7) after passing through the LPF151e, and then sent to the transmission circuit (via wired or wireless 81) which performs modulation and amplification for transmission. transmission system (91).

On the receiving side in FIG. 1(B), the received signal that has passed through the transmission system +91 is transferred to the receiving circuit 11 (
After demodulating with L, the received audio is sampled and stored in accordance with the clock of the clock frequency control circuit (CP2 41) through L
N sample storage circuit output via PF[121 +3
1 is stored. The synchronization between transmitting (1 (!l) and receiving (lIll) is to separate the synchronizing signal sent from the transmitting side synchronizing signal generation circuit (6) from the received signal by the receiving 41111's synchronizing signal circuit (61). This is done by completely synchronizing the reception (III) clock with that of the transmission (III) using a separated synchronization signal.

Next, the basic circuits of the transmitter side and receiver (ill) of the present invention are shown in FIGS. Delay circuit (31 (31) and its clock pulse (131a) such as output BBD (clock frequency control circuit 14 that controls the frequency of 31) and synchronization signal circuit f6
+f6+'. To explain in more detail, the clock frequency control circuit 14 bar 41 includes a master clock frequency oscillation circuit usas, variable division circuits tt61a and tt61e for frequency dividing the output thereof, and a delay circuit +311 such as BBD.
A counter circuit (17) that counts clock pulses to 31
1 (171) and the branch circuit f by the output signal of the counter.
161 Logic circuit for controlling the number of minutes of +lθ (J
It consists of kun + a +. Also, the transmission 4Bl+ in Figure 2
The synchronization signal circuit +61 of the receiver 1111 in FIG.
41 is a synchronization separation circuit (2υ) and a synchronization trigger generation circuit (2υ).
The basic principle of the present invention is explained by taking a sine wave I as an input signal as an example. As shown in Figure 4, the spectral structure of the audio signal is changed by synchronously shifting the frequency up and down,
To explain in more detail, the second
In the figure, the clock frequency control circuit (variable frequency divider circuit in 41 [1, 61 by changing the frequency division number)
a By changing the clock frequency to D13+ and making the frequency of the clock pulse when the audio signal is input to the BBD different from the clock frequency when outputting after the delay, the frequency of the output audio signal can be changed to the original one. On the other hand, on the receiving side in Fig. 6, in a circuit with approximately the same configuration as that in Fig. 2 of the transmitting IIJ, B B D1 in the transmitting 4uh K is changed.
BB on the receiving side in synchronization with the change in clock frequency to 3+.
By changing the same wave number of the clock to D(141), the frequency of the received scrambled audio is converted again so as to return to the original frequency, thereby performing a restoration operation.

Next, the above-mentioned operation will be explained in more detail with reference to FIGS. 2 and 5.

The audio signal is sent to the delay circuit 13+(3+' by the clock (131)
(It is taken in according to Ii and transferred to the next stage of the memory cell in the delay circuit like a ljK relay, and after inputting the clocks for the number of delay stages, it is output. Here, the clock frequency when the audio signal is input is If fa is the clock frequency when the delayed signal is output, fb is the clock frequency when the delayed signal is output, then the audio signal at the time of output is converted to f b / f a times the wave number and sent out. Therefore, the clock frequency must be varied. Scrambling processing can be performed by 0 Here, the transmission (ill delay circuit (31) has a clock of 8e when the audio signal is input, the number is fl, and the clock same wave number when outputting the signal after delay is f2, then the receiving side delay circuit The clock frequency when inputting to M11 is f2, and the clock frequency when outputting from the receiving side after delay is f3. f2/f1 x f5/f'2
= 1, that is, the clock frequency should be changed by giving a period equal to the sum of the delay times between the transmitting side and the receiving side (Ill) so that f5=f1. Then, as shown in FIGS. 2 and 6 Clock frequency control circuit (4) 14I is J
: This is a circuit that controls the conversion of the voice station wave number as shown in the following.

Now, unless both the transmission (111) and reception (4111) circuits operate at the same frequency and the same phase clock, the original signal will not be restored correctly.The present invention utilizes this relationship between frequency and phase. !I and reception (lull) to create many keys using the clock phase as a parameter. That is, the present invention utilizes the fact that the clock frequency is determined by the value of the counter qyot6. When the transmitting side counter (17I) has a certain value, a gate signal is generated from the gate signal generation circuit (19), and this signal is used to generate a carrier wave (for example, a sine wave with a frequency of 5 to 10 KHz) of the carrier wave generation circuit for synchronization. The gate Ill is controlled by the gate control circuit t21), and this gate-controlled signal is used as a synchronization signal.Then, this synchronization signal is applied to the synthesis circuit (7) to convert it into a scrambled audio signal. It is superimposed and transmitted to the can feeding yarn (91).

On the other hand, reception 01! l (Fig. 5), the synchronization separation circuit (
211 separates the synchronization signal in the received signal, generates a trigger signal in the synchronization trigger generation circuit 122, applies the emblem and trigger signal to the Grise/Soto value control circuit (2), and applies it to the preset value control circuit (23). ), the counter circuit of is preset to the same value as the counter an on the transmitting side.

In the present invention, in order to create a key, a gate signal generation circuit (Il
The value of the transmitting side counter fin when sending out the output gate signal of l and the value to preset the receiving side counter ai are set as a pair of parameters, and if the keys are different, the original signal will not be restored correctly and the contents will not be understood. It is configured so that it does not occur.

Next, a concrete example of the present invention will be explained with reference to FIGS. 5 and 6.

First, in FIG. 5, the clock frequency on the transmitting side is determined according to the value of the counter (In).
) is the sum of the delay times of the delay circuits tsrtsr on the transmitting side and the receiving side, that is, the time required to count the clock for the sum of the number of delay stages of transmitting and receiving (#!l) The clock wave number changes in this period.The output gate signal of the gate signal generation circuit a9 is obtained from the output of the NOR circuit @ in the figure.In the example in the figure, the key setting terminal ('l'1) For example, if ('r2) ('['5) (T4) are (1, 0, 1, 0), the counter Q7J
The values of Q1=R1, Q2==0, Q3=1, Q4-00
Then, the output (G) of the NOR time mtu is ]", and in other cases it is 1ゞo". Using this gate signal, the synchronization carrier wave (sine wave or rectangular wave of 5 to 10 KHz) is controlled by the gate control circuit 121) f[The controlled signal is used as a synchronization signal〇On the other hand, on the receiving side is extracted by a synchronous separation circuit Qυ made up of a filter, and the rising timing of this signal is detected to generate a trigger pulse, which presets the counter an* on the receiving side. The preset value at this time will be the same value as on the transmitting side if it is configured with a circuit like No. 6C. In Figure 6, (T1) (T2) (T5) (
T4J is the key set terminal, (LlJ(L2J(Lg)
... is the load input terminal for counter preset, (Ql
)(Q2)(Q5)...These are counter outputs.

An example of a circuit for generating a trigger for presetting the counter circuit ai in the busy reception 41111 will be described. Figure 7 7. (Figure 87 is goo) It is a synchronization signal with ftil, 'l+ll, and when this signal is passed through a comparator circuit, (
b) A pulse train as shown in the figure is obtained. In addition, in figure (a) (
? J is I8&a! 5-10 KHz tD (carrier wave signal for ifJ period signal, (vl) is the reference voltage of the comparator. Furthermore, if the pulse train of (b) C is passed through, for example, a monostable circuit, the pulse train as shown in (c) A single pulse consisting of a series of is obtained, and a trigger pulse as shown in FIG.

At this time, the trigger generation timing in the dJ diagram is the rising time of the first two pulses of the pulser IJ in diagram (b), which is the comparator output waveform.
If the frequency is about 5 to 10 KHz, this timing is
The gate signal generation circuit of ti11 (9th gate, which is the output of 19; the rise of the 1st voice group signal is slightly delayed (Δt). This delay is caused by the lower value of the 4MQ counter a% (
By further setting preset values for (Qs, Q6, Ql, etc.), light component extraction can be performed.

In the above description of the actual winding example, for convenience, an example was shown in which z4-i6 keys were created. Experiments have shown that if the clock operation phase differs by about 10 to 15 degrees or more between the transmitter and the receiver, the content of the reproduced audio signal becomes almost inaudible. Therefore, in this case, the number of key codes is 20 to 40.
Streets can also be built. In this way, by creating keys using the phase of the clock frequencies on the transmitting side and the receiving side as parameters, it is possible to have a large number of keys. Keys can also be created by changing other parameters such as the master clock frequency on the transmitting and receiving sides, so by combining these, hundreds of different keys are possible.

Furthermore, in the above explanation, the 88D was used as an example of the variable delay circuit, but it goes without saying that a similar configuration can be made using a COD or a shift register. RAM in history
When using digital memory circuits such as
The circuit can be appropriately rearranged by combining it with a circuit or an A/D circuit.

(f) Effects As described above, the present invention provides a scrambling device that can generate a larger number of keys than by creating keys using the preset values of the counter circuits that control the clock frequencies on the transmitting and receiving sides as parameters. Based on this method, if wired or wireless devices equipped with circuits are used, the contents of the call will not be intercepted even if received by a third party, and a great practical effect can be obtained in carrying out confidential communication. .

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram showing the principle of the present invention, Fig. 2 is a block diagram of the transmission side circuit of the secure communication device of the invention, Fig. 3 is a block diagram of the receiving 411 circuit of the same equipment, and Fig. 4 is the block diagram of the main unit. Characteristic diagram of the scramble signal waveform processed by the device of the invention, No. 5
The figure shows a specific example of a gate signal generation circuit used in the device of the present invention, FIG. 6 shows a specific example of a preset value control circuit used in the device of the present invention, and FIG. 7 shows a signal waveform used for synchronization. be. 1 'UQ @(D N'il"4;tl+...input terminal, +a++ai...variable delay circuit, +41A・
... Black (b'> Tsuku frequency control circuit, (6)... Synchronization signal circuit, →→
-1, +71...Synthesis circuit, +9...Transmission system, (131...Clock pulse, (14+...Output terminal, ++s+am...Master clock 1 pulse number firing circuit, u6Iae ...Variable minute circuit, ++71+tn...Counter circuit, aaai
...Logic circuit, (19...Gate signal generation circuit, (
20+...Synchronization carrier generation circuit, (211...Synchronization separation 1 circuit, (22...Synchronization trigger generation circuit,!
? ,'(+...Preset value control circuit. Figure 4 Figure 7:; -ζ1

Claims (1)

[Scope of Claims] (A1) A signal variable delay circuit that sequentially samples and stores a signal according to a clock pulse, and outputs the same; (b) A clock frequency control circuit that controls the number of cycles of the clock pulse; 01 transmission (11) and reception (tli) are provided on the transmitting side and the receiving side of the communication system, and the clock frequency control circuit counts the clock pulses applied to the variable delay circuit. a counter circuit that controls one wave number of the clock pulse in relation to the output of the counter circuit, and is responsive to the output of the counter circuit when the counter circuit of the transmission 41t11 counts a predetermined clock pulse. A synchronization signal is generated in the synchronization signal circuit, and the output sound ¥R signal of the variable delay circuit of the transmission 4111 and the synchronization signal are synthesized in a synthesis circuit, and then transmitted to the transmission system, and then transmitted to the reception system 4111. The synchronizing signal is separated at , and the counter circuit of the receiver 41111 is preset by the separated synchronizing signal, and the value of the counter circuit at the time of sending the synchronizing signal of the transmitter 411+1 and the value for presetting the counter circuit of the receiving side are set. A secret communication device characterized by creating a key code as a parameter○ (2) The upper part of the counter circuit is used for setting the key code,
The confidential communication device according to claim il+, characterized in that the lower order is used to compensate for synchronization delay in reception 4111.