JPH02184086A - Chip holder for josephson integrated circuit - Google Patents

Chip holder for josephson integrated circuit

Info

Publication number
JPH02184086A
JPH02184086A JP280489A JP280489A JPH02184086A JP H02184086 A JPH02184086 A JP H02184086A JP 280489 A JP280489 A JP 280489A JP 280489 A JP280489 A JP 280489A JP H02184086 A JPH02184086 A JP H02184086A
Authority
JP
Japan
Prior art keywords
chip
inductance
chip holder
integrated circuit
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP280489A
Other languages
Japanese (ja)
Inventor
Shuichi Tawara
修一 田原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP280489A priority Critical patent/JPH02184086A/en
Publication of JPH02184086A publication Critical patent/JPH02184086A/en
Pending legal-status Critical Current

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  • Containers, Films, And Cooling For Superconductive Devices (AREA)

Abstract

PURPOSE:To transmit a high-speed signal from a signal line at room temperature to a cryogenic Josephson integrated circuit chip without causing a greater reflection by connecting a passive element of inductance and capacitance between a strip line and an electrode electrically connected to this strip line in a chip holder. CONSTITUTION:An inductance element 6 and a capacitance element 7 inserted between a strip line 4 and a contact electrode 8 on a chip holder constitutes a resonance circuit, which transmits a signal onto a chip at a resonance frequency f0. The inserted inductance and capacitance plays a role of an impedance conversion circuit for the characteristic impedance of a signal line and the characteristic impedance on the chip. In this chip holder, the resonance frequency f0 can be changed easily by varying the values of the inserted inductance and capacitance, and a high-speed signal can be transmitted.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はジョセフソン集積回路チップと外部回路との電
気的接続を取るためのジョセフソン集積回路用チップホ
ルダー、特に高速の動作測定を行う場合に用いるチップ
ホルダーに関するものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a Josephson integrated circuit chip holder for electrically connecting a Josephson integrated circuit chip to an external circuit, especially when performing high-speed operation measurements. This relates to a chip holder used for.

(従来の技術) ジョセフソン集積回路においては、外部との電気接続用
のコンタクトパッドとして、超伝導材料であるNb、 
Nb合金が一般に用いられている。ジョセフソン集積回
路は液体ヘリウム中での測定を必要とするため、一般の
半導体集積回路のようにワイヤーポンディングによる接
続を取ることは効率の良い方法とは言いがたい。そこで
第3図に示すような、チップホルダーを用いる。これは
ジョセフソン集積回路チップ25のコンタクトパッドに
対応した位置の絶縁基板22上にストリップ線路24や
コンタクト用電極を形成したジョセフソン集積回路チッ
プとチップホルダーを対抗させて、接触により電気接続
を取り基板22の裏面で信号線23と接続する方法が取
られている。この時、チップホルダー側のコンタクト用
電極にバネ作用をもたせることで電気接続を確実にする
ことが行われている。この方法はハンダ付けなどの方法
に比べ簡便であるため、液体ヘリウム中での測定が不可
欠であるジョセフソン集積回路の測定には非常に有効で
ある。
(Prior Art) In Josephson integrated circuits, Nb, which is a superconducting material, is used as a contact pad for electrical connection with the outside.
Nb alloys are commonly used. Since Josephson integrated circuits require measurements in liquid helium, it is difficult to say that connecting them by wire bonding, as is the case with general semiconductor integrated circuits, is an efficient method. Therefore, a chip holder as shown in FIG. 3 is used. This involves placing a chip holder against a Josephson integrated circuit chip on which strip lines 24 and contact electrodes are formed on an insulating substrate 22 at positions corresponding to the contact pads of the Josephson integrated circuit chip 25, and establishing an electrical connection through contact. A method is used in which the signal line 23 is connected to the back surface of the board 22. At this time, electrical connection is ensured by providing a spring action to the contact electrode on the chip holder side. Since this method is simpler than methods such as soldering, it is very effective for measuring Josephson integrated circuits, which must be measured in liquid helium.

(発明が解決しようとする課題) しかしながら、この方法は、ストリップ線路とジョセフ
ソン集積回路チップとの間での信号の反射が問題になっ
てくる程度の高速の測定には適当とは言えない。ジョセ
フソン集積回路は電流駆動型の回路であり、一般にその
入力インピーダンスは数mΩから数Ω程度と、外部回路
やストリップ線路のインピーダンスに比べ低い。従って
、数100MHz以上の周波数で信号を送る場合、イン
ピーダンスの変換回路が必要である。特に大電力を送る
必要のあるパワーラインなどでは信号の反射が大きな問
題となる。従来、この変換回路としてはチップ上にトラ
ンスフォーマをつけたり、LC共振回路を設けたりする
ことにより、高速の信号を伝搬することが考えられてい
たが、この方法ではチップ上での回路構成が複雑になる
こと、上限周波数に制限があること、周波数帯域が一定
であることなどの問題がある。
(Problems to be Solved by the Invention) However, this method is not suitable for high-speed measurements where signal reflection between the strip line and the Josephson integrated circuit chip becomes a problem. A Josephson integrated circuit is a current-driven circuit, and its input impedance is generally on the order of several milliohms to several ohms, which is lower than the impedance of an external circuit or a strip line. Therefore, when transmitting signals at a frequency of several 100 MHz or higher, an impedance conversion circuit is required. Signal reflection is a big problem, especially in power lines that need to transmit large amounts of power. Conventionally, this conversion circuit was thought to propagate high-speed signals by attaching a transformer on the chip or providing an LC resonant circuit, but this method required a complicated circuit configuration on the chip. There are problems such as the fact that the frequency band is constant, the upper frequency limit is limited, and the frequency band is constant.

本発明の目的は、上記問題点を除去したチップホルダー
を提供することにある。
An object of the present invention is to provide a chip holder that eliminates the above-mentioned problems.

(課題を解決するための手段) 本発明によれば、絶縁基板上に複数個のストリップ線路
と、該ストリップ線路と電気的に接続した複数個の電極
とを形成したチップホルダーにおいて、前記ストリップ
線路と前記電極との間にインダクタンスとキャパシタン
スよりなる受動素子を接続したことを特徴とするジョセ
フソン集積回路用チップホルダーが得られる。
(Means for Solving the Problem) According to the present invention, in a chip holder in which a plurality of strip lines and a plurality of electrodes electrically connected to the strip lines are formed on an insulating substrate, the strip line A chip holder for a Josephson integrated circuit is obtained, characterized in that a passive element consisting of an inductance and a capacitance is connected between the electrode and the electrode.

(作用) チップホルダー上のストリップ線路は通常外部回路との
周波数整合を取るために、50Ωのインピーダンスに設
計される。一方、ジョセフソン集積回路の入力インピー
ダンスは数mΩから数Ωとストリップ線路に比べ小さい
ので、整合を取るための変換回路が必要である。ストリ
ップ線路上に設けたインダクタンスとキャパシタンスと
からなる共振回路は、ある周波数帯域の信号に対しては
、インピーダンス整合を取る役目を果たす。ストリップ
線路上に設けた受動素子は、チップ上に設けた場合と異
なり、容易に取り外しが可能であり、必要な測定周波数
に合わせて、パラメータを選ぶことができる。
(Function) The strip line on the chip holder is usually designed to have an impedance of 50Ω in order to achieve frequency matching with an external circuit. On the other hand, since the input impedance of the Josephson integrated circuit is from several mΩ to several Ω, which is smaller than that of a strip line, a conversion circuit is required for matching. A resonant circuit made of inductance and capacitance provided on the strip line serves to match impedance for signals in a certain frequency band. Unlike passive elements provided on a chip, passive elements provided on a strip line can be easily removed, and parameters can be selected according to the required measurement frequency.

(実施例) 第1図は本発明の詳細な説明するためのチップホルダー
の模式図である。図において1はチップ装着部、2は絶
縁基板、3は信号線、4はストリップ線路、5はジョセ
フソン集積回路チップ、6はインダクタンス素子、7は
キャパシタンス素子を示す。第2図にチップホルダーの
等価回路を示す。第2図において、11はインダクタン
ス、12はキャパシタンス、13は信号の特性インピー
ダンス、14は電源、15はジョセフソン集積回路チッ
プの入力インピーダンス、16はジョセフソン集積回路
チップ部分の等価回路、17は電極、及びチップ上の配
線の寄生インダクタンスを示す。第1図に示すようにジ
ョセフソン集積回路チップ5はチップホルダー上のチッ
プ装着部1に圧着され、バネ状のコンタクト電極と電気
的に接触する。ここで例えば8にゲートレベルの電源線
に500MHzの周波数で電流を供給する場合を考える
。信号線3およびストリップ線路4の特性インピーダン
スは通常50Ωであり、ジョセフソン集積回路チップ5
の特性インピーダンスは約3mΩと非常に低い。このま
までは双方のインピーダンスは不整合であり、高速の信
号を伝搬する場合に大きな反射が生じてしまうが、チッ
プホルダー上のストリップ線路4とコンタクト電極8の
間に挿入されたインダクタンス素子6とキャパシタンス
素子7は第2図(a)に示すように、共振回路を構成し
、第2図(b)に示されるように、ある共振周波数fo
においてチップ上に信号を伝搬することができる。本来
の場合、電極及び配線のインダクタンスを約40pHと
仮定すると、L = 87pH,C= 794pFでf
□ = 500MHzの共振周波数でジョセフソン集積
回路へ電流を供給することが出来る。言い換えると、挿
入されたインダクタンスとキャパシタンスは信号線の特
性インピーダンスとチップ上の特性インピーダンスとの
インピーダンス変換回路の役割を果たしている。このチ
ップホルダーにおいては、共振周波数f0は挿入された
インダクタンスとキャパシタンスの値を変えることで容
易に変更でき、必要な高速信号を伝えることができる。
(Example) FIG. 1 is a schematic diagram of a chip holder for explaining the present invention in detail. In the figure, 1 is a chip mounting part, 2 is an insulating substrate, 3 is a signal line, 4 is a strip line, 5 is a Josephson integrated circuit chip, 6 is an inductance element, and 7 is a capacitance element. Figure 2 shows the equivalent circuit of the chip holder. In FIG. 2, 11 is an inductance, 12 is a capacitance, 13 is a signal characteristic impedance, 14 is a power supply, 15 is an input impedance of the Josephson integrated circuit chip, 16 is an equivalent circuit of the Josephson integrated circuit chip, and 17 is an electrode. , and the parasitic inductance of the wiring on the chip. As shown in FIG. 1, a Josephson integrated circuit chip 5 is pressed onto a chip mounting portion 1 on a chip holder and is brought into electrical contact with spring-like contact electrodes. For example, consider the case where a current is supplied to the gate level power supply line 8 at a frequency of 500 MHz. The characteristic impedance of the signal line 3 and the strip line 4 is typically 50Ω, and the characteristic impedance of the Josephson integrated circuit chip 5 is
The characteristic impedance of is approximately 3 mΩ, which is very low. In this state, the impedances of both sides are mismatched, and large reflections occur when high-speed signals are propagated. 7 constitutes a resonant circuit as shown in FIG. 2(a), and as shown in FIG. 2(b), a certain resonant frequency fo
signals can be propagated onto the chip at In the original case, assuming that the inductance of the electrode and wiring is approximately 40 pH, L = 87 pH, C = 794 pF, and f
□ = Can supply current to the Josephson integrated circuit at a resonant frequency of 500 MHz. In other words, the inserted inductance and capacitance play the role of an impedance conversion circuit between the characteristic impedance of the signal line and the characteristic impedance on the chip. In this chip holder, the resonant frequency f0 can be easily changed by changing the values of the inserted inductance and capacitance, and the necessary high-speed signal can be transmitted.

また、本チップホルダーは準静的な測定にも対応するこ
とができる。
Additionally, this chip holder can also be used for quasi-static measurements.

(発明の効果) 本発明のチップホルダーを用いることにより、必要な周
波数帯域において、室温下の信号線からの高速信号を、
大きな反射を生じる事なく、極低温化のジョセフソン集
積回路チップへ伝搬することができる。この周波数の値
はチップホルダー上のインダクタンスとキャパシタンス
の値を変えることで、容易に変更することができる。ま
た、準静的な測定にも対応することができる。
(Effects of the Invention) By using the chip holder of the present invention, high-speed signals from signal lines at room temperature can be transmitted in the necessary frequency band.
It can be propagated to cryogenic Josephson integrated circuit chips without significant reflection. The value of this frequency can be easily changed by changing the values of inductance and capacitance on the chip holder. Additionally, it can also be used for quasi-static measurements.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図に本発明の実施例の模式図を、第2図に該実施例
の等価回路図を、第3図に本発明の従来例の模式図を示
す。 図において、1.21・・・チップ装着部、2,22・
・・絶縁基板、3,23・・・信号線、4,24・・・
ストリップ線路、5,25・・・ジョセフソン集積回路
チップ、6・・・インダクタンス素子、7・・・キャパ
シタンス素子、8・・・コンタクト電極、11・・・イ
ンダクタンス1.12・・・キャパシタンス、13・・
・インピーダンス、14・・・電源、15・・・チップ
上のインピーダンス、16・・・ジョセフソン集積回路
チップ部分、17・・・電極及び配線の寄生インダクタ
ンス、を示す。
FIG. 1 is a schematic diagram of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the embodiment, and FIG. 3 is a schematic diagram of a conventional example of the present invention. In the figure, 1.21...chip mounting part, 2,22...
...Insulating substrate, 3,23...Signal line, 4,24...
Strip line, 5, 25... Josephson integrated circuit chip, 6... Inductance element, 7... Capacitance element, 8... Contact electrode, 11... Inductance 1.12... Capacitance, 13・・・
- Impedance, 14... Power supply, 15... Impedance on the chip, 16... Josephson integrated circuit chip portion, 17... Parasitic inductance of electrodes and wiring.

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に複数個のストリップ線路と、該ストリップ
線路と電気的に接続した複数個の電極とを形成したチッ
プホルダーにおいて、前記ストリップ線路と前記電極と
の間にインダクタンスとキャパシタンスよりなる受動素
子を接続したことを特徴とするジョセフソン集積回路用
チップホルダー。
In a chip holder in which a plurality of strip lines and a plurality of electrodes electrically connected to the strip lines are formed on an insulating substrate, a passive element consisting of an inductance and a capacitance is provided between the strip line and the electrode. A chip holder for a Josephson integrated circuit, characterized by a connection.
JP280489A 1989-01-11 1989-01-11 Chip holder for josephson integrated circuit Pending JPH02184086A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP280489A JPH02184086A (en) 1989-01-11 1989-01-11 Chip holder for josephson integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP280489A JPH02184086A (en) 1989-01-11 1989-01-11 Chip holder for josephson integrated circuit

Publications (1)

Publication Number Publication Date
JPH02184086A true JPH02184086A (en) 1990-07-18

Family

ID=11539568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP280489A Pending JPH02184086A (en) 1989-01-11 1989-01-11 Chip holder for josephson integrated circuit

Country Status (1)

Country Link
JP (1) JPH02184086A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170777A (en) * 2008-01-18 2009-07-30 National Institute Of Advanced Industrial & Technology Programmable josephson voltage standard apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63280506A (en) * 1987-05-12 1988-11-17 Hitachi Cable Ltd Method for connecting circuit wiring of superconductor and element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63280506A (en) * 1987-05-12 1988-11-17 Hitachi Cable Ltd Method for connecting circuit wiring of superconductor and element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170777A (en) * 2008-01-18 2009-07-30 National Institute Of Advanced Industrial & Technology Programmable josephson voltage standard apparatus

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