JPH02183614A - Adaptive type waveform equalizer - Google Patents

Abstract

PURPOSE:To always attain sufficient waveform equalization even if a signal being the result of applying time division multiplex to plural channel signals by storing plural tap coefficients corresponding to each of the plural channel signals and outputting the tap coefficient corresponding to the channel signal represented by a discrimination signal. CONSTITUTION:At the point of time when a tap coefficient corresponding to the m-th channel signal being part of the input signal subject to time division multiplex is calculated, when the input signal is switched to the n-th channel signal, a tap coefficient of a coefficient revision circuit 3 at that point of time is stored in a storage means corresponding to the m-th channel signal of a coefficient storage circuit 4 by using the discrimination signal. Simultaneously, the tap coefficient stored in the storage means corresponding to the n-th channel signal is written in the coefficient revision circuit 3, which restarts the calculation of the coefficient by using the tap coefficient as the initial value. The operation above is implemented every time the switching of the channel signal is caused. Thus, each channel signal is subject to adaptive equalizer with respect to a signal of applying time division multiplex to the plural channel signals.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an adaptive waveform equalizer used for waveform equalization in digital signal processing and the like.

BACKGROUND OF THE INVENTION In recent years, there has been an increasing need to transmit high-frequency digital signals. To achieve this, an adaptive waveform equalizer is known that automatically equalizes waveform distortion occurring in a transmission path. A typical example is shown in FIG.

In FIG. 2, the coefficient updating circuit 3 calculates optimal tap coefficients based on the distortion-containing signal applied to the input terminal 23 and the output signal appearing at the output terminal 24, and calculates the optimum tap coefficients for the transversal filter 2! Tap 25.2G.

Set to 27.

As an application example of the adaptive waveform equalization configured as described above, a rotary head digital tape recorder (R-DA
There is T) equalization processing of recording and reproduction signals.

FIG. 3 shows a block diagram of a transmission system for recording and reproducing signals of the R-DAT.

In R-DAT, digital signals are recorded and reproduced on a magnetic tape 303 by an A head 322 and a B head 312 mounted on a rotating head drum (not shown). The recording head changeover switch 30 is activated during recording by the channel switching determination signal applied to the determination signal input terminal 31B.
2, the A head 322 is rotated every half rotation of the rotating head drum.
side and the B head 312 side alternately. Similarly, during reproduction, the head changeover switch 304 alternately switches between the A head 322 side and the B head 312 side every half rotation of the rotary head drum. The signal recorded by the A head 322 is reproduced by the A head 322, and the signal recorded by the B head 312 is reproduced by the B head 312.

That is, the digital signal generated by the signal processing circuit 307 is recorded on the magnetic tape 303 and then reproduced.

Then, the reproduced signal is transmitted to the transmission line 32 on the A side of the Rad 322.
The signal is obtained by time-division multiplexing the channel signal that has passed through the transmission path 324 on the B head 312 side and the channel signal that has passed through the transmission path 324 on the B head 312 side. Such a signal will be supplied to the adaptive waveform equalizer 305 shown in FIG.

Problems to be Solved by the Invention As described above, when trying to equalize a signal obtained by time-division multiplexing of multiple channel signals using an adaptive waveform equalizer, a coefficient update circuit that calculates the tap coefficients of the adaptive waveform equalizer is required. 3 is
Since it operates without distinguishing between the channel signals that make up the time-division multiplexed signal, optimal tap coefficients cannot be obtained and waveform equalization becomes insufficient. Furthermore, if the characteristics of each channel signal are far apart, or if the time-division multiplexing period is short, the adaptive waveform equalizer may not be able to converge on any channel signal. Since the adaptive waveform equalizer switches to the next channel signal, it does not converge and waveform equalization becomes impossible.

The present invention has been made in view of the above, and an object of the present invention is to provide an adaptive waveform equalizer that can always perform sufficient waveform equalization even when a signal obtained by time-division multiplexing of a plurality of channel signals is provided. .

Means for Solving the Problems In order to solve the above problems, the invention of claim 1 of the present application is provided with an input signal obtained by time-division multiplexing of a plurality of channel signals and a discrimination signal indicating the distinction of the channel signals. The adaptive waveform equalizer includes a transversal filter that is given tap coefficients and equalizes the input signal, and a transversal filter that stores a plurality of tap coefficients corresponding to each of a plurality of channel signals, a coefficient storage circuit that outputs a tap coefficient corresponding to the channel signal indicated by the discrimination signal; and a coefficient storage circuit that uses the tap coefficient output of the coefficient storage circuit as an initial value and sets the tap coefficient corresponding to the input signal and the output of the transversal filter. and a coefficient update circuit that updates the tap coefficients and outputs the tap coefficients to the transversal filter.

Further, in the invention of claim 2 of the present application, the coefficient storage circuit has an address for storing tap coefficients corresponding to each channel of the input signal, and the tap coefficients immediately before the discrimination signal is switched are indicated in the discrimination signal. The data is stored at the specified address.

Furthermore, in the invention according to claim 3 of the present application, the discrimination signal indicates when the channel signal is switched, and the coefficient storage circuit stores the tap coefficient input according to the discrimination signal and simultaneously outputs the stored contents. It is composed of the same number of storage means as the number of signals connected in series.

Effect The invention according to claims 1 to 3 of the present application has the above-described configuration, so that when the tap coefficient corresponding to the m-th channel signal constituting the time-division multiplexed input signal is being calculated, the input signal is When switching to the channel signal, the tap coefficient of the coefficient changing circuit at that time is stored in the coefficient storage circuit at an address corresponding to the above-mentioned ①th channel signal or in the storage means according to the discrimination signal. At the same time, the address corresponding to the n-th channel signal or the tap coefficient stored in the storage means is written into the coefficient updating circuit, and the coefficient updating circuit restarts calculation of coefficients using the tap coefficient as an initial value. The above operations are performed every time a channel signal is switched, and the coefficient update circuit operates in time division in synchronization with the channel signal switch. Therefore, the setting operation is performed so that the optimal tap coefficients are set for each channel signal, and each channel signal is sufficiently equalized.

EXAMPLE Hereinafter, the present invention will be explained in detail based on an example of the present invention. FIG. 1 shows an example of the adaptive waveform equalization amount of the present invention, in which a signal obtained by alternately time-division multiplexing a first channel signal a and a second channel signal A is adaptively equalized. This is an example. In FIG. 1, the first stage storage means 1.2
A coefficient storage circuit 4 is constructed by connecting the storage means 2 of each stage in series.

If the storage means 1 and 2 are, for example, flip-flops whose number corresponds to the tap coefficients, the coefficient storage circuit 4 becomes a shift register. 3 is a coefficient update circuit; 31 is an input terminal for an input signal obtained by time-division multiplexing of the first channel signal a and the second channel signal A; 12 is a transversal filter having the same configuration as that shown in FIG. 2; is an output terminal, and 1G is an input terminal for a determination signal SO for determining the channel switching state. Reference numeral 15 denotes a clock supply circuit that provides a load command S3 and a clock S2 to the coefficient update circuit 3 and coefficient storage circuit 4, respectively, based on this input signal. The coefficient update circuit 3 includes an up-down counter that can increase or decrease the tap coefficient 56, and means for controlling the up-down counter from the input and output of the transversal filter 12. FIG. 4 shows an example of the configuration of the coefficient update circuit.

In FIG. 4, the control means 41 calculates the correlation between the input and output of the transversal filter 12, and sends a control signal to the up/down counter 42 indicating whether it is a hair-cut count or a down count.

The up/down counter 42 indicates that the load discussion S3 is “H”.
When it becomes II, the input data S5 is received. Then, the tap coefficient 56 is updated by up-counting or down-counting and outputting the value of S5 using the control signal from the control means 41 described above.

When the number of taps of the transversal filter 12 is N, it is sufficient to prepare N pieces of the configuration shown in FIG. 4 for each tap.

5 is a timing chart for explaining the operation of FIG. 1, and shows the timing of each signal in FIG. 1. In FIG. 5, the input signal is the first channel signal a1 from time to to t5 and from t9 to t13.
The period from time t5 to t9 is the second channel signal, and this input signal is input to the input terminal 31. The discrimination signal SO applied to the discrimination signal input terminal IB is "11" and "11" corresponding to the above-mentioned channel signals a and b.
S2 is an operation clock of the shift register constituting the coefficient storage circuit 4, and is given from the clock supply circuit 15 based on the discrimination signal SO. The load command S3 is given by the clock supply circuit I5 based on the discrimination signal SO. Since S2 and S3 are both pulse signals synchronized with SO, the clock supply circuit 15 can be easily configured using a shift register and simple logic. Furthermore, S4 is the output of the flip-flop that constitutes the first stage storage means 1, and S5 is the output of the flip-flop that constitutes the second stage storage means 2.SO is the coefficient update circuit 3.
This is the output of the up/down counter that constitutes the , that is, the tap coefficient. Further, St is an operation control signal (not shown in FIG. 1) of the coefficient update circuit 3, and the coefficient update circuit 3 is
When S1="H", tap coefficients are increased/decreased (updated) from the input and output of the transversal filter 12. In this example, this can be easily achieved by selecting the up/down counter 42 of the coefficient update circuit 3 to be enabled or disabled.

Next, the operation will be explained using FIGS. 1 and 5. Now, consider time t1 in FIG. SO is “11”
Therefore, the first channel signal a is input to the transversal filter 12. Output S4 of first stage storage means 1
is B, and the output S5 of the 12th stage storage means 2 is A.

Further, the output S6 of the coefficient update circuit 3 is A. Therefore, the first
Channel signal a has a tap coefficient of fixed value A. The signal passes through the transversal filter 12 and is output to the output terminal I3.

After that, during Δt from time t2 to t3, the operation control signal St of the coefficient update circuit 3 becomes IIHll, and the up/down counter forming the coefficient update circuit 3 becomes capable of counting. Therefore, the tap coefficient 56 increases or decreases depending on the input and output of the transversal filter 12. In other words, during this time,
Adaptive equalization processing is performed on the first channel signal a. After that, when t3 is reached, Sl becomes "off" and the tap coefficient A at that point. .

It is fixed at 1.

Later, when the clock S2 rises at time t4, the shift register constituting the coefficient storage circuit 4 shifts by one stage, and the output S4 of the first stage storage means 1 is the tap coefficient Sl at that time.
j:A. 1, and the output S5 of the second stage storage means 2 becomes the output S4:B of the first stage storage means.

Later, at time t5, when SO becomes 'L' and the input signal is switched to the second channel signal, the coefficient load command S3 is given from the clock supply circuit 15 to the coefficient update circuit 3, and the second stage storage means 2 The output 55=B of is written to the coefficient update circuit 3. From this, the output S6 of the coefficient update circuit 3 becomes Bn, and thereafter until reaching time t6, S6 is written to the coefficient update circuit 3.
Since l is L, the tap coefficient 56 is fixed at Bn, and therefore, during this period, the second channel signal or tap coefficient is outputted to the output terminal 13 through the transversal filter 12 having a fixed value B, .

After this, the operation is similar to the above tl-t5 until time t9 when the input signal switches to the first channel signal a again,
Immediately before time t3, the output S4 of the first stage storage means 1 is the current tap coefficient 56=B, -+, and the output S5 of the second stage storage means 2 is An4. It is. Here, A
l141 is the tap coefficient 56 for the first channel signal a stored in the first stage storage means 1 at time t4.

Therefore, when time t3 arrives, this person. 4+ is written to the coefficient update circuit 3. That is, while the adaptive equalization process was being performed on the second channel signal a from time t5 to t9, the tap coefficient Ana1 for the first channel signal a was stored in the coefficient storage circuit 4, and from time t9 When the input signal is switched to the first channel signal a again, the adaptive equalization process is restarted using the stored tap coefficient 16+1.

Similarly, while the adaptive equalization process is being performed on the first channel signal a from time t9 to t13, the coefficient storage circuit 4 stores tap coefficients Bn, , for the second channel signal a, When the input signal is switched again to the second channel signal at time t13, the adaptive equalization process is restarted using the stored tap coefficients Bfi, I.

As a result, the first channel signal a is adaptively equalized by the tap coefficients (Afl, , ) corresponding to the first channel signal a, and the second channel signal a is adaptively equalized by the tap coefficients (Afl, , ) corresponding to the second channel signal a. Adaptive equalization processing is performed in (Bn.,). The above operations are repeated to increase/decrease the tap coefficients in a time-division manner corresponding to each of the first channel signal a and the second channel signal.

The example explained above is a case where there are two channel signals, but if the order in which the channel signals are switched is constant, even when there are two or more n channel signals, the storage means constituting the coefficient storage circuit 4 can be This can be easily achieved by connecting the two in series.

Further, as shown in FIG. 6, a RAM is used as the coefficient storage circuit 4.
By specifying the discrimination signal SO, which indicates the distinction between channel signals, as an address, this can be realized even when the order in which the channel signals are switched is indefinite. Also,
In the above example, the coefficient storage circuit stores the tap coefficients adaptively updated by the coefficient update circuit, but if the switching period of the channel signal is longer than the time for the update operation to converge, the coefficient storage circuit stores a fixed value tap coefficient. As described in detail, according to the present invention, it is possible to adaptively equalize a signal obtained by time division multiplexing multiple channel signals for each channel signal. Accurate equalization processing can be achieved. Furthermore, since only one transversal filter and one coefficient update circuit are required regardless of the number of channel signals, adaptive waveform equalization can be provided with a very small circuit scale and low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an adaptive waveform equalizer according to an embodiment of the present invention, FIG. 2 is a block diagram of an example of a conventional adaptive waveform equalizer, and FIG. 3 is a block diagram of an R-DAT recording/reproducing signal. 4 is a block diagram showing a configuration example of a coefficient update circuit, FIG. 5 is a timing chart of an adaptive waveform equalizer according to an embodiment of the present invention, and FIG. 6 is a block diagram showing a configuration example of a coefficient update circuit. FIG. 2 is a block diagram illustrating an adaptive waveform equalizer in another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... First stage storage means, 2... Second stage storage means, 3... Coefficient update circuit, 4... Coefficient storage circuit, 12... Transversal filter, 1
3... Equalized signal output terminal, 14... Changeover switch, 15... Clock supply circuit, 16
. . . Input terminal for discrimination signal, 31 . . . Input terminal for equalizing signal, 41 . . . Control means, 42 . . . Up/down counter. Name of agent: Patent attorney Shigetaka Awano and 1 other person 3l--
XR1? ':j! j4 8-F n + Figure 2 Figure Transformer 8'-°Suru

Claims (3)

[Claims] (1) An input signal obtained by time-division multiplexing of a plurality of channel signals and a discrimination signal indicating the distinction of the channel signals are provided,
An adaptive waveform equalizer that equalizes the waveform of each channel signal, which is provided with tap coefficients and stores a transversal filter that equalizes the input signal and a plurality of tap coefficients corresponding to each of the plurality of channel signals. At the same time, a coefficient storage circuit outputs a tap coefficient corresponding to the channel signal indicated by the discrimination signal, and the tap coefficient output of the coefficient storage circuit is set as an initial value, and the tap coefficient is determined by the input signal and the output of the transversal filter. an adaptive waveform equalizer, comprising: a coefficient update circuit that updates the tap coefficients in accordance with the tap coefficients, and outputs the tap coefficients to the transversal filter. (2) The coefficient storage circuit has an address for storing tap coefficients corresponding to each channel of the input signal, and is configured to store the tap coefficient immediately before the discrimination signal is switched at the address indicated in the discrimination signal. 2. The adaptive waveform equalizer according to claim 1. (3) The discrimination signal indicates when the channel signal is switched, and the coefficient storage circuit stores registers in series for the number of channel signals, which store the tap coefficient input according to the discrimination signal and simultaneously output the stored contents. 2. An adaptive waveform equalizer according to claim 1, further comprising connected storage means.