JP3111671B2 - Television signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal processing apparatus, and more particularly to a television signal processing apparatus which can input a television signal having an aspect ratio different from that of a general television signal. The present invention relates to a television signal processing device for converting a display format according to an identification signal multiplexed on a television signal.

[0002]

2. Description of the Related Art The current standard television system, NT
In addition to the SC, many high-definition television systems that reproduce high-definition and realistic sounds and images have been proposed in the United States and Europe, as well as in Japan, and are being put to practical use. This high-definition television system is compatible with the current system so that it can be viewed on a receiver of the standard television system that is already widespread, and uses an adapter type converter to maintain compatibility Various methods such as a method have been proposed.

In Japan, in particular, the MUSE system and the ED
The TV-II system is dominant, the former is not compatible with the current system, but is a system that maintains compatibility using a converter, and the latter is a system that considers compatibility with the current system. The common feature of both systems is that the aspect ratio of the reproduced image is 16: 9, which is wider than that of the current system.

On the other hand, when the aspect ratio of the input video signal changes, the receiver switches the signal processing method in accordance with the change, and displays an optimum reproduced image according to the aspect ratio of the display provided in the receiver. There is a need to.
For example, NTSC signals (normal video signals having an aspect ratio of 4: 3), EDTV-II signals (letter-box format video signals), and squeeze format video signals output from a MUSE / NTSC down converter are used as input signals. Assuming that the aspect ratio of the display provided in the receiver is 16: 9, an example will be described with reference to FIG.

FIG. 2 is a diagram showing a form of an input signal and a form of display of an output signal. When the aspect ratio of the receiver is 16: 9, when an NTSC signal is input (FIG. 2, a-1), an empty area on the left and right sides of the screen caused by the difference in the aspect ratio is taken into consideration, and JP-A-1-194784 is disclosed. As shown in (1), a video signal is read out using a line memory or the like at a speed higher than the writing speed to perform left-right compression processing, thereby reproducing an image in the form shown in (c-1 in FIG. 2).

Also, an EDTV-II signal, that is, a letter box.
When a video signal of a format is input (FIG. 2, a-2), the technical report of the Institute of Television Engineers of Japan, BCS'90-28 (May, 199)
0) and Technical Report BCS'92-6 (Jan, 19
As shown in (92), the high-definition information multiplexed in the upper and lower free areas is decoded, and a high-quality wide aspect image is reproduced in the form shown in (c-2) of FIG. At this time, a method of simply reproducing a wide aspect image by expanding the input signal in the vertical direction by a line interpolation process or the like is also conceivable.

Further, when a squeeze-type video signal is input (FIG. 2, a-3), it is displayed as it is (FIG. 2, c-
The wide aspect image shown in 3) is reproduced. On the other hand, when the aspect ratio of the receiver is 4: 3 and the above input signal is processed, the letter B is input only when a squeeze format video signal is input.
It is necessary to convert to an ox format video signal and display it.

As described above, in order to switch the signal processing according to various types of input signals, an identification signal for automatically determining the type of the input signal is required. For this reason, for example, JP-B-51-1724 and JP-A-60-16588
As disclosed in, for example, Japanese Unexamined Patent Publication No. 3 (1994), a discrimination signal for discriminating an aspect ratio of a display image is multiplexed with a video signal to be transmitted, and the discrimination signal is detected on the receiver side to switch signal processing. There is a technology that can display the most effective converted image without bothering the viewer.

[0009]

The above prior art is a technique for multiplexing an identification signal in a video signal other than a display period such as a horizontal blanking period and a vertical blanking period. In the ideal case, it was the preferred technique.

However, when recording and reproducing a video signal on which the identification signal is multiplexed by a VTR or the like, the identification signal is lost due to repeated dubbing or the like, or during special reproduction (fast forward, rewind, still, etc.). ) Lacked consideration for problems such as a missing identification signal.

Similarly, input (arriving) during special display (freeze (still), strobe, multi-channel (hereinafter referred to as multi-channel), etc.) on the receiver side.
When the display mode of the signal changes, the identification signal also changes at the same time, so that there is no consideration for problems such as erroneous signal processing of the special display screen.

As described above, in the case where the multiplexed identification signal is lost or the display form of the input (arrival) signal changes during the special display, in the above-described conventional example, FIG. 2, c-1, 2, 3 The display form that should be displayed as shown in FIG.
However, there is a problem that the display form is erroneously converted into a display form as shown in FIG.

The present invention has been made in view of the above problems. Accordingly, a first object of the present invention is to provide a television signal processing apparatus capable of solving the problem that the display mode is suddenly switched even if the multiplexed identification signal is lost as described above. It is to provide a device.

A second object of the present invention is to control detected identification signal data so that optimal signal processing can be performed even when the display form of an input (arrival) signal changes during the special display. It is an object of the present invention to provide a television signal processing device capable of performing the above.

[0015]

In order to achieve the first object, according to the present invention, predetermined signal processing is performed on an input video signal, and at least a video signal of a standard television system or a video of a double-speed television system is processed. Video signal processing means for generating a signal; synchronous detection means for reproducing a synchronous signal from the input signal and outputting a synchronous / asynchronous signal indicating a synchronous state and an asynchronous state at the same time; and a display format identification multiplexed from the input signal An identification signal detecting means for detecting a signal, judging the presence or absence of the identification signal and outputting the same at the same time as outputting the identification signal data, and inputting an output signal of the identification signal detecting means and a synchronous / asynchronous signal output from the synchronous detecting means. Then, when asynchronous, fixed identification signal (fixed mode) data is output. On the contrary, when synchronous, the holding time differs according to the presence or absence of identification signal multiplexing. Identification signal control means for outputting identification signal (display mode) data, and an aspect ratio for inputting an output signal of the video signal processing means and performing an aspect ratio conversion process in accordance with the identification signal data output from the identification signal control means. At least conversion processing means.

In order to achieve the second object, according to the present invention, predetermined signal processing is performed on an input video signal,
Video signal processing means for creating at least a video signal of a standard television system or a video signal of a double-speed television system, identification signal detection means for detecting a display format identification signal multiplexed from the input signal and outputting identification signal data, A special mode detecting means for detecting that the state of the input signal has shifted to the special mode and outputting the signal, and a special display of the identification signal data output from the identification signal detecting means in accordance with a detection signal obtained from the special mode detecting means. During the processing period, a special mode hold means for holding and outputting the immediately preceding identification signal (display mode) data, and an output signal of the video signal processing means are inputted and according to the identification signal data output from the special mode hold means. At least an aspect ratio conversion unit for performing an aspect ratio conversion process is provided.

[0017]

The identification signal control means receives the identification signal data output from the identification signal detection means, and additionally outputs a signal which determines the presence or absence of the identification signal output from the identification signal detection means;
By using a synchronous / asynchronous signal output from the synchronous detection means as a control signal, a fixed identification signal (fixed mode) data is output at the time of asynchronous operation, and conversely, at the time of synchronization, held according to the presence or absence of multiplexing of the identification signal It operates so as to switch and output the identification signal (display mode) data having different times.

As a result, it is possible to solve the problem that the display mode is suddenly switched even when the identification signal is lost.

Further, the special mode detecting means detects that the state of the input signal has shifted to the special mode and outputs the same, and the special mode hold means further outputs the special mode according to the detection output immediately before the special display processing period. Operates to hold the identification signal (display mode) data.

As a result, even if the display mode of the input (arrival) signal changes during the special display, the signal processing of the display image is not erroneously performed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. In the description of this embodiment, a standard television signal having an aspect ratio of a reproduced image of 4: 3 is used as a standard television signal.
The SC signal is converted into a MUSE signal and an EDTV-
This will be described by taking the II signal as an example.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 101 is an input terminal, 102 is a video signal processing circuit, 103 is an aspect ratio conversion processing circuit,
104 is a display having an aspect ratio of 16: 9, and 105 is a display.
Is an identification signal detection circuit, 106 is an identification signal control circuit, 10
7 is a synchronization detection circuit, 108 is a special mode detection circuit, 10
9 is a fixed mode setting circuit, 110 is identification signal coincidence detection &
Hold circuit, 111 is L field hold (hold)
Circuit, 112 is a selection circuit, 113 is a hold (hold) circuit, and 114 is a special code input terminal.

A major feature of the present invention lies in the configuration and operation of the identification signal control circuit shown in the signal processing block 106. Here, a logic for solving the above problem is configured using signals input from the identification signal detection circuit 105, the synchronization detection circuit 107, and the special mode detection circuit 108. Before describing the operation of the identification signal processing circuit 106, the operation of the peripheral circuit will be described.

An input terminal 101 receives an NTSC signal or M
The USE signal or the EDTV-II signal is input to the video signal processing circuit 102, the identification signal detection circuit 105, the synchronization detection circuit 107, and the special mode detection circuit 108.

When an NTSC signal, for example, is input from the input terminal 101, the video signal processing circuit 102 operates as a “NHK color television textbook [upper], [lower]” edited by the Japan Broadcasting Corporation.
And TV technology, February 1989, pp19-pp42, “Special Features: Basics of Clear Vision and Corresponding Technologies”, etc. are performed to create standard television video signals and double-speed television video signals. Then, it outputs to the aspect ratio conversion processing circuit 103. In this case, since the video signal of the form shown in FIG. 2 (a-1) is input to the aspect ratio conversion processing circuit 103,
As disclosed in Japanese Patent Laid-Open Publication No. 4 (1994), a video signal is read out using a line memory or the like at a speed higher than a writing speed to perform left-right compression, thereby reproducing an image in a display form shown in (c-1, FIG. 2).

Also, from the input terminal 101, for example, EDT
When a V-II signal is input, the video signal processing circuit 102
Is the Technical Report of the Institute of Television Engineers of Japan BCS'90-28 (M
ay, 1990) and Technical Report BCS'92-6 of the same society.
(Jan, 1992) and the like,
The high-definition information is restored from the video signal in the form shown in FIG. 2A, and is converted into the video signal in the form shown in FIG. This video signal is input to the aspect ratio conversion processing circuit 103 and output (displayed) as it is, whereby an image in the display form shown in (c-2 in FIG. 2) is reproduced.
At this time, the video signal processing circuit 102 does not perform the normal signal processing as described above, but performs the same signal processing as that at the time of the NTSC signal input, so that the video signal in the form shown in FIG. May be input to the aspect ratio conversion processing circuit 103 and expanded in the vertical direction by line interpolation processing or the like to simply reproduce a wide aspect image. However, in this case, since the high-definition information is not reproduced, the image quality of the reproduced image is deteriorated.

Further, from the input terminal 101, for example, MU
When the SE signal is input, the video signal processing circuit 102
Is the Journal of the Institute of Television Engineers of Japan, Vol. 44 No.6 pp57
Pp64 (1990) and the journal of the same society, Vol. 45 No.
The signal processing described in 12 pp 1600 to 1602 (1991) is performed to generate a video signal of a standard television system and a video signal of a double-speed television system, and output the same to the aspect ratio conversion processing circuit 103. In this case, since the video signal in the form shown in (a-3 in FIG. 2) is input to the aspect ratio conversion processing circuit 103, it is output (displayed) as it is to display the image in the form shown in (c-3 in FIG. 2). Images can be played.

When special reproduction such as freeze, strobe, and multi-channel is performed by the video signal processing circuit 102, a code indicating that special reproduction is being performed is output to the special mode detection circuit 108.

As described above, the NTSC signal or the EDT of the form shown in FIG.
A V-II signal, a MUSE signal, and the like are input and converted into a standard television video signal and a double-speed television video signal by the video signal processing circuit 102, respectively. In response, desired signal processing is performed by the operation of the identification signal control circuit 106, and a display image in the form shown in FIG. 2 (c-1, 2, 3) is obtained.

However, when the identification signal multiplexed to determine the form of the input signal is lost for some reason, or when the form (display mode) of the input signal changes during special reproduction such as freeze, etc. As shown in FIGS. 2, d-1, 2, and 3, an expected reproduced image may not be obtained. Less than,
The operation of the signal processing circuit that solves the above problem will be described.

The synchronization detection circuit 107 detects a synchronization signal from the video signal obtained from the input terminal 101 and outputs it to the identification signal detection circuit 105. At the same time, the synchronization state where the video signal is input to the input terminal 101 or the absence of a signal A synchronous (low level “L”) / asynchronous (high level “H”) signal indicating an asynchronous state is created and output to the identification signal control circuit 106.

The identification signal detection circuit 105 extracts an identification signal multiplexed in the video signal input from the input terminal 101 based on the synchronization signal obtained from the synchronization detection circuit 107. FIG. 4 shows an example of the identification signal detection circuit 105, and shows an example of the identification signal output when the form of the input signal is only the three types shown in FIG. In this case, data of 2 bits is sufficient as the identification signal. In FIG. 4, the identification signal 1 is displayed in the letterbox display (FIG. 2, a-2), and the identification signal 2 is displayed in the squeeze display (FIG. 2, a-3). In the example shown in FIG. As a multiplexing method of the identification signal, besides the above-described conventional example, for example, the provisional standard (EI
AJ CPX-1202) As shown in “Identification Signals of Video Signals with Different Aspect Ratios and Transmission Method,”
Various schemes are conceivable, such as a scheme for multiplexing with a color difference separation type (Y / C separation type) video signal, and the configuration of the identification signal detection circuit 105 differs depending on the multiplexing scheme. However, this circuit is obvious to those skilled in the art, and the essence of the present invention does not change regardless of the form of the multiplexing system. For this reason, in the present embodiment, a case where the identification signal is multiplexed in the vertical blanking period will be described as an example.

In the identification signal detection circuit 105, the 2 bit
And min identification signal data, a clock signal latchable vertical synchronizing cycle of the data (hereinafter, referred to as f _V) and to create an identification signal Available (low level "L") / free (high level "H") signal Then, the signal is output to the identification signal control circuit 106.

The special mode detection circuit 108 is connected to the input terminal 1
01, a special reproduction code output from the video signal processing circuit 102, and a special reproduction code obtained from the input terminal 114. At the time of special reproduction, a low level "L" special reproduction identification signal is created and identified. The signal is output to the signal control circuit 106.

In order to identify the special reproduction from the video signal obtained from the input terminal 101, a method of detecting a change in the period (length) of the synchronizing signal (at the time of VTR special reproduction) or a motion detection of the video signal (at the time of freeze) There are various methods, such as a method of performing. For example, when fast-forwarding / rewinding a VTR, the cycle (length) of the synchronization signal changes. If the period of the regular synchronization signal is prepared as an internal reference signal, the special reproduction state can be easily detected by comparing with the synchronization signal for the special reproduction. In the case of a freeze (also called a still image (= image in a still image state)), since the entire screen is in a still state, it is supervised by the Technology Division of the Broadcasting Administration Bureau, Ministry of Posts and Telecommunications. By using the motion detection circuit described in “Clear Vision Handbook” edited by Clear Vision Promotion Council, it is possible to easily detect the freeze state.

The special reproduction code obtained from the input terminal 114 is, for example, a special reproduction code transmitted from a remote controller or the like, or, in the case of a VTR integrated receiver, a special reproduction code directly from a VTR control microcomputer. And the like. For example, when a special display is performed as a function of the TV receiver itself, the special reproduction must be performed directly from a special reproduction code oscillated from a remote controller or the like or a built-in microcomputer that generates a control signal based on the special reproduction code. Can be detected. Further, in the case of a VTR-integrated receiver, similarly, at the time of VTR special reproduction, the VTR control microcomputer can directly detect the special reproduction.

In the identification signal control circuit 106, the synchronization
An identification signal data output is controlled using the (L) / asynchronous (H) signal, the clock signal f _V , the identification signal presence (L) / absence (H) signal, and the trick play identification signal. About this operation, FIG.
This will be described with reference to FIGS. 6, 7, 8, and 9.

FIG. 5 is a detailed block diagram of the identification signal control circuit 106. Components denoted by the same reference numerals as those in FIG.
It is a component that performs the same operation as. In FIG. 5, 50
1 is an inter-field match detection circuit, 502 is an N field hold circuit, 503 is an M field hold circuit, 5
04,505,506 selection circuit, 507 denotes a flip-flop, the gate circuit 508, the identification signal data input terminal 509, the clock signal f _V input terminal 510, 511 identification signal Yes (L) / No (H) signal Input terminal 512 is synchronous
An (L) / asynchronous (H) signal input terminal 513 is a special reproduction identification signal (L during special reproduction) input terminal, and 514 is an output terminal. FIG. 9 is an example of a time chart used for explaining the operation of FIG.

In FIG. 5, an inter-field match detection circuit 501 receives identification signal data from an input terminal 509 and a clock signal f _V from an input terminal 510, and outputs identification signal data between fields, that is, at 1/60 second intervals. Find a match for.

FIG. 6 shows an example of a specific circuit of the inter-field coincidence detecting circuit 501 of FIG. 5. Components designated by the same reference numerals as those in FIG. I do. In FIG. 6, reference numeral 601 denotes a flip-flop;
02 is an EOR gate, 603 is an AND gate, and 604 is an output terminal. In this embodiment, 2 is used as the identification signal data.
bit, so flip-flop 601, EO
Two R gates 602 are required, and the AND gate 603 is a two-input AND gate. As a matter of course, when the input signal has a plurality of bits (N bits), N flip-flops 601 and EOR gates 602 are required, and the AND gate 603 is an N-input AND gate.

The identification signal data input to the flip-flop 601 is latched by the clock signal f _V and input to the EOR gate 602 as identification signal data of the opposite polarity delayed by one field. The EOR gate 602 receives the incoming identification signal data and the identification signal data of the opposite polarity delayed by one field. Therefore, as an output signal, a high level "H" is output when data matches between fields, and a low level "L" is output when data does not match. The comparison result is input to the AND gate 603, and the high level “H” is set only when all the bits match.
Is output. Next, the N-field hold circuit 502 and the M-field hold circuit 503 controlled using the inter-field match detection output will be described.

In FIG. 5, an N-field hold circuit 502 and an M-field hold circuit 503 output identification signal data from an input terminal 509, a clock signal f _V from an input terminal 510, and a detection output of the inter-field coincidence detection circuit 501. Is input, and the identification signal data is held for a certain period (N or M fields).

FIG. 7 shows an example of a specific circuit of the N-field hold circuit 502 and the M-field hold circuit 503 of FIG. 5, and the parts denoted by the same reference numerals as those of FIGS. , And perform the same operations as those in FIG. 7, reference numeral 701 denotes an N or M-bit shift register, 702 denotes a two-input AND gate, 703 denotes a flip-flop, and 704 denotes an output terminal. In the same manner as above, the required number of flip-flops 703 is
It changes with the number of bits. Further, the shift register 701
Requires (N-1) bits when shifting by N bits, and (M-1) bits when shifting by M bits.

The shift register 701 receives, as a reset signal, the detection output of the inter-field match detection circuit 501 and the clock signal f _V , and keeps a constant (N or M fields) period after the identification signal does not match between the fields. The low level “L” is output and input to the AND gate 702. This signal and the clock signal f _V are gated by the AND gate 702, and the clock signal is stopped for a certain period (N or M fields) after the identification signal does not match between the fields. The output signal of the AND gate 702 is input to the flip-flop 703 as a clock signal. Therefore, the identification signal data input to the flip-flop 703 is immediately preceding data, that is, data for a fixed (N or M fields) period after the identification signal becomes inconsistent between fields due to the clock signal output from the AND gate 702. , The identification signal data immediately before the mismatch between the fields is held.

In this embodiment, the fixed mode setting circuit 109 outputs 2-bit data (L, L) as shown in FIG. 4 as identification signal data.

The identification signal data processed as described above is
The signal is input to the selection circuit 112 and is selectively output by various control signals.

Among the control signals input to the selection circuit 112, the control signal output from the L field hold circuit 111 is an identification signal input (L) / no input from the input terminal 511.
(H) It is processed by the signal. Here, FIG. 8 corresponds to L in FIG.
This is an example of a specific circuit of the field hold circuit 111, and components denoted by the same reference numerals as those in FIGS. 1 and 5 are components that perform the same operations as those in FIGS. In FIG. 8, 8
01 is an L-bit shift register.

The shift register 801 receives an identification signal presence (L) / no (H) signal as a reset signal, and a clock signal f _V , and a fixed (L field) period after the identification signal presence (L). The low level “L” is output and input to the selection circuit 112.

The operation of the selection circuit 112 will be described with reference to FIG. 9 based on the operation of each block. Also,
L = M = 5 fields, N = 2 for easy understanding of the drawing
The field will be described below.

In FIG. 9, is the expected value of the identification signal data (corresponding to the identification signal 1 in FIG. 4). The timing of switching from the letter box mode to the squeeze mode is the arrival of the identification signal when the identification signal data is partially lost. Data is an output signal of the inter-field match detection circuit 501;
Is the identification signal data output from the N field hold circuit 502, is the identification signal data output from the M field hold circuit 503, is the identification signal presence (L) / absence (H) signal, and is the identification signal data output from the selection circuit 505. It is.

When an incoming signal as shown in FIG. 9 is input, an inter-field coincidence detecting circuit 501 detects coincidence of identification signal data between fields and outputs a signal having the waveform shown in FIG. In response, the N field hold circuit 502 and the M field hold circuit 503 respectively
As shown in (1) and (2), the identification signal data immediately before the mismatch between the fields is held and output for a certain period.

The selection circuit 504 is a selection circuit for coping with a sudden loss of identification signal data. Selection circuit 5
The identification signal data output from the fixed mode setting circuit 109 and the M field hold circuit 503 is input to 04, and is selectively output by the control signal output from the L field hold circuit 111. The selection circuit 504 selectively outputs the b side when the control signal is “Low”, and outputs the a side when the control signal is “H”. In this embodiment, since L = M = 5,
If the loss of the identification signal data is within 5 fields, the control signal becomes "L", and the output signal data of the selection circuit 504 can obtain the identification signal data in which the loss is compensated as shown in FIG. 5 missing identification signal data
If it is equal to or more than the field, the control signal becomes "H" and the identification signal data is fixed to the 4: 3 mode. This is to cope with a video signal in which identification signal data is not multiplexed.

Here, for example, if the noise level contained in the input signal is large and the values of L and M are too small, the identification signal data may be frequently lost. Therefore, the set values of L and M when the noise level is high are set larger than L and M when the noise level of the input signal is low. For example, the set values of L and M in the standard time are set to K2
(= 10, etc.), L and M when the noise level is low are Ls and Ms, and L and M when the noise level is high are Lb and Mb, and (Mb, Lb) ≧ K1 ≧
(Ms, Ls) is set.

If the set values of L and M are too large at the time of channel switching or the like, regardless of the level of the noise level, it takes a long time for the video signal after channel switching to become an expected display image. turn into. Therefore, at the time of channel switching or the like, the set values of the above L and M are preferentially set to be smaller than those in the normal state.
For example the set value of L and M in a steady state and K2 (such as = 5), the L and M, such as hand-off L _ch and M _ch, When L and M the Lt and Mt of the steady, (L
(t, Mt) ≧ K1 ≧ (M _ch , L _ch ).

The selection circuit 505 is a selection circuit for immediately switching the identification signal data when the identification signal data is switched. The selection circuit 505 includes the selection circuit 5
04 and the identification signal data output from the N field hold circuit 502 are input, and the identification signal is present (L) shown in FIG.
/ No (H) signal is selectively output. Selection circuit 505
Selects and outputs the a side when the control signal is "L" and the b side when the control signal is "H". In this embodiment, since N = 2, N
The identification signal data output from the field hold circuit 502 switches immediately after two fields after the switching of the identification signal data as shown in FIG. At this time, if the identification signal is present “L”, the identification signal data can be immediately obtained as the output signal data of the selection circuit 505 as shown in FIG.

At this time, if the noise level of the input signal is large and the value of N is too large, the display mode may not be switched due to erroneous detection of the identification signal data. Therefore,
The set value of N when the noise level is high is set smaller than N when the noise level of the input signal is low. For example, if the set value of N in the standard time is K3 (= 4 or the like), N is Ns when the noise level is low, and Nb is N when the noise level is high, the relationship of Ns ≧ K3 ≧ Nb is satisfied. Set.

Furthermore, regardless of the level of the noise level, if the set value of N is too large at the time of channel switching or the like, the time required for the video signal after channel switching to become an expected display image becomes longer. I will. Therefore, in a predetermined period immediately after the channel switching, etc., the set value of N is preferentially set smaller than that in the normal state.
For example, if the set value of N in the steady state is K4 (= 2 or the like), N at the time of channel switching is N _ch , and N in the steady state is Nt, the relationship is (Nt) ≧ K4 ≧ (N _ch ). Set as follows.

If the identification signal is not "H", the selection circuit 505 selects and outputs the input signal data on the b side, that is, the identification signal data of the fixed mode setting circuit 109 output from the selection circuit 504. In this way, the selection circuit 505
Can output the identification signal data shown in FIG.

The various hold circuits 502, 5 described above
When the hold periods L, M, and N of 03, 111 are set to have a relationship of M ≧ L> N, it is strong against an identification signal omission (corresponding up to the L period), and immediately when the display mode is switched ( The operation is performed so that the display mode is switched after (N period).

The operation in the case where the identification signal data is suddenly lost and the operation when the identification signal is switched have been described above. The display is also performed when the input signal is out of synchronization, that is, when there is no signal. The mode must be set.

The selection circuit 506 performs synchronous (L) / asynchronous (H)
A selection circuit for selectively outputting identification signal data output from the fixed mode setting circuit 109 when a signal is used and the input signal is out of synchronization, that is, when there is no signal. The identification signal data output from the selection circuit 505 and the fixed mode setting circuit 109 is input to the selection circuit 506, and the synchronization signal (L)
/ Asynchronous (H) signal. Selection circuit 5
06 selects and outputs the b-side when the control signal is "L" and the a-side when the control signal is "H".

At present, the NTSC signal which is widely and generally used is a video signal having a display mode with a normal aspect ratio of 4: 3. Therefore, in the present embodiment, the configuration is such that the display mode is reset to the 4: 3 display mode when there is no signal (at the time of asynchronous operation). However, the situation has changed,
If signals other than the 4: 3 display mode become common,
A of the selection circuit 506 so as to be reset to the display mode.
It is necessary to change the input data setting on the side. When the display mode of the selected channel is known in advance, such as when the power is turned on, it is necessary to set the input data on the a side of the selection circuit 506 so that the display mode is reset.

The identification signal data subjected to the above processing is input to the hold circuit 113. Here, when the display mode is shifted from the normal display mode to the special mode display mode, the identification signal is controlled so that no trouble occurs.

A clock signal f _V is input from the input terminal 510 and a trick play identification signal is input from the input terminal 513 to the hold circuit 113 as control signals. AND
The gate 508 receives the above two types of control signals.
The AND gate 508 stops the clock signal f _V in the “L” state during the special reproduction, that is, when the special reproduction identification signal is “L”. Therefore, the flip-flop 507 which inputs the output of the AND gate 508 as a clock signal holds the identification signal data immediately before execution of the special reproduction at the time of the special reproduction. The identification signal data thus obtained is input to the aspect ratio conversion circuit 103.

By the above operation, even if the display mode of the incoming signal changes during special reproduction such as freeze, erroneous signal processing is not performed. However, among special playback, multi c
h (for example, a mode in which a screen is divided into nine, and video signals of different channels (different display modes) are displayed on the divided screens), etc., are displayed on the same screen. In this case, the special reproduction identification signal is set to “H”. This can prevent loss of video information due to erroneous signal processing at the time of multi-channel or the like. Further, for example, if the display mode setting is fixed to the 4: 3 display mode only in the multi-channel mode, the display can be understood at a glance of the broadcast mode of each channel.

The signal processing of the identification signal control circuit 106 described above is represented by a flowchart as shown in FIG. That is, the identification signal control circuit 106 shown in FIG.
Is realized by hardware. On the other hand, by using a microcomputer in which the flowchart of FIG. 3 is programmed (as software) and replacing it with the signal processing block of the identification signal control circuit 106, a control circuit that performs the same operation as in FIG. Blocks can be easily constructed as microcomputer controls.

As described above, the synchronous (L) / asynchronous (H) signal, the clock signal f _V , the identification signal presence (L) / absence (H) signal,
By using the special playback identification signal and controlling the identification signal data output, during the special mode, the display mode immediately before entering the special mode is retained, and it is displayed even if the display mode of the input signal is switched during the special display It is possible to prevent a display form error due to switching of the screen signal processing.

Further, when the identification signal is lost, the identification signal (display mode) immediately before the loss is retained for L periods, and when the display mode is switched due to the presence of the identification signal, the switching operation is performed immediately after N periods. Will be. L> N
In the case of the following relationship, the lack of the identification signal can be dealt with within the L period, and when the display mode is switched, the display mode is switched immediately after the N period. As a result, the display mode switching operation can be smoothly performed while solving the problem that the display mode is suddenly switched even when the identification signal is lost as in the conventional example.

In the above description, for simplification of the drawing,
Although the form of the input signal has been described as the above three types, the present invention is not limited to this. For example, in many cases, there are three or more types of input signals, such as a video signal of a movie size with an NTSC signal and a video signal subjected to MUSE / NTSC down-conversion processing. However, the present invention functions effectively regardless of the type of the input signal and the multiplexing method of the identification signal. Further, the essence of the present invention does not change even if the detection method is changed in the special mode detection circuit 108 and the identification signal detection circuit 105 according to the case where the format of the multiplexed identification signal is different.

[0070]

According to the present invention, in a device for processing and displaying a plurality of video signals having different display modes, the display mode is suddenly increased even if the identification signal multiplexed in the video signal is missing. This has the effect that the switching operation of the display mode can be smoothly performed while solving the problem of the switching of the display mode. Also,
In the special mode, the display mode immediately before entering the special mode is maintained, and even if the display mode of the input signal is switched during the special display, it is possible to prevent a display form error due to switching of the signal processing of the display screen. It has the effect.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating a display mode of the present invention.

FIG. 3 is a flowchart illustrating signal processing according to the present invention.

FIG. 4 is a diagram showing an identification signal data and identification signal detection circuit of the present invention.

FIG. 5 is a configuration diagram showing an identification signal control circuit of the present invention.

FIG. 6 is a configuration diagram showing an inter-field match detection circuit of the present invention.

FIG. 7 is a configuration diagram showing N and M field hold circuits of the present invention.

FIG. 8 is a configuration diagram showing an L field hold circuit of the present invention.

FIG. 9 is a timing chart illustrating signal processing according to the present invention.

[Explanation of symbols]

 Reference numeral 101: input terminal, 102: video signal processing circuit, 103: aspect ratio conversion processing circuit, 104: display, 105: identification signal detection circuit, 106: identification signal control circuit, 107: synchronization detection circuit, 108: special mode detection circuit 109: fixed mode setting circuit 110: inter-field match detection & hold circuit 111: L-field hold circuit 112: selection circuit 113: hold circuit 501: inter-field match detection circuit 502: N-field hold circuit 503: M field hold circuit, 504, 505, 506: selection circuit, 507: flip-flop, 508: AND gate, 509: identification signal data input terminal, 510, 511, 512, 513: control signal input terminal, 514: identification Signal data output terminal, 601 ... free Flop, 602 ... EOR gate, 603 ... the AND gates, 604 ... output terminal, 701 ... shift register, 702 ... the AND gates, 703 ... flip-flop, 704 ... output terminal, 801 ... shift register, 802 ... output terminal.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Kenji Katsumata, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Inside the Media Research Laboratory of Hitachi, Ltd. (72) Haruki Takada 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Inside Hitachi Media Co., Ltd. (72) Inventor Takaaki Matino 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Product Planning Division, AV Division, Hitachi, Ltd. (72) Takeshi Sakai, Yokohama-shi, Kanagawa 292 Yoshida-cho, Totsuka-ku, Hitachi, Ltd. AV Business Unit Product Planning Division (56) References JP-A-4-82486 (JP, A) JP-A-60-165883 (JP, A) JP-A-6- 14309 (JP, A) JP-A-63-146586 (JP, A) JP-A-61-88378 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/46

Claims (7)

(57) [Claims] An apparatus for detecting a display format identification signal multiplexed on a video signal to determine a form of an input signal, switching signal processing and performing display format conversion, and performing a predetermined signal processing on the input video signal. the performed, at least the standard television video signal processing means for generating a video signal of the video signal or speed television system John scheme, the show from the input signal and the synchronous state and an asynchronous state together to play a sync signal synchronous / asynchronous a synchronization detecting means for outputting a signal, an identification signal detecting means for outputting an identification signal data together when the detecting a multiplexed display format identification signal from an input signal and outputting the determined presence or absence of the identification signal, said identification signal An output signal of the detecting means and a synchronous / asynchronous signal output from the synchronous detecting means are input, and a fixed identification signal (fixed mode) Outputs, at the time of synchronization and identification signal control means for outputting an identification signal (display mode) data different retention times depending on the presence or absence of multiple identification signal, the identification before the output signal of said video signal processing means A television signal processing device comprising: an aspect ratio conversion processing unit that performs an aspect ratio conversion process according to identification signal data output from a signal control unit. 2. The television signal processing device according to claim 1,
Oite the location, the identification signal control means, the identification signal outputted from the detection means inputs the identification signal data, coincidence detecting detects whether the identification signal data matches with a constant time at a predetermined means and, using the output signal of the coincidence detection means, and N time holding means for holding period of N times of the plant constant time an identification signal data, using the output signal of the coincidence detection means, the predetermined identification signal data M period holding means for holding a period of M times the time, fixed mode setting means for outputting a fixed identification signal, and an identification signal presence / absence determination signal output from the identification signal detection means , The identification signal
L for holding the signal presence / absence determination signal for a period L times the predetermined time.
Period holding means, the N period holding means and the M
Identification signal data output from the period hold means and the fixed mode setting means, an output signal from the L period hold means, an identification signal presence / absence determination signal output from the identification signal detection means, and the synchronization detection means And a selecting means for selecting and outputting the identification signal data in accordance with a synchronous / asynchronous signal output from the television signal (where N, M, and L are constants represented by positive integers). Processing equipment. 3. The television signal processing device according to claim 2,
Oite the location, the N period hold means and the M period hold means and the constant N in the L period hold means,
A television signal processing apparatus, wherein M and L satisfy a relationship of M ≧ L> N. 4. The television signal processing device according to claim 2,
Oite the location, the constant in the N period holding unit N
Is a television signal processing device, wherein N is set to be larger when the noise level is low than N when the noise level is high according to the noise level of the input signal. 5. The television signal according to claim 2 or 4.
Oite the processor, the set value of the constant N in N periods hold means is compared with the setting value in the steady state reception, and sets smaller towards the predetermined time period immediately after the input signal switching (channel switching) Television signal processing device. 6. The television signal processing device according to claim 2,
Oite the location, the M period hold means and the constant M and L in the L period hold means, depending on the noise level of the input signal, than the M and L when the noise level large,
A television signal processing device, wherein M and L are set small when the noise level is low. 7. The television signal according to claim 2 or 6.
Oite the processor, the M period hold means and said L
A television signal processing apparatus, wherein the set values of the constants M and L in the period holding means are set smaller during a predetermined period immediately after the input signal switching (channel switching) than the set values at the time of steady reception.