JPH02183568A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase breakdown strength between a gate and a drain, and reduce ON-resistance by arranging an off-set low-concentration layer of the same conductivity type as a diffusion layer so as to be in contact with a second insulating layer and a drain diffusion layer, and to be separated from a first insulating layer and a source diffusion layer. CONSTITUTION:In a semiconductor layer forming a channel, an off-set low- concentration layer 17 of the same conductivity type as diffusion layers 14, 15 is arranged so as to be in contact with a second insulating layer 12 and the drain diffusion layer 15, and to be separated from a first insulating layer 11 used as a gate insulating film and the source diffusion layer 14. Since the off-set low-concentration layer 17 is separated from a gate electrode 16, breakdown between a gate and a drain can be prevented. Thereby, breakdown strength between a gate and a drain can be improved, and low ON-resistance can be realized, without complicating a process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device applied to a MOS FET that achieves high breakdown voltage and high performance.

In recent years, demands in fields such as display panel driving and mechatronics have required MOS FETs to have even higher breakdown voltages and lower on-resistance. For example, DC (or AC) is used to drive a plasma display.
) is required to withstand high voltage of 120 to 180V. It is also necessary to improve the on-resistance in the saturation region, and reducing the on-resistance can be achieved by simply increasing the chip size, but this goes against the demands for higher integration. Therefore, it is desired that both of the above requirements be met.

[Conventional technology]

An example of a conventional high-voltage FET of this type is one with a structure as shown in Figure 7 (offset type MO3FET).
It has been known. In the figure, 1 is a p-type silicon substrate, 2 is a LOCo S (Loco S) for element isolation, and 2 is a p-type silicon substrate.
xidization of 5ilicon) 'p
H region, 3 is a high concentration n-type source diffusion layer, 4 is a high concentration n-type drain diffusion layer 5 is an n-type offset low concentration layer, 6 is a gate oxide film, 7 is a gate electrode, 8 is an insulation layer membrane, 9
is a source electrode made of A2, and 10 is a drain electrode made of Al.

In an FET with such a configuration, the electric field in the channel region formed under the gate electrode 7 is changed by the voltage applied to the gate electrode 7 through the deposited gate oxide film 6, and this channel The current flowing between the source diffusion layer 3 and drain diffusion layer 4 at both ends of the passage region is controlled. In this case, the high voltage applied to the drain diffusion N4 is weakened through the offset low concentration layer 5, thereby preventing breakdown when high voltage is used. Furthermore, instead of simply separating the drain diffusion layer from the gate electrode, an offset low concentration layer 5 is interposed to reduce the on-resistance of the transistor.

[Problems to be Solved by the Invention] However, in the conventional MOSFET having such a structure, electric field concentration occurs at the portion indicated by ABC in FIG. 7 when using a high voltage.
On the other hand, electric field concentration at the 0 point can be effectively prevented by adopting the structure (licon on 1 nsulator) and by lowering the substrate concentration, but on the other hand, the offset low concentration layer 5
There was a problem in that it was not possible to effectively prevent electric field concentration at the tip of the gate, causing breakdown between the gate and drain.

On the other hand, in order to prevent electric field concentration at the 0 point, it is necessary, for example, to thicken the gate oxide film 6 or to lower the concentration of the offset low concentration N5, but both of these lead to an increase in the on-resistance of the transistor. Undesirable. Furthermore, in order to increase the thickness of the gate oxide film 6, it is conceivable to prepare, for example, two or more types of insulating films depending on the breakdown voltage, but this would complicate the manufacturing process and is not an effective solution.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can improve the breakdown voltage between the gate and drain and reduce the on-resistance without complicating the manufacturing process.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor layer of one conductivity type in which a channel path is formed between a first insulating layer and a second insulating layer, and an impurity of an opposite conductivity type is added to the semiconductor layer. a source diffusion layer and a drain diffusion layer are formed, the first insulating layer is used as a gate insulating film, and a gate electrode is provided so as not to overlap with the drain diffusion layer; An offset low-concentration layer of the same conductivity type as the first insulating layer and the source diffusion layer is provided in contact with the first insulating layer and the drain diffusion layer, and is separated from the first insulating layer and the source diffusion layer to form a field effect transistor. I am trying to configure it.

[Effect]

In the present invention, a semiconductor layer forming a channel path is in contact with both the second insulating layer and the drain diffusion layer, and is in contact with the first insulating layer and the source diffusion layer used as the gate insulating film. An offset low active layer having the same conductivity type as each of the diffusion layers is provided separately.

Therefore, the offset low concentration layer, which was conventionally located on the gate electrode side, is separated from the gate electrode, and breakdown between the gate and drain is prevented. Furthermore, by making the gate insulating film thinner, the on-resistance can be reduced, and the manufacturing process will not be complicated.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

First, a detailed explanation of the present invention will be given. FIG. 1 is a diagram showing the principle of the present invention, and is a cross-sectional view of a MOS FET. In FIG. 1, 11 is, for example, Sin.

12 is a second insulating layer made of, for example, SiO2, and an n-type semiconductor layer 13 is provided between the first insulating layer 11 and the second insulating layer N12. . The semiconductor layer 13 is non-doped or lightly doped with n-type impurities, and is a relatively high resistance region. A p-type source diffusion layer 1514 and a p-type drain diffusion layer 15 are formed at both ends of the semiconductor Ji13, and the first insulating layer 11 described above is connected to each diffusion layer N13.1.
The sides are surrounded so that the impurity concentration of 4.15 does not change.

16 is a gate electrode, and the gate electrode 16 faces the semiconductor layer 13 with the first insulating layer 11 in between. Therefore, the first insulating layer 11 is used as a gate insulating film,
Further, the gate electrode 16 and the drain diffusion layer 15 are provided so as not to overlap. 17 is an offset low concentration layer, the offset 17 is provided in the semiconductor layer 13,
The second insulating layer 12 and the drain diffusion layer 15 are in contact with each other, while the first insulating fill and the source diffusion layer 14 are in contact with the second insulating layer 12 and the drain diffusion layer 15.
It is different from the two, and is formed by doping with a low concentration of p-type impurity.

18 is a source electrode, 19 is a drain 1, and 20 is a wiring insulating film.

In the above structure, in the present invention, the offset low concentration layer 17, which was conventionally on the side of the gate electrode 16, is provided apart from the gate electrode 16, and the p-channel MO shown in FIG.
In the case of the 3FET, the current takes a route from the source diffusion layer 14 to the lower part of the gate electrode 16, then flows into the offset lightly doped layer 17, and flows out to the drain diffusion N15, as shown by the arrow. Therefore, gate electrode 1
6 and low offset? By separating the 1A degree layer 17, electric field concentration at the 0 point in the figure (i.e., the tip of the offset low concentration layer 17, which has been a problem in the past) is prevented, and breakdown between the gate and drain is prevented. be able to. Incidentally, breakdown occurs when the FET is OF.
F, and at this time breakdown occurs because the slope of the electric field between the gate electrode 16 and the offset low concentration layer 17 causes dielectric breakdown. In order to solve this problem, for example, it is necessary to increase the value of the on-resistance, but this makes it difficult for current to flow, which goes against the goal of lowering the on-resistance.

In contrast, in the present invention, the current flows through the so-called gate electrode 1.
6 flows in the form of injection between the channel directly below the offset low concentration layer 17, so by providing the offset low concentration layer 17 so as to at least partially overlap the gate electrode 16, the on-resistance can be lowered in the saturation region. This makes it possible to achieve both the breakdown requirement and the breakdown requirement.

In addition, in order to reduce on-resistance, there is no need to prepare two or more thicknesses of the first insulating layer 11, which is a gate insulating film, depending on the withstand voltage, which may lead to complication of the manufacturing process. In other words, only one type of thin gate insulating film is required, which simplifies the manufacturing process.

First Example ■ Next, a first example of actually manufacturing a MOS FET based on the above principle will be described. Figure 2(a)~
(g) is a diagram showing the manufacturing process.

First, as shown in FIG. 2(a), a resist 2 is placed on an insulating layer (corresponding to a second insulating layer) 21 made of, for example, 5iO7.
2 is patterned, and impurity ions are implanted into the insulation N21 corresponding to the opening 22a.

Note that the insulating layer 21 is formed on the substrate and is not illustrated. This also applies to the processes shown in FIG. 2(b) and subsequent steps. Here, the opening 22
a corresponds to a region where an offset low concentration layer will be formed later and a region where a drain will be formed. When the ion implantation is completed, the resist 22 is peeled off.

Next, a polycrystalline semiconductor 23 is grown on the insulating layer 21,
Thereafter, the polycrystalline semiconductor 23 is heated from the end to become a single crystal (FIG. 2(b)). In FIG. 2(b), the single crystallized portion is represented by a single crystal semiconductor 24. Further, the position of the ion-implanted impurity is indicated by an x mark, and the number is 25. Next, the single crystal semiconductor 24 is patterned to form a device region (corresponding to a - conductivity type semiconductor layer) 26 (a second
Figure (C)). In this case, the device area 26 is mesa-shaped, but the device area is not limited to this, and may have a LOGO3 structure, for example.

Next, a gate insulating film (first
(equivalent to the insulating layer) 27 is formed. At this time, in the process of forming the insulating film, while controlling the temperature and time to predetermined values, the impurity 25 that has been similarly implanted into the underlying insulating layer 21 is introduced into the semiconductor layer that is the device region 26 as shown by the arrow. to form an offset low concentration layer 28 (second
Figure (d)). Next, a gate electrode 29 is formed and patterned on the top of the gate insulating film 27 (FIG. 2(e)), and then a resist l-30 is patterned in a predetermined area including a part of the upper surface of the gate electrode 29, thereby forming a device. A source region 31 and a drain region 32 are formed by implanting ions of the same conductivity type as the region 26 (FIG. 2(g)). After that, a wiring layer is formed to form an MO with a structure similar to that shown in FIG.
3FET is completed. With this structure, it is possible to obtain the same effect as the principle of the present invention described above.

Kayau! 1 MO3FET having the structure shown in FIG. 1 can be manufactured not only by the manufacturing process shown in FIG. 2 but also by other processes, and this is shown in FIG. 3 as a second embodiment.

What is shown in FIG. 3 is an alternative to the steps shown in FIGS. 2(a) to (d).

First, a single crystal semiconductor 42 is formed on the upper surface of an insulating layer (corresponding to a second insulating layer) 41 on a substrate (not shown) to form a so-called Sol structure (FIG. 3(a)). In addition, Fig. 3 (a
), it is not limited to the SOI structure of processes such as
OS (silicon on 5apphire),
S I MOX (separation by im
A structure such as a planted oxygen (planted oxygen) or a laser SOI may also be used.

Next, a resist 43 is patterned on the single crystal semiconductor 42, and impurity ions are implanted into the single crystal semiconductor 42 corresponding to the region where the offset low concentration layer is to be formed and the region where the drain is to be formed (FIG. 3(b)). ). In the figure, ion implantation into the single crystal semiconductor 42 is indicated by a white arrow, and this portion becomes the offset low concentration layer 44. Then,
After removing the resist 43, epitaxial growth N45 is formed on the upper surface of the single crystal semiconductor 42 (FIG. 3(C)).
. As a result, a semiconductor layer of the same conductivity type is grown on the single crystal semiconductor 42.

Next, the single crystal semiconductor 42 and the epitaxial growth layer 45 are patterned to form a device region 46 (third
Figure (d)). The device region 46 is an offset low concentration layer 4
4 and a semiconductor layer 47, the semiconductor Ji
47 is composed of both the single crystal semiconductor 42 and the epitaxially grown layer 45 described above.

Note that, as a matter of course, the device region 46 may have a mesa type or a LOGO3 structure. Next, a gate insulating film (corresponding to a first insulating layer) 48 is formed around the device region 46 (3rd E(e)).

As a result, a structure similar to that shown in FIG. 2(d) was obtained, and the MO3FET having the structure shown in FIG. 1 was then realized through the same process as shown in FIG. 2(e) and thereafter.

Next, the structure of the MO3FET according to the present invention is not limited to the example shown in FIG. 1, but may have another structure (see FIG. 5).
This will be described as a third embodiment, including the manufacturing process, with reference to FIG. 4.5.

First, the upper surface of silicon (Si) 51 is oxidized to form SiO2
An oxide film 52 consisting of (FIG. 4(a)) is formed.

The oxide film 52 will later become a first insulating layer.

Next, a groove 5 is formed in the oxide film 52 in the region where the gate electrode is to be formed.
2a (FIG. 4(b)), and polysilicon 53 is grown thereon while flattening the entire surface (FIG. 4(C)).
)). After that, impurity diffusion is performed to lower the resistivity of the polysilicon 53, and etching is performed to remove the portion other than the polysilicon 53 in the trench 52a.
The portion shown in FIG. 3 is the gate electrode 54. Furthermore, the upper surface of the oxide film 52 including the surface of the polysilicon 53 is also oxidized by thermal oxidation (FIG. 4(d)). At this time, polysilicon 53
The oxidized portion on the top surface of the gate oxidizes ll! It will be 55. Further, the gate electrode 54 is a so-called buried polysilicon gate, and in reality, the electrode is attached on the front or rear side of the paper in FIG.

Next, polysilicon 56 is grown on the oxide film 52,
Recrystallization is performed by irradiation with a laser beam and heating, and the P-type semiconductor layer 57 of single crystal silicon is patterned to form a device region 58 (FIG. 4(f)). In this example, L
A filled oxide film 59 is formed on the side of the device region 58 to adopt an OGO3 structure. Note that the device area 58
may be formed in a mesa shape. Next, filled oxide film 5
A resist 60 is patterned on the upper surface of the resist 60, and n-type impurity ions are implanted through the resist 60 to form an offset low concentration layer 61 (FIG. 4(g)). After that, another resist 62 is patterned, and n-type impurity ions are implanted through this to form a source region 63 and a drain region 64 (FIG. 4(h)). Next, wiring layers 65 and 66 are formed to make contact with the source region 63 and drain region 64, respectively (FIG. 4(i)).

When the wiring insulating film 67 is formed through the above steps, the result is an N-channel MO with a structure as shown in FIG.
3FET is completed. In this case, the positions of the gate electrode 54 and gate oxide film 55 are reversed from those of the structure shown in FIG. 1, and the filled oxide film 59 serves as the second insulating layer. Of course, even with such a structure, effects similar to those shown in FIG. 1 can be obtained.

In this third embodiment, in order to improve the flatness of the device, the gate electrode 54 is made of a Sin substrate.

However, a structure similar to that of the third embodiment can be realized even if, for example, the oxide film 52 is not grooved and the recrystallized silicon is made to have irregularities.

■Travel to the Earth■ The MOS FET having the structure shown in FIG. 5 can be manufactured by other processes, and this is shown in FIG. 6 as a fourth embodiment. The device shown in FIG. 6 uses a well instead of a buried gate.

First, a resist 72 is patterned on the upper surface of a silicon substrate 71, and impurity ions of a type opposite to that of the silicon substrate 71 are ion-implanted to form a well 73 for a gate electrode (FIG. 6(a)). Next, gate oxide film (first insulation N)
and an oxide film 74 (for example, SiO
6(b)), then polysilicon 75 is deposited on the oxide film 74 and recrystallized by irradiation with laser light and heating to form a semiconductor layer 7 of single crystal silicon.
6 (Fig. 6(C)).

Next, the semiconductor layer 76 is patterned to form a device region 77. In this example, the LOGO3 structure is adopted, so
A filled oxide film 78 is formed on the sides of the device region 77 (FIG. 6(d)). Note that the Debye region 77 may be formed in a mesa shape. Next, a resist 79 is patterned on the upper surface of the filled oxide film 78, and n-type impurity ions are implanted through this to form an offset low concentration [80
(Fig. 6(e)). After that, another resist 81 is patterned, and n-type impurity ions are implanted through this to form a source region 82 and a drain region 83 (FIG. 6(r)). Next, wiring layers 84 and 85 are formed to make contact with the source region 82 and the drain region 83 (see FIG. 6(g)).
)). Through the above steps, a MOS having the structure shown in FIG.
FET can be manufactured.

〔Effect of the invention〕

According to the present invention, electric field concentration in the offset low concentration layer can be effectively prevented, the breakdown voltage between the gate and drain can be improved, and the manufacturing process can be simplified by using only one type of gate insulating film. It is possible to reduce the on-resistance in the saturation region.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a MOS FET showing the principle of the present invention, Figures 2 (a) to (g) are diagrams showing the manufacturing process of the first embodiment of the MOSFET according to the present invention, and Figure 3 (a). ~(e
) is a diagram showing the manufacturing process of the second embodiment of the MOSFET according to the present invention, and FIGS.
Figure 5 showing the manufacturing process of the third embodiment of OSFET
The figure is a sectional view showing another example of the structure of the MOSFET according to the present invention, FIGS. 6(a) to (g) are views showing the manufacturing process of the fourth embodiment of the MOSFET according to the present invention, and FIG. Traditional MO
FIG. 2 is a cross-sectional view of an S FET. 11...First insulating layer, 12...Second insulating layer, 13...Semiconductor layer, 14...Source diffusion layer, 15... ...Drain diffusion layer, 16.29.54...Gate electrode, 17.28
．． 44.61.80...Offset low concentration layer,
18... Source electrode, 19... Drain electrode, 20.67... Wiring insulating film, 21.41... Insulating layer (second insulating layer) ), 26
...Device region, 27.48...Gate insulating film (first insulating layer)
, 31.63.82... Source area, 32.6
4.83...Drain region, 46.58.77
...Device area, 47.57.76...
...Semiconductor layer, 55...Gate oxide film (first insulating layer), 59.78...Filled oxide layer (second insulating layer), 73... Well (gate electrode)
, 74... Oxide film (first insulating layer). ll: First insulating layer Source diffusion layer Drain diffusion layer Gate electrode offset Low concentration layer Source electrode Drain electrode Wiring Insulating film Ion Figure 1 Cross-sectional diagram showing a MOS according to the present invention Figure 2 shows another structural example of an FET

Claims (1)

Claims: A semiconductor layer of one conductivity type in which a channel path is formed is provided between a first insulating layer and a second insulating layer, a source diffusion layer having an impurity of an opposite conductivity type in the semiconductor layer; forming a drain diffusion layer; using the first insulating layer as a gate insulating film, a gate electrode is provided so as not to overlap the drain diffusion layer; and a second insulating layer and a drain diffusion layer are formed in the semiconductor layer. A field effect transistor is constructed by providing an offset low concentration layer of the same conductivity type as the first insulating layer and the source diffusion layer, which is in contact with the first insulating layer and the source diffusion layer. Characteristic semiconductor devices.