JPH02181936A - Formation of fine electrode - Google Patents

Formation of fine electrode

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Publication number
JPH02181936A
JPH02181936A JP124289A JP124289A JPH02181936A JP H02181936 A JPH02181936 A JP H02181936A JP 124289 A JP124289 A JP 124289A JP 124289 A JP124289 A JP 124289A JP H02181936 A JPH02181936 A JP H02181936A
Authority
JP
Japan
Prior art keywords
electrode
insulating film
resist
semiconductor substrate
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP124289A
Other languages
Japanese (ja)
Inventor
Norihiko Samoto
典彦 佐本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP124289A priority Critical patent/JPH02181936A/en
Publication of JPH02181936A publication Critical patent/JPH02181936A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To prevent an electrical characteristic in an electrode part from being deteriorated even when a width of an insulating film deciding an electrode-length size is made small and to prevent a yield from being lowered by a method wherein an interface of a semiconductor substrate in which the electrode is formed is formed so as not to come into contact with a resist. CONSTITUTION:An insulating film 11 deciding a gate-length size is formed on a semiconductor substrate 10; a resist 12 does not come into direct contact with the substrate 11 in a part in which a gate electrode is formed; a yield is not deteriorated by a residual scum of the resist. In order to form a pattern, for upper-part electrode use, which reduces a resistance, the insulating film 11 is exposed by using an ion beam whose energy has been controlled; the film is etched to an extent that a resist pattern does not reach the semiconductor substrate 10. Then, the insulating film 11 is removed; an electrode metal 16 is evaporated; a T-shaped electrode can be formed by a lift-off method. The gate-length size of the obtained T-shaped electrode and a size of the upper- part electrode are exposed to light individually; since their sizes are controlled separately, they can be set to arbitrary values.

Description

【発明の詳細な説明】 [産業上の利用分野1 本発明は微細用(車の形成法に関し、特に抵抗の低減化
された断面T字型微細電極の形成法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method for forming micro electrodes, and particularly to a method for forming micro electrodes with a T-shaped cross section with reduced resistance.

[従来の技術] 従来、微細電極の抵抗を下げる電極の形成方法として、
特公昭61−77370号公報「パターン形成法」に記
載の方法が知られている。前記公報記載の形成法を第2
図(a)〜(C)に示す。即ち、まず第2図(a)に示
すように低感度のポジ型レジスト21を半導体基板20
上に塗イ17シ、ついで高感度のポジ型レジスト22を
上記低感度ポジ型レジスト21上に塗布し、電子線23
により露光する。次いで現像して、1字型のレジストパ
ターンをjqだ後、第2図(b)に示すように金属24
を蒸着し、有機洗浄によりレジスト21.22およびレ
ジスト22上の蒸着金属24を除去することによって、
第2図(C)に示すようにTV型の電極25が形成され
、電極抵抗の低減化が図られている。
[Prior Art] Conventionally, as a method for forming electrodes to reduce the resistance of fine electrodes,
A method described in Japanese Patent Publication No. 61-77370 entitled "Pattern Formation Method" is known. The formation method described in the above publication was used as the second method.
Shown in Figures (a) to (C). That is, as shown in FIG. 2(a), a low-sensitivity positive resist 21 is first applied to the semiconductor substrate 20.
Then, a high-sensitivity positive resist 22 is coated on the low-sensitivity positive resist 21, and an electron beam 23 is applied on top of the low-sensitivity positive resist 21.
Expose to light. Next, after developing and forming a 1-shaped resist pattern, a metal 24 is formed as shown in FIG. 2(b).
and removing the resist 21, 22 and the deposited metal 24 on the resist 22 by organic cleaning.
As shown in FIG. 2(C), a TV-type electrode 25 is formed to reduce electrode resistance.

[発明が解決しようとする課題] 以上述べた形成法は、電極の抵抗が小さくできる点で従
来の単層レジストによって形成された電極に比べて改善
されているものの、ゲート長は、下層レジスト開口幅で
決定されるため、レジスト厚が厚くなるに従って、0.
25 /1ffl以下のゲート長を得ることが難しくな
る。
[Problems to be Solved by the Invention] Although the above-described formation method is improved over electrodes formed using conventional single-layer resist in that the resistance of the electrode can be reduced, the gate length is Since it is determined by the width, as the resist thickness increases, the value decreases to 0.
It becomes difficult to obtain a gate length of 25/1ffl or less.

また、半導体基板上に直接レジストが塗布形成されてい
るため、レジスト開口部が小さくなるにつれて該開口部
にレジスト残りが存在するようになり、このため0.2
卯以下の電極形成においては、電極と半導体基板の接触
が悪く、電気的特性の劣化や歩留まりの劣化が生じゃと
いう問題点があった。
In addition, since the resist is directly coated and formed on the semiconductor substrate, as the resist opening becomes smaller, some resist remains in the opening.
In the formation of electrodes below the rabbit level, there was a problem in that the contact between the electrodes and the semiconductor substrate was poor, resulting in deterioration of electrical characteristics and yield.

本発明の目的は、このような従来の欠点を除去せしめて
、抵抗の低減化された電極を歩留まりよく形成する方法
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for eliminating such conventional drawbacks and forming an electrode with reduced resistance with a high yield.

[課題を解決するための手段] 本発明は、半導体基板上に二酸化ケイ素絶縁膜を形成し
、該絶縁膜をパターニングして電(垂下部に相当する所
望寸法を残した絶縁膜パターンを形成する工程と、該絶
縁膜パターン上にポジ型レジストを塗イ[↑形成りる工
程と、前記半導体基板には達しないか前記絶縁膜パター
ンには達する飛程を有するエネルギーのイオンビームて
、前記絶縁膜パターンを中心として電極の上部寸法に相
当する所定の領域を露光・現像して前記絶縁膜パターン
の頭出しを行う工程と、この頭出しされた絶縁膜パター
ンをウェットエツチングにJ:り除去する工程と、電極
金属を蒸着する工程と、前記レジス1へおよび該レジス
l〜上の不要金属を除去して断面T字型の金属パターン
を形成する工程とを備えてなることを特徴とする微細電
(※の形成法である。
[Means for Solving the Problems] The present invention involves forming a silicon dioxide insulating film on a semiconductor substrate, and patterning the insulating film to form an insulating film pattern leaving a desired dimension corresponding to the drooping portion. a step of forming a positive resist on the insulating film pattern; and a step of forming a positive resist on the insulating film pattern; A step of locating the insulating film pattern by exposing and developing a predetermined area corresponding to the upper dimension of the electrode centering on the film pattern, and removing the oriented insulating film pattern by wet etching. a step of vapor depositing an electrode metal; and a step of removing unnecessary metal on the resist 1 and above the resist 1 to form a metal pattern having a T-shaped cross section. Electron (*This is the formation method.

[作用] 本発明においては、ゲート長司法を決める絶縁膜を半導
体基板上に形成してあり、ゲート電極形成部においてレ
ジメ1〜と基板が直接接触していないため、レジストの
スカム残りによる歩留まりの劣化は生じない。また、抵
抗を低減させる上部電極用パターンの形成については、
エネルギー制御されたイオンビームを用いて、絶縁膜を
露呈さU、かつレジストパターンが半導体旦仮まで達し
ない程度にエツチングすることによって行う。次いで絶
縁膜を除去して、電極金属を蒸着することによりリフト
オフ法での1字型電極の形成が可能となる。iqられる
1字型電極のゲート長寸法と上部電極寸法とは、それぞ
れ単独に露光され、その寸法は別々に制御されているの
で、任意の値に設定することができる。
[Function] In the present invention, since the insulating film that determines the gate length is formed on the semiconductor substrate, and the substrate is not in direct contact with the regime 1~ in the gate electrode forming area, yield is reduced due to resist scum remaining. No deterioration occurs. Regarding the formation of the upper electrode pattern to reduce resistance,
Etching is performed using an energy-controlled ion beam to the extent that the insulating film is exposed and the resist pattern does not reach the semiconductor layer. Next, by removing the insulating film and depositing an electrode metal, it becomes possible to form a single-shaped electrode using a lift-off method. The gate length dimension and the upper electrode dimension of the single-shaped electrode, which are iq, are each exposed independently and the dimensions are controlled separately, so they can be set to arbitrary values.

[実施例] 次に図面を参照して、本発明の実施例について説明する
[Example] Next, an example of the present invention will be described with reference to the drawings.

第1図(a)〜((])は、本発明の一実施例を工程順
に示す電極部の概略断面図である。まず、第1図(a)
に示すように半導体基板10上に二酸化ケイ素(Si0
2)の絶縁膜11を2000人から5000人の厚さに
形成し、次いでネガ型レジスト12を前記絶縁膜11上
に塗布形成する。次いで、第1図(b)に示すように、
ネガ型レジスト12を露光・現像した後、残ったネガ型
しジスlへ12をマスク1;3として、露呈した前記絶
縁1tA11をエッヂング除去して前記マスク13下の
絶縁1漠11をダミーゲート・14として形成する。
FIGS. 1(a) to (()) are schematic cross-sectional views of an electrode part showing an embodiment of the present invention in the order of steps. First, FIG. 1(a)
As shown in the figure, silicon dioxide (Si0
2) The insulating film 11 is formed to a thickness of 2,000 to 5,000 wafers, and then a negative resist 12 is coated on the insulating film 11. Next, as shown in FIG. 1(b),
After exposing and developing the negative resist 12, using the remaining negative resist 12 as a mask 1;3, the exposed insulation 1tA11 is removed by etching, and the insulation 11 under the mask 13 is replaced with a dummy gate. 14.

この後、第1図(C)に示すように、マスク13として
用いたネガ型レジストを酸素(02)プラズマおよび有
機洗浄によって除去した後、ポジ型レジスト(例えばP
MMA)15を前記半導体基板10上に、絶縁膜で形成
され、たダミーゲート14が覆われるように1βmの厚
さに塗布形成する。次いで、前記ダミーゲート14を中
心に含み、かつダミーグ1へ14まで達するが、基板1
0までは達しない飛程をもつイオンビーム18で前記ポ
ジ型しジス1〜15を露光する。例えば、ポジ型レジス
ト15としてPMMAを用いれば、260 keV、 
S +  のイオンエネルギーとイオン種のとき0.8
1JInの飛程となる。こうすることにより、現像後に
は、第1図(d)に示すように、基板10まで達するこ
とのない聞ロバターン19が形成でき、かつダミーグー
1〜14の頭出しが可能でおる。
Thereafter, as shown in FIG. 1C, after removing the negative resist used as the mask 13 by oxygen (02) plasma and organic cleaning, the positive resist (for example, P
MMA) 15 is coated on the semiconductor substrate 10 to a thickness of 1βm so as to cover the dummy gate 14 formed of an insulating film. Next, it includes the dummy gate 14 in the center and reaches up to the dummy gate 14, but the substrate 1
The positive type resistors 1 to 15 are exposed with an ion beam 18 having a range that does not reach zero. For example, if PMMA is used as the positive resist 15, 260 keV,
When the ion energy and ion species of S + are 0.8
The range is 1 JIn. By doing so, after development, as shown in FIG. 1(d), a groove pattern 19 that does not reach the substrate 10 can be formed, and it is possible to locate the dummy goose 1 to 14.

次いで、第1図(e)に示ゴようにダミーゲート14を
エツチングにより除去する。次いで、第1図([)に示
すように、電極金属16、例えばアルミニウム(Aβ)
を蒸着する。次いで、第1図((])に示すように、有
機洗浄おるいは酸素(02)プラズマによって前記ポジ
型しジス1へ15および該レジスト15上の不要電極金
属16を除去することによって断面T字型低抵抗電極1
7を得ることができる。
Next, as shown in FIG. 1(e), the dummy gate 14 is removed by etching. Next, as shown in FIG. 1 ([), the electrode metal 16, for example aluminum (Aβ)
Deposit. Next, as shown in FIG. 1 (()), the positive type resist 15 and the unnecessary electrode metal 16 on the resist 15 are removed by organic cleaning or oxygen (02) plasma, thereby forming a cross section T. Shape low resistance electrode 1
You can get 7.

なあ、上記実施例で述べたイオン種とエネルギは一例で
あり、所定のレジメl〜厚において、ダミーゲートの頭
出しが可能な飛程をもつイオン種であれば、3iイオン
の他にBeイオンやAuイオン等でもよく、そのエネル
ギーはレジストの厚さに応じて100〜300 keV
の間で可変である。
Note that the ion species and energy described in the above example are just examples, and as long as the ion species has a range that allows the dummy gate to be located in a predetermined regime l~thickness, Be ions in addition to 3i ions can be used. or Au ions, etc., and the energy is 100 to 300 keV depending on the thickness of the resist.
It is variable between.

また、電4ifi金属は他にチタン(T i ) 、白
金(Pt)、金(Au)35るいはこれらの組み合わせ
など、電極として用いることのできるものであればよい
Further, the metal may be any other material that can be used as an electrode, such as titanium (T i ), platinum (Pt), gold (Au), or a combination thereof.

[発明の効果] 以上説明したように、本発明の微細電極の形成法によれ
ば電極が形成される半導体基板の界面はレジストと接し
ていないので、電極長寸法を決める絶縁膜幅を小さくし
ても電極部における電気的特性の劣化や歩留まりの低下
を生じることがない。
[Effects of the Invention] As explained above, according to the method for forming a fine electrode of the present invention, the interface of the semiconductor substrate on which the electrode is formed is not in contact with the resist, so the width of the insulating film, which determines the length of the electrode, can be reduced. However, the electrical characteristics of the electrode portion do not deteriorate or the yield decreases.

また、電極長を決定する露光と張り出し爪を形成する露
光が別々に制御されるので、電極長が例えば0.251
JIn以下に短くなっても電極下部の寸法および上部張
り出し母を自由に制御でき、充分な低抵抗の電1〜形成
が可能となる。
In addition, since the exposure that determines the electrode length and the exposure that forms the overhanging claw are controlled separately, the electrode length can be set to 0.251, for example.
Even if the length is shorter than JIn, the dimensions of the lower part of the electrode and the protrusion of the upper part can be freely controlled, making it possible to form electrodes 1~ with sufficiently low resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を工程順に示づ電(へ部の概
略断面図、第2図は従来例による微細電極の形成方法を
工程順に示す電極部の概略断面図である。 10、20・・・半導体基板   11・・・絶縁膜1
2・・・ネガ型レジスト   13・・・マスク14・
・・ダミーゲート15・・・ポジ型レジスト16・・・
電極金属 17・・・断面T′?−型低抵抗電極 18・・・イオンビーム    19・・・間ロバター
ン21・・・低感度ポジ型レジスト 22・・・高感度ポジ型しジメ(〜 23・・・電子線       24・・・蒸着金属2
5・・・電4へ
FIG. 1 is a schematic cross-sectional view of an electrode part showing an example of the present invention in the order of steps, and FIG. 2 is a schematic cross-sectional view of the electrode part showing a conventional method of forming a fine electrode in the order of steps. , 20... Semiconductor substrate 11... Insulating film 1
2... Negative resist 13... Mask 14.
...Dummy gate 15...Positive resist 16...
Electrode metal 17...cross section T'? - type low resistance electrode 18...Ion beam 19...Interval pattern 21...Low sensitivity positive resist 22...High sensitivity positive resist (~ 23...Electron beam 24...Vapor deposited metal 2
5...to Den 4

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上に二酸化ケイ素絶縁膜を形成し、該
絶縁膜をパターニングして電極下部に相当する所望寸法
を残した絶縁膜パターンを形成する工程と、該絶縁膜パ
ターン上にポジ型レジストを塗布形成する工程と、前記
半導体基板には達しないが前記絶縁膜パターンには達す
る飛程を有するエネルギーのイオンビームで、前記絶縁
膜パターンを中心として電極の上部寸法に相当する所定
の領域を露光・現像して前記絶縁膜パターンの頭出しを
行う工程と、この頭出しされた絶縁膜パターンをウェッ
トエッチングにより除去する工程と、電極金属を蒸着す
る工程と、前記レジストおよび該レジスト上の不要金属
を除去して断面T字型の金属パターンを形成する工程と
を備えてなることを特徴とする微細電極の形成法。
(1) A step of forming a silicon dioxide insulating film on a semiconductor substrate, patterning the insulating film to form an insulating film pattern leaving a desired dimension corresponding to the lower part of the electrode, and applying a positive resist on the insulating film pattern. and forming a predetermined area corresponding to the upper dimension of the electrode around the insulating film pattern with an ion beam of energy having a range that does not reach the semiconductor substrate but reaches the insulating film pattern. A step of locating the insulating film pattern by exposure and development, a step of removing the locating insulating film pattern by wet etching, a step of vapor depositing an electrode metal, and a step of removing the resist and unnecessary material on the resist. A method for forming a microelectrode, comprising the step of removing metal to form a metal pattern having a T-shaped cross section.
JP124289A 1989-01-09 1989-01-09 Formation of fine electrode Pending JPH02181936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP124289A JPH02181936A (en) 1989-01-09 1989-01-09 Formation of fine electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP124289A JPH02181936A (en) 1989-01-09 1989-01-09 Formation of fine electrode

Publications (1)

Publication Number Publication Date
JPH02181936A true JPH02181936A (en) 1990-07-16

Family

ID=11495990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP124289A Pending JPH02181936A (en) 1989-01-09 1989-01-09 Formation of fine electrode

Country Status (1)

Country Link
JP (1) JPH02181936A (en)

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