JPH02180054A - Container for semiconductor - Google Patents
Container for semiconductorInfo
- Publication number
- JPH02180054A JPH02180054A JP33559588A JP33559588A JPH02180054A JP H02180054 A JPH02180054 A JP H02180054A JP 33559588 A JP33559588 A JP 33559588A JP 33559588 A JP33559588 A JP 33559588A JP H02180054 A JPH02180054 A JP H02180054A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- metallized
- layer
- container
- metallized layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000000919 ceramic Substances 0.000 claims abstract description 11
- 238000007639 printing Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- NEIHULKJZQTQKJ-UHFFFAOYSA-N [Cu].[Ag] Chemical compound [Cu].[Ag] NEIHULKJZQTQKJ-UHFFFAOYSA-N 0.000 description 3
- 238000005219 brazing Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高周波領域で使用される半導体用容器の構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a semiconductor container used in a high frequency region.
従来の技術
従来、高周波半導体素子に使用される半導体用容器は、
通常第３図に示すような構造のものが用いられている。Conventional technology Conventionally, semiconductor containers used for high-frequency semiconductor devices are
Usually, a structure as shown in FIG. 3 is used.
図中、２１は誘電体基板、２２．２３．２４はそれぞれ
裏面、側面、表面のメタライス層、２５は半導体素子搭
載部領域のメタライズ層、２６は銀銅ろう材、２７はリ
ード電極、２８は壁部材、３１は半導体素子、３２は金
線、３０はキャップ部、２９は金銭半田をそれぞれ示す
。In the figure, 21 is a dielectric substrate, 22, 23, and 24 are metallized layers on the back, side, and front surfaces, respectively, 25 is a metallized layer in the semiconductor element mounting area, 26 is a silver-copper brazing material, 27 is a lead electrode, and 28 is a metallized layer. In the wall member, 31 is a semiconductor element, 32 is a gold wire, 30 is a cap portion, and 29 is money solder.
発明が解決しようとする課題
しかしながら、第３図に示すような従来構造の半導体用
容器においては、金錫半田の封止部分２９と電極のメタ
ライズ部との間の静電容量を低減するために、壁部材２
８はある程度の厚みを必要とする。前記静電容量の値は
、半導体装置の高周波性能と密接に関係しており、これ
を増加させないことが重要である。このような構造にお
いては、壁部材２８の上面は、半導体素子搭載面よりも
高くなり、さらに半導体素子搭載後も半導体素子の表面
よりも高くなっている。Problems to be Solved by the Invention However, in a semiconductor container having a conventional structure as shown in FIG. , wall member 2
8 requires a certain degree of thickness. The capacitance value is closely related to the high frequency performance of the semiconductor device, and it is important not to increase it. In such a structure, the upper surface of the wall member 28 is higher than the semiconductor element mounting surface, and even after the semiconductor element is mounted, the upper surface of the wall member 28 is higher than the surface of the semiconductor element.
半導体素子３１を半導体用容器に搭載する場合には、半
導体素子３１を適当な治具（以下コレット〉で吸着し、
半導体用容器のメタライズ領域に熱圧着、もしくはペー
スト等で接着する。その後、適当な治具（以下ツール）
を用いて半導体素子上の電極と半導体用容器のメタライ
ズ層とを金線で接続する。この場合、前記コレット、ツ
ールは壁部材の内側に入るために、その形状、動作は著
しく制約される。このような構造においては、特別な設
備、治工具が必要となり、その生産性は通常の半導体生
産に比して著しく低い。When mounting the semiconductor element 31 in a semiconductor container, the semiconductor element 31 is sucked with an appropriate jig (hereinafter referred to as collet),
Adhere to the metallized area of the semiconductor container by thermocompression bonding or paste. After that, use a suitable jig (hereinafter referred to as “tool”)
The electrode on the semiconductor element and the metallized layer of the semiconductor container are connected using a gold wire. In this case, since the collet and tool enter inside the wall member, their shape and operation are significantly restricted. Such a structure requires special equipment and jigs, and its productivity is significantly lower than in normal semiconductor production.
本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記課題
を解決することを可能とした新規な半導体用容器を提供
することにある。The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a novel container for semiconductors that makes it possible to solve the above-mentioned problems inherent in the conventional technology.
発明の従来技術に対する相違点
本発明においては、スルーホールとセラミック印刷層と
を組み合せて使用することにより、半導体装置の電極と
気密封止部との間の静電容量を増加させずに、気密封止
部と半導体用容器のメタライズ層とをほぼ同一平面上に
することが可能となる。従来の構造では、半導体用容器
の壁部材を薄くすると、前記静電容量が増加し、素子性
能が劣化するのに対して、本発明による構造では従来必
要であった壁部材を必要としない。Differences between the Invention and the Prior Art In the present invention, by using a combination of through-holes and a ceramic printed layer, air can be reduced without increasing the capacitance between the electrodes of the semiconductor device and the hermetic seal. It becomes possible to make the sealing part and the metallized layer of the semiconductor container substantially on the same plane. In the conventional structure, when the wall member of the semiconductor container is thinned, the capacitance increases and the device performance deteriorates, whereas the structure according to the present invention does not require the conventional wall member.
課題を解決するための手段
前記目的を達成する為に、本発明による半導体用容器の
構造は、誘電体基板の表面と裏面のメタライズ層を ル
ーホールによって接続することと、封止用のメタライズ
層を薄いセラミック印刷層を介して誘電体基板の表面に
設けることを特徴としている。Means for Solving the Problems In order to achieve the above object, the structure of the semiconductor container according to the present invention includes connecting the metallized layers on the front and back surfaces of the dielectric substrate with through holes, and connecting the metallized layer for sealing. It is characterized by being provided on the surface of a dielectric substrate via a thin ceramic printing layer.
セラミック印刷層は、半導体用容器の電極のメタライズ
領域と、気密封止のメタライズ領域とが接触することを
防ぐために設けられ、これにより、上記の両メタライズ
層を近接して設置することができ、半導体用容器の形状
が大きくなることを防ぐことができる。The ceramic printing layer is provided to prevent the metallized area of the electrode of the semiconductor container from contacting the metallized area of the hermetically sealed seal, thereby allowing both of the metallized layers to be placed close to each other. It is possible to prevent the shape of the semiconductor container from becoming large.
実施例
次に本発明をその好ましい各実施例について図面を参照
しながら具体的に説明する。Embodiments Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
第１図を参照するに、参照番号１は誘電体基板、２．３
．４．５は誘電体基板１に設けられたメタライズ層、６
は銀銅ろう材、７は外部リード電極、８は壁部材、９は
半導体用容器とキャップとを接着する金銭等の低融点金
属、１０はキャップ、１１は半導体素子、１２は金線、
１３はスルーポールをそれぞれ示している。１５は封止
のためのメタライズ層を示し、１４は、２０〜５０ミク
ロンの厚さを有するセラミック層であり、印刷によって
形成される。このセラミック印刷層１４は、近接した他
のメタライズ層（図中参□照番号５他）との接触を防止
するためのものである。また、半導体素子１１は、スル
ーホール１３、裏面のメタライズ層２を通して、外部リ
ード７に電気的に接続されている。Referring to FIG. 1, reference number 1 is a dielectric substrate, 2.3
．． 4.5 is a metallized layer provided on the dielectric substrate 1, 6
7 is a silver copper brazing material, 7 is an external lead electrode, 8 is a wall member, 9 is a low melting point metal such as money for bonding the semiconductor container and the cap, 10 is a cap, 11 is a semiconductor element, 12 is a gold wire,
13 indicates through poles. 15 indicates a metallized layer for sealing, and 14 is a ceramic layer having a thickness of 20 to 50 microns, which is formed by printing. This ceramic printing layer 14 is for preventing contact with other adjacent metallized layers (reference □ number 5 in the figure and others). Further, the semiconductor element 11 is electrically connected to the external lead 7 through the through hole 13 and the metallized layer 2 on the back surface.
これによって、メタライズ層５とメタライズ層１５は相
対する領域を有さないために両メタライズ層間の静電容
量値を抑制することができる。As a result, since the metallized layer 5 and the metallized layer 15 do not have opposing regions, the capacitance value between the two metallized layers can be suppressed.
第２図は本発明による第２の実施例を示す断面図である
。FIG. 2 is a sectional view showing a second embodiment of the present invention.
第２図において、本発明に係る半導体用容器の第２の実
施例は、外部リード電極を有しないり−ドレスパッケー
ジであり、裏面にはスルーホール１３部の気密保持のた
めのセラミック印刷層重が設けられている。In FIG. 2, the second embodiment of the semiconductor container according to the present invention is a dress package that does not have an external lead electrode, and the back side has a ceramic printed layer for keeping the through hole 13 airtight. is provided.
発明の詳細
な説明したように、本発明に係る半導体用容器によれば
各電極間の静電容量を増加させることなく、かつ、半導
体用容器の形状を大きくぜずに、半導体素子の搭載面と
気密封止のためのメタライズ層とをほぼ同一平面上にす
ることが可能である。これにより、半導体用容器に半導
体素子を搭載する工程及び搭載された半導体素子の電極
と半導体用容器のメタライズ層とを金属細線で接続する
工程等の組立工程において、特別な設備、治工具を必要
とせず、通常市販されている設備を使用することができ
る。また、壁部材がないことにより、組立工程の自由度
が大きく、生産性が著しく改善される。As described in detail, the semiconductor container according to the present invention can improve the mounting surface of a semiconductor element without increasing the capacitance between each electrode and without significantly deforming the shape of the semiconductor container. It is possible to make the metallized layer for hermetic sealing and the metallized layer substantially on the same plane. As a result, special equipment and jigs are required in the assembly process, such as the process of mounting a semiconductor element in a semiconductor container and the process of connecting the electrodes of the mounted semiconductor element and the metallized layer of the semiconductor container with thin metal wires. Instead, commercially available equipment can be used. Further, since there is no wall member, the degree of freedom in the assembly process is increased, and productivity is significantly improved.
第１図は本発明による第１の一実施例を示す断面図、第
２図は本発明による第２の実施例を示す断面図、第３図
は従来の技術による例を示す断面図である。
１．２１・・・誘電体基板、２．３．４．５．２２．２
３．２４．２５・・・誘電体基板に設けられたメタライ
ス層、６．２６ ・・銀銅ろう材、 ７−２７・・・外
部リード電極、９．２９・・・半導体用容器とキャップ
とを接着する金錫等の低融点金属、１０．３０・・・キ
ャップ、１１．３１・・・半導体素子、１２．３２・・
・金線、１３・・・スルーボール、１４・・・セラミッ
ク印刷層、１５・・・メタライズ層、１６・・裏面のセ
ラミック印刷層、２８・・・壁部材特許出願人 日本
電気株式会社
代 理 人 弁理士 熊谷雄太部FIG. 1 is a sectional view showing a first embodiment according to the present invention, FIG. 2 is a sectional view showing a second embodiment according to the present invention, and FIG. 3 is a sectional view showing an example according to a conventional technique. . 1.21...Dielectric substrate, 2.3.4.5.22.2
3.24.25...Metal rice layer provided on dielectric substrate, 6.26...Silver copper brazing material, 7-27...External lead electrode, 9.29...Semiconductor container and cap Low melting point metal such as gold and tin for adhesion, 10.30... Cap, 11.31... Semiconductor element, 12.32...
・Gold wire, 13... Through ball, 14... Ceramic printing layer, 15... Metallized layer, 16... Ceramic printing layer on back side, 28... Wall member patent applicant NEC Corporation representative People Patent Attorney Yutabe Kumagai
Claims (1)
するためのメタライズ層が前記誘電体基板に設けられた
スルーホールによって裏面メタライズ層と接続され、か
つ、前記誘電体基板の表面上にキャップ接着のためのメ
タライズ層が、セラミック印刷層を介して設けられてい
ることを特徴とする半導体用容器。A metallized layer for connecting to a semiconductor element electrode provided on the front surface of the dielectric substrate is connected to the back metallized layer through a through hole provided in the dielectric substrate, and a cap is provided on the surface of the dielectric substrate. A semiconductor container characterized in that a metallized layer for adhesion is provided via a ceramic printing layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33559588A JPH02180054A (en) | 1988-12-29 | 1988-12-29 | Container for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33559588A JPH02180054A (en) | 1988-12-29 | 1988-12-29 | Container for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02180054A true JPH02180054A (en) | 1990-07-12 |
Family
ID=18290345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33559588A Pending JPH02180054A (en) | 1988-12-29 | 1988-12-29 | Container for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02180054A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808357A (en) * | 1992-06-02 | 1998-09-15 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
-
1988
- 1988-12-29 JP JP33559588A patent/JPH02180054A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808357A (en) * | 1992-06-02 | 1998-09-15 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
| US6031280A (en) * | 1992-06-02 | 2000-02-29 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
| US6271583B1 (en) | 1992-06-02 | 2001-08-07 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
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