JPH02178975A - Mos type semiconductor device - Google Patents

Abstract

PURPOSE:To equalize the inflow of currents from the corners of a channel, and to increase resistance by forming the contour of the internal periphery of a gate film in to a regular polygon with sides of five or more and shaping a main electrode in staggered arrangement by displating the position of the main electrode between adjacent rows. CONSTITUTION:A contour on the outside of an N<+> source layer in the surface section of a P layer composed of a P<-> channel layer 2 and a P<+> low resistance layer 3 in a cell formed to the surface section of an N<-> layer 1, a contour on the inside of a polycrystalline silicon gate film 6 superposed onto the source layer, and a contour on the inside of a PSG film 7 covering the upper section of the film 6 are shaped to a regular octagon. The arrangement of a contact hole 8 in which the P<-> channel layer 2, the P<+> low resistance layer 3, the source layer 4 nd a source electrode are brought into contact is formed in staggered arrangement by displacing positions in each row. Consequently, cells are shaped in staggered arrangement, thus reducing a burden area. Accordingly, the inflow of currents from the corners of a channel is equalized approximately, thus increasing resistance.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is directed to a power MOSFET or an insulated gate bipolar transistor in which a plurality of main electrodes are arranged in a straight line on one surface of a semiconductor substrate. The present invention relates to a MOS type semiconductor device in which a plurality of columns are provided, and a gate film forming a channel outside a layer in contact with each main electrode surrounds the main electrode with an insulating film sandwiched therebetween on a semiconductor substrate.

[Conventional technology]

Figure 2 shows (a), (b), (C1 power vertical MO
Four cells of the MOS structure of the SFET or insulated gate bipolar transistor are shown, and C in the plan view f8+ is shown.
As shown in fb) in the cross-sectional view taken along the line C, one cell provided on the surface of the N-layer 1 consists of a P layer consisting of a P-channel layer 2 and a low resistance layer 3, and a cell provided on the surface of the P-layer. A polycrystalline silicon gate film 6 and a polycrystalline silicon gate film 6 are provided on the channel layer 2 sandwiched between the N source layer 4 and the N source layer 4N- layer 1, with a gate oxide film 5 interposed therebetween. membrane 6
and a PSG insulating film 7 covering. A source electrode contacts the 91 layer 3 and the source layer 4 through a contact ball 8 formed in the PSG film 7 . In this structure, D in figure (a)
As shown in Figure (C), which is a cross-sectional view taken along the -D line, in the area where there is no MOS cell, the polycrystalline silicon film 6 and P
[Problem to be Solved by the Invention] Between the gate and source electrodes of a semiconductor device having the above-mentioned MOS structure, the SG film 7 covers the entire surface, and therefore these films surround each cell. When a voltage is applied to the source layer 4 and the N− layer 1
An N channel is formed in the channel layer 2 sandwiched between the two layers. In this case, a large amount of channel current tends to flow from the corner of the channel due to the electric field of the wide gate electrode that is applied behind the corner of the inner edge of the rectangular gate, and the parasitic transistor is turned on at that point. There was a problem that destruction was unlikely to occur.

An object of the present invention is to provide an MO in which a large amount of channel current does not flow into the corners of the inner edge of the gate, thereby preventing destruction.
An object of the present invention is to provide an S-type semiconductor device.

[Failure to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a plurality of rows consisting of a plurality of main electrodes located in a straight line on one surface of a semiconductor substrate, and a channel is formed on the outside of the layer in contact with each main electrode. In a MOS type semiconductor device in which a gate film surrounds a main electrode with an insulating film on a semiconductor substrate, the inner peripheral edge of the gate film has a regular polygonal shape of pentagon or more, and the main electrode between adjacent columns By shifting the positions of the main electrodes, the main electrodes are arranged in a staggered manner.

[Effect]

By making the outline of the inner edge of the electrode into a polygon of pentagon or more, the corners of the inner edge become obtuse angles, and the width of the gate electrode between the main electrodes arranged in a staggered arrangement becomes nearly uniform. Since there are no locations where the current flowing into the channel is concentrated, there are no locations where the parasitic transistor is easily turned on and destroyed, and the withstand capability is improved.

〔Example〕

Figure 1 (al, (bl, +c+) shows an embodiment of the present invention, Figure (al is a plan view, Figure (bl is (+11 A-
1 (C) is a cross-sectional view of ta+ taken along line 13-B, and parts common to those in FIG. 2 are given the same reference numerals. In this case, the P of the cell provided on the surface of the N-layer 1 is
- The outer contour of the N source layer on the surface of the P layer consisting of the channel layer 2 and the P1 low resistance layer 3, the inner contour of the polycrystalline silicon gate film 6 that overlaps it, and the PSG layer that covers it.
The inner contour of the membrane is a regular octagon.

The contact holes 8 in contact with the P-channel layer 2, P''' low resistance layer 3, source layer 4, and source electrode are arranged in a staggered manner by shifting their positions in each column. Even if you just arrange it vertically and horizontally,
Simply changing the outline of the inner edge of the gate from a square to a hexagon reduces the gate area behind the channel corners by 13%, and by staggering the cells, the area covered by the channel is reduced by 60%6. Current flow from the corners becomes nearly uniform, improving withstand capability.

In the above embodiment, the shape of the cell is a regular octagon, but the area covered by the corners of the channel becomes smaller as the number of corners increases and the angle of the corner becomes obtuse. Therefore, even a regular pentagon is more effective than a square, and a circle is the most effective.

〔Effect of the invention〕

According to the present invention, the contour of the inner edge of the gate of each cell of a MOS semiconductor device including a large number of cells of a MOS structure arranged in a plurality of rows on one surface of a semiconductor substrate, in other words, the contour of the outer circumference of a channel, is changed from a rectangular shape to a rectangular shape. By making it more than a regular pentagon with many shapes and using a staggered arrangement, the gate area borne by the outer corners of the channel is equalized, and the current that flows from winter use becomes nearly uniform, making it difficult to cause damage due to concentration of channel current. (This improves tolerance.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention (al is a plan view (b
) is a cross-sectional view of (al) along line A-A, (C) is (a
2 shows a conventional MOS semiconductor device, (a) is a plan view, (b) is a sectional view taken along line CC in (a), and (C ) is a sectional view taken along line DD in (a). 1: N-layer, 2: P-channel layer, 4: N1 source layer, 5: Gate oxide film, 6: Gate film, 7: PSG film, 8
: Contact hole.

Claims (1)

[Claims] (1) A row consisting of a plurality of main electrodes located in a straight line is provided on one surface of a semiconductor substrate, and a gate film for forming a channel is formed on the outside of the layer in contact with each main electrode, and an insulating film is formed on the semiconductor substrate. In the case where the main electrodes are sandwiched between them, the outline of the inner peripheral edge of the gate film is a regular polygon of pentagon or more, and the main electrodes are arranged in a staggered manner by shifting the position of the main electrodes between adjacent columns. A MOS type semiconductor device characterized by: